JP6633243B2 - メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 - Google Patents
メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 Download PDFInfo
- Publication number
- JP6633243B2 JP6633243B2 JP2019504126A JP2019504126A JP6633243B2 JP 6633243 B2 JP6633243 B2 JP 6633243B2 JP 2019504126 A JP2019504126 A JP 2019504126A JP 2019504126 A JP2019504126 A JP 2019504126A JP 6633243 B2 JP6633243 B2 JP 6633243B2
- Authority
- JP
- Japan
- Prior art keywords
- dimm
- memory module
- circuit board
- ground plane
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0236—Electromagnetic band-gap structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
- H05K1/0225—Single or multiple openings in a shielding, ground or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662367836P | 2016-07-28 | 2016-07-28 | |
| US62/367,836 | 2016-07-28 | ||
| US15/659,187 | 2017-07-25 | ||
| US15/659,187 US10349513B2 (en) | 2016-07-28 | 2017-07-25 | Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling |
| PCT/US2017/043844 WO2018022687A1 (en) | 2016-07-28 | 2017-07-26 | Circuits and methods providing electronic band gap (ebg) structures at memory module electrical coupling |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019525472A JP2019525472A (ja) | 2019-09-05 |
| JP2019525472A5 JP2019525472A5 (enExample) | 2019-10-17 |
| JP6633243B2 true JP6633243B2 (ja) | 2020-01-22 |
Family
ID=61010581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019504126A Active JP6633243B2 (ja) | 2016-07-28 | 2017-07-26 | メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10349513B2 (enExample) |
| EP (1) | EP3491898B1 (enExample) |
| JP (1) | JP6633243B2 (enExample) |
| KR (1) | KR102078065B1 (enExample) |
| CN (1) | CN109565925B (enExample) |
| AU (1) | AU2017302566B9 (enExample) |
| BR (1) | BR112019001333B1 (enExample) |
| TW (1) | TWI695658B (enExample) |
| WO (1) | WO2018022687A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11169940B2 (en) * | 2019-02-20 | 2021-11-09 | Qualcomm Incorporated | Trace length on printed circuit board (PCB) based on input/output (I/O) operating speed |
| TWI795644B (zh) * | 2020-06-02 | 2023-03-11 | 大陸商上海兆芯集成電路有限公司 | 電子總成 |
| JP7529628B2 (ja) * | 2021-07-26 | 2024-08-06 | 株式会社日立製作所 | プリント配線板及び情報処理装置 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3876964A (en) | 1973-08-23 | 1975-04-08 | Amp Inc | Flat flexible transmission cable |
| JP3307597B2 (ja) | 1998-09-30 | 2002-07-24 | 株式会社 アドテック | 印刷配線装置 |
| JP4023166B2 (ja) | 2002-01-25 | 2007-12-19 | ソニー株式会社 | 高周波モジュール用基板及び高周波モジュール |
| WO2006052133A2 (en) * | 2004-11-12 | 2006-05-18 | Doorzand Airdrive B.V. | Composition for cold preservation and perfusion of organs |
| KR20070062633A (ko) * | 2005-12-13 | 2007-06-18 | 삼성전자주식회사 | 컴퓨터 시스템의 시스템 기판에 장착되는 인터페이스 소켓장치 |
| JP2007228222A (ja) * | 2006-02-23 | 2007-09-06 | Mitsubishi Electric Corp | Ebgマテリアル |
| KR101265245B1 (ko) | 2006-11-01 | 2013-05-16 | 에이전시 포 사이언스, 테크놀로지 앤드 리서치 | 이중적층형 ebg 구조체 |
| ITRA20060064A1 (it) * | 2006-11-03 | 2008-05-04 | Fondazione Torino Wireless | Dispositivo con costante dielettrica modulata per la propagazione di onde elettromagnetiche. |
| JP2008171834A (ja) * | 2007-01-05 | 2008-07-24 | Hitachi Ltd | ガラスクロス配線基板 |
| US7768297B2 (en) | 2007-01-31 | 2010-08-03 | Rambus, Inc. | Multi-drop bus system |
| US7839654B2 (en) | 2007-02-28 | 2010-11-23 | International Business Machines Corporation | Method for ultimate noise isolation in high-speed digital systems on packages and printed circuit boards (PCBS) |
| US8164006B2 (en) * | 2008-03-19 | 2012-04-24 | Samsung Electro-Mechanics Co., Ltd. | Electromagnetic bandgap structure and printed circuit board |
| KR100956891B1 (ko) * | 2008-03-19 | 2010-05-11 | 삼성전기주식회사 | 전자기 밴드갭 구조물 및 인쇄회로기판 |
| KR101086856B1 (ko) * | 2008-04-16 | 2011-11-25 | 주식회사 하이닉스반도체 | 반도체 집적 회로 모듈 및 이를 구비하는 pcb 장치 |
| KR101038236B1 (ko) * | 2009-09-16 | 2011-06-01 | 삼성전기주식회사 | 전자기 밴드갭 구조를 구비하는 인쇄회로기판 |
| JP2011108123A (ja) * | 2009-11-20 | 2011-06-02 | Elpida Memory Inc | 終端基板、メモリシステム及びその反射波抑制方法 |
| US9112272B2 (en) * | 2010-08-12 | 2015-08-18 | Feinics Amatech Teoranta | Antenna modules for dual interface smart cards, booster antenna configurations, and methods |
| EP2574155B1 (en) * | 2010-12-03 | 2015-07-29 | Murata Manufacturing Co., Ltd. | High-frequency signal line |
| JP2013232613A (ja) * | 2012-04-05 | 2013-11-14 | Sony Corp | 配線基板及び電子機器 |
| JP5694251B2 (ja) | 2012-07-27 | 2015-04-01 | 株式会社東芝 | Ebg構造体および回路基板 |
| JP5670392B2 (ja) * | 2012-07-27 | 2015-02-18 | 株式会社東芝 | 回路基板 |
| JP6125274B2 (ja) * | 2013-02-27 | 2017-05-10 | 株式会社東芝 | 電子回路および電子機器 |
| US9858181B2 (en) * | 2013-06-20 | 2018-01-02 | Hitachi, Ltd. | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein |
| JP6168943B2 (ja) * | 2013-09-20 | 2017-07-26 | 株式会社東芝 | Ebg構造体、半導体デバイスおよび回路基板 |
| JP5690428B1 (ja) * | 2014-05-21 | 2015-03-25 | 株式会社フジクラ | プリント配線板 |
| WO2017037957A1 (en) | 2015-08-31 | 2017-03-09 | Hitachi, Ltd. | Information processing device, apparatus and connection wiring board |
-
2017
- 2017-07-25 US US15/659,187 patent/US10349513B2/en active Active
- 2017-07-26 BR BR112019001333-4A patent/BR112019001333B1/pt active IP Right Grant
- 2017-07-26 KR KR1020197002434A patent/KR102078065B1/ko active Active
- 2017-07-26 CN CN201780046093.3A patent/CN109565925B/zh active Active
- 2017-07-26 JP JP2019504126A patent/JP6633243B2/ja active Active
- 2017-07-26 AU AU2017302566A patent/AU2017302566B9/en active Active
- 2017-07-26 EP EP17754863.3A patent/EP3491898B1/en active Active
- 2017-07-26 WO PCT/US2017/043844 patent/WO2018022687A1/en not_active Ceased
- 2017-07-27 TW TW106125251A patent/TWI695658B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| AU2017302566B2 (en) | 2020-08-27 |
| TWI695658B (zh) | 2020-06-01 |
| BR112019001333B1 (pt) | 2024-01-02 |
| AU2017302566B9 (en) | 2020-12-24 |
| EP3491898C0 (en) | 2024-09-25 |
| TW201804885A (zh) | 2018-02-01 |
| US20180035533A1 (en) | 2018-02-01 |
| US10349513B2 (en) | 2019-07-09 |
| EP3491898A1 (en) | 2019-06-05 |
| AU2017302566A1 (en) | 2019-01-17 |
| JP2019525472A (ja) | 2019-09-05 |
| BR112019001333A2 (pt) | 2019-05-07 |
| WO2018022687A1 (en) | 2018-02-01 |
| CN109565925A (zh) | 2019-04-02 |
| CN109565925B (zh) | 2022-01-18 |
| EP3491898B1 (en) | 2024-09-25 |
| KR102078065B1 (ko) | 2020-02-17 |
| KR20190029613A (ko) | 2019-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6633243B2 (ja) | メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 | |
| US20150180104A1 (en) | Reduced backdrilling with quarter wavelength transmission line stubs | |
| CN109936912B (zh) | 具有旁路电容的电子模块卡结构 | |
| US10311189B2 (en) | Simulation method and simulation apparatus | |
| US20160179733A1 (en) | Two-part electrical connector | |
| US20200100355A1 (en) | Multilayer ceramic electronic package with modulated mesh topology | |
| US20180060478A1 (en) | Signal via positioning in a multi-layer circuit board | |
| US10271420B2 (en) | Electronic apparatus | |
| WO2014109010A1 (ja) | ストレージ装置及び基板 | |
| US11071197B2 (en) | Multilayer ceramic electronic package with modulated mesh topology and alternating rods | |
| CN115348731A (zh) | 一种多层结构的pcb的频率响应建模方法 | |
| US8669830B2 (en) | Method and device for routing over a void for high speed signal routing in electronic systems | |
| CN221101698U (zh) | 一种改善主干阻抗连续性的nand闪存菊花链拓扑结构 | |
| CN120568586B (zh) | 多层电路板、过孔结构优化方法及电子设备 | |
| CN117528929A (zh) | 400g自环光模块pcb的设计方法和pcb板 | |
| Scogna | Signal integrity analysis of a 26 layers board with emphasis on the effect of non-functional pads | |
| Lee et al. | An Analysis of DDR Channel Signal Integrity on a High-Performance Computing Mainboard | |
| JP2023017299A (ja) | プリント配線板及び情報処理装置 | |
| Liao et al. | Challenges of high-speed channel design on GPU accelerated system | |
| CN119653583A (zh) | 一种具有超频特征的pcb电路板 | |
| CA2218575C (en) | Trace-pad interface for improved signal quality | |
| JP2004355063A (ja) | 方向性結合器基板を用いたバスシステム | |
| CN205622983U (zh) | 内存装置及应用该内存装置的电子装置 | |
| Krohne et al. | Impact of flexible PCB on DDR4 channel memor performance | |
| Rajeswari et al. | Chapter-6 Mitigation Techniques to Reduce Crosstalk in SATA Interconnects |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190409 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190809 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190809 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20190809 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20190918 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20191112 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20191211 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6633243 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |