BR112019001333B1 - Circuitos e métodos que fornecem estruturas de intervalo de banda eletrônica (ebg) em módulo de memória de acoplamento elétrico - Google Patents

Circuitos e métodos que fornecem estruturas de intervalo de banda eletrônica (ebg) em módulo de memória de acoplamento elétrico Download PDF

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Publication number
BR112019001333B1
BR112019001333B1 BR112019001333-4A BR112019001333A BR112019001333B1 BR 112019001333 B1 BR112019001333 B1 BR 112019001333B1 BR 112019001333 A BR112019001333 A BR 112019001333A BR 112019001333 B1 BR112019001333 B1 BR 112019001333B1
Authority
BR
Brazil
Prior art keywords
memory module
ebg
ground plane
conductive traces
dimm
Prior art date
Application number
BR112019001333-4A
Other languages
English (en)
Portuguese (pt)
Other versions
BR112019001333A2 (pt
Inventor
Priyatharshan Pathmanathan
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112019001333A2 publication Critical patent/BR112019001333A2/pt
Publication of BR112019001333B1 publication Critical patent/BR112019001333B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0236—Electromagnetic band-gap structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/029—Woven fibrous reinforcement or textile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
BR112019001333-4A 2016-07-28 2017-07-26 Circuitos e métodos que fornecem estruturas de intervalo de banda eletrônica (ebg) em módulo de memória de acoplamento elétrico BR112019001333B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662367836P 2016-07-28 2016-07-28
US62/367,836 2016-07-28
US15/659,187 US10349513B2 (en) 2016-07-28 2017-07-25 Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling
US15/659,187 2017-07-25
PCT/US2017/043844 WO2018022687A1 (en) 2016-07-28 2017-07-26 Circuits and methods providing electronic band gap (ebg) structures at memory module electrical coupling

Publications (2)

Publication Number Publication Date
BR112019001333A2 BR112019001333A2 (pt) 2019-05-07
BR112019001333B1 true BR112019001333B1 (pt) 2024-01-02

Family

ID=61010581

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112019001333-4A BR112019001333B1 (pt) 2016-07-28 2017-07-26 Circuitos e métodos que fornecem estruturas de intervalo de banda eletrônica (ebg) em módulo de memória de acoplamento elétrico

Country Status (9)

Country Link
US (1) US10349513B2 (enExample)
EP (1) EP3491898B1 (enExample)
JP (1) JP6633243B2 (enExample)
KR (1) KR102078065B1 (enExample)
CN (1) CN109565925B (enExample)
AU (1) AU2017302566B9 (enExample)
BR (1) BR112019001333B1 (enExample)
TW (1) TWI695658B (enExample)
WO (1) WO2018022687A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11169940B2 (en) * 2019-02-20 2021-11-09 Qualcomm Incorporated Trace length on printed circuit board (PCB) based on input/output (I/O) operating speed
TWI795644B (zh) * 2020-06-02 2023-03-11 大陸商上海兆芯集成電路有限公司 電子總成
JP7529628B2 (ja) * 2021-07-26 2024-08-06 株式会社日立製作所 プリント配線板及び情報処理装置

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AU2005302851B2 (en) * 2004-11-12 2012-02-23 Organoflush B.V. Composition for cold preservation and perfusion of organs
KR20070062633A (ko) * 2005-12-13 2007-06-18 삼성전자주식회사 컴퓨터 시스템의 시스템 기판에 장착되는 인터페이스 소켓장치
JP2007228222A (ja) * 2006-02-23 2007-09-06 Mitsubishi Electric Corp Ｅｂｇマテリアル
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ITRA20060064A1 (it) * 2006-11-03 2008-05-04 Fondazione Torino Wireless Dispositivo con costante dielettrica modulata per la propagazione di onde elettromagnetiche.
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US8164006B2 (en) * 2008-03-19 2012-04-24 Samsung Electro-Mechanics Co., Ltd. Electromagnetic bandgap structure and printed circuit board
KR100956891B1 (ko) 2008-03-19 2010-05-11 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
KR101086856B1 (ko) * 2008-04-16 2011-11-25 주식회사 하이닉스반도체 반도체 집적 회로 모듈 및 이를 구비하는 ｐｃｂ 장치
KR101038236B1 (ko) * 2009-09-16 2011-06-01 삼성전기주식회사 전자기 밴드갭 구조를 구비하는 인쇄회로기판
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JP2013232613A (ja) * 2012-04-05 2013-11-14 Sony Corp 配線基板及び電子機器
JP5670392B2 (ja) * 2012-07-27 2015-02-18 株式会社東芝 回路基板
JP5694251B2 (ja) 2012-07-27 2015-04-01 株式会社東芝 Ｅｂｇ構造体および回路基板
JP6125274B2 (ja) * 2013-02-27 2017-05-10 株式会社東芝 電子回路および電子機器
WO2014203383A1 (ja) * 2013-06-20 2014-12-24 株式会社日立製作所 異種メモリを混載したメモリモジュール、及びそれを搭載した情報処理装置
JP6168943B2 (ja) * 2013-09-20 2017-07-26 株式会社東芝 Ｅｂｇ構造体、半導体デバイスおよび回路基板
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Also Published As

Publication number Publication date
AU2017302566B9 (en) 2020-12-24
KR20190029613A (ko) 2019-03-20
EP3491898C0 (en) 2024-09-25
AU2017302566B2 (en) 2020-08-27
US10349513B2 (en) 2019-07-09
JP2019525472A (ja) 2019-09-05
TW201804885A (zh) 2018-02-01
EP3491898B1 (en) 2024-09-25
TWI695658B (zh) 2020-06-01
WO2018022687A1 (en) 2018-02-01
AU2017302566A1 (en) 2019-01-17
CN109565925A (zh) 2019-04-02
KR102078065B1 (ko) 2020-02-17
US20180035533A1 (en) 2018-02-01
CN109565925B (zh) 2022-01-18
EP3491898A1 (en) 2019-06-05
BR112019001333A2 (pt) 2019-05-07
JP6633243B2 (ja) 2020-01-22

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 26/07/2017, OBSERVADAS AS CONDICOES LEGAIS