JP6610508B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6610508B2 JP6610508B2 JP2016219029A JP2016219029A JP6610508B2 JP 6610508 B2 JP6610508 B2 JP 6610508B2 JP 2016219029 A JP2016219029 A JP 2016219029A JP 2016219029 A JP2016219029 A JP 2016219029A JP 6610508 B2 JP6610508 B2 JP 6610508B2
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 239000010410 layer Substances 0.000 claims description 132
- 210000000746 body region Anatomy 0.000 claims description 58
- 230000003071 parasitic effect Effects 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 19
- 239000002344 surface layer Substances 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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Description
第1実施形態について説明する。本実施形態で説明する半導体装置は、LDMOSなどの各種素子に加えて、LDMOSと同様の構造を用いて保護素子となるGGMOSを構成したものであるが、LDMOSなどの一般的な素子については従来と同様であるため、主にGGMOSについて説明する。
第2実施形態について説明する。本実施形態は、第1実施形態に対してGGMOS100の平面レイアウトを変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第3実施形態について説明する。本実施形態も、第1実施形態に対してGGMOS100の平面レイアウトを変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第4実施形態について説明する。本実施形態は、第1〜第3実施形態に対してボディコンタクト抵抗の構成を変更したものであり、その他については第1〜第3実施形態と同様であるため、第1〜第3実施形態と異なる部分についてのみ説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
3 P型ウェル層
4 P+型カソード領域
5 N型ボディ領域
5a N型高抵抗層
7 P+型アノード領域
11 カソード電極
12 アノード電極
100 GGMOS
200 LDMOS
Claims (6)
- 保護素子を構成する半導体装置であって、
互いに接して構成された第1導電型ウェル層(2)と第2導電型ウェル層(3)とを有した半導体基板(1)と、
前記第1導電型ウェル層の表層部において、前記第1導電型ウェル層と前記第2導電型ウェル層とが構成するPNジャンクションから離れた位置に形成され、前記第2導電型ウェル層よりも第2導電型不純物濃度が高くされたカソード領域(4)と、
前記第1導電型ウェル層の表層部のうち、前記カソード領域と異なる位置に形成された第1導電型のボディ領域(5)と、
前記第2導電型ウェル層の表層部において、前記PNジャンクションから離れた位置に形成され、前記第2導電型ウェル層よりも第2導電型不純物濃度が高くされたアノード領域(7)と、
前記第2導電型ウェル層のうち前記カソード領域と前記アノード領域との間に位置する部分の表面に形成されたゲート絶縁膜(8)と、
前記ゲート絶縁膜の上に形成されたゲート電極(9)と、
前記カソード領域に電気的に接続されると共に、前記ボディ領域を介して前記第1導電型ウェル層に電気的に接続されるカソード電極(11)と、
前記アノード領域に電気的に接続されるアノード電極(12)と、を備え、前記カソード領域と前記第1導電型ウェル層および前記第2導電型ウェル層による寄生トランジスタ(20)がオンしてカソード−アノード間が導通させられることで、該カソード−アノード間に接続される被保護素子(200)を保護する前記保護素子を有し、
前記ボディ領域は、前記保護素子の1セルに対して複数個配置されており、かつ、前記カソード電極に対してショットキー接触させられている半導体装置。 - 保護素子を構成する半導体装置であって、
互いに接して構成された第1導電型ウェル層(2)と第2導電型ウェル層(3)とを有した半導体基板(1)と、
前記第1導電型ウェル層の表層部において、前記第1導電型ウェル層と前記第2導電型ウェル層とが構成するPNジャンクションから離れた位置に形成され、前記第2導電型ウェル層よりも第2導電型不純物濃度が高くされたカソード領域(4)と、
前記第1導電型ウェル層の表層部のうち、前記カソード領域と異なる位置に形成された第1導電型のボディ領域(5)と、
前記第2導電型ウェル層の表層部において、前記PNジャンクションから離れた位置に形成され、前記第2導電型ウェル層よりも第2導電型不純物濃度が高くされたアノード領域(7)と、
前記第2導電型ウェル層のうち前記カソード領域と前記アノード領域との間に位置する部分の表面に形成されたゲート絶縁膜(8)と、
前記ゲート絶縁膜の上に形成されたゲート電極(9)と、
前記カソード領域に電気的に接続されると共に、前記ボディ領域を介して前記第1導電型ウェル層に電気的に接続されるカソード電極(11)と、
前記アノード領域に電気的に接続されるアノード電極(12)と、を備え、前記カソード領域と前記第1導電型ウェル層および前記第2導電型ウェル層による寄生トランジスタ(20)がオンしてカソード−アノード間が導通させられることで、該カソード−アノード間に接続される被保護素子(200)を保護する前記保護素子を有し、
前記ボディ領域は、前記保護素子の1セルに対して複数個配置されており、かつ、前記第1導電型ウェル層よりも上の位置に形成されると共に前記第1導電型ウェル層よりも高抵抗で構成され、前記カソード電極に対して接触させられる第1導電型の高抵抗層(5a)を有している半導体装置。 - 前記高抵抗層は、高抵抗ポリシリコンまたは高抵抗シリサイド層である請求項2に記載の半導体装置。
- 前記第1導電型ウェル層および前記第2導電型ウェル層は、前記半導体基板の表面と平行な一方向に延設された直線状の部分を有し、前記PNジャンクションの境界線も前記一方向に沿った直線状の部分を有しており、
前記カソード領域および前記ボディ領域は、前記一方向に沿って複数個並べられており、
前記アノード領域は、前記一方向に沿って延設されている請求項1ないし3のいずれか1つに記載の半導体装置。 - 前記第1導電型ウェル層および前記第2導電型ウェル層の少なくとも一方はメッシュ状とされていると共に、他方は前記一方が構成するメッシュ状の網目の位置に形成され、
前記カソード領域および前記ボディ領域は、前記第1導電型ウェル層が形成されている位置に格子状に複数個配置されており、
前記アノード領域は、前記第2導電型ウェル層が形成されている位置に格子状に複数個配置されている請求項1ないし3のいずれか1つに記載の半導体装置。 - 前記第2導電型ウェル層および前記アノード領域は同心円となる円形状とされ、
前記第1導電型ウェル層は、前記アノード領域を中心として同心円状に配置され、
前記カソード領域および前記ボディ領域は、前記アノード領域を囲むように円形状に交互に複数個ずつ配置されている請求項1ないし3のいずれか1つに記載の半導体装置。
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