CN109923663B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109923663B
CN109923663B CN201780068708.2A CN201780068708A CN109923663B CN 109923663 B CN109923663 B CN 109923663B CN 201780068708 A CN201780068708 A CN 201780068708A CN 109923663 B CN109923663 B CN 109923663B
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山田明
樱井晋也
中野敬志
近藤阳介
本岛六都也
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Abstract

对于GGMOS的1个单元将N型体区域(5)配置多个，并且将N型体区域(5)的N型杂质浓度设定得较低，从而与阴极电极进行肖特基接触。具体而言，包围构成GGMOS的单元而将N型体区域(5)配置多个。由此，能够提高体接触电阻，能够提高基极电阻，所以能够更早地使寄生PNP晶体管导通。因而，能够可靠地抑制对被保护元件流过浪涌电流。

Description

半导体装置
相关申请的相互参照
本申请基于2016年11月09日申请的日本专利申请第2016－219029号，这里通过参照而包括其记载内容。
技术领域
本发明涉及具有使LDMOS(横向扩散MOS)(Laterally Diffused MOSFET的简写)的栅极－源极间短路而使用的GGMOS(栅极接地MOS)(Grounded-gate MOSFET的简写)等保护元件的半导体装置。
背景技术
以往，已知例如通过将GGMOS与用作向负载的电力供给的开关元件的MOSFET等并联连接从而通过GGMOS保护MOSFET的保护电路。该保护电路中，由于与MOSFET并联连接的GGMOS比MOSFET先击穿(break through)，所以浪涌电流流过GGMOS侧从而能够使浪涌电流不流过MOSFET，能够保护MOSFET不损坏。
例如，GGMOS被做成具有寄生PNP晶体管以及寄生二极管的结构。寄生PNP晶体管包括邻接配置的N型阱层及P型阱层、在N型阱层的表层部形成的P+型阴极区域及N+型体(body)区域、以及在P型阱层的表层部形成的P+型阳极区域等。寄生二极管包括N型阱层与P型阱层的PN结。另外，N+型体区域相当于寄生二极管的阴极，在寄生PNP晶体管中相当于基极。同样，P+型阳极区域相当于寄生二极管的阳极，在寄生PNP晶体管中相当于集电极。P+型阴极区域相当于寄生PNP晶体管的发射极。
在这样的结构下，在施加浪涌时N型阱层与P型阱层的PN结所形成的寄生二极管导通。并且，通过伴随于此的基极电阻即N型阱层中的直至N+型体区域的内部电阻的电压下降，寄生晶体管的基极－阴极间电压上升。由此，寄生PNP晶体管导通，不进行向用作开关元件的MOSFET的电力供给，从而能够抑制浪涌电流流过MOSFET。
但是，由于P型阱层的电阻成分而P型阱层的电压上升，超过作为被保护元件的MOSFET的耐压，不再能够保护被保护元件。特别是，在保护元件的耐压高的情况下，漂移(drift)长度即P型阱层中的成为与N型阱层的边界的PN结至P+型阳极区域的长度较长从而漂移电阻变高，容易引起上述电压上升。
因此，为了进一步使寄生PNP晶体管容易动作、不对被保护元件施加过大电压，提出了将N+型体区域仅形成在形成GGMOS的单元区域的外周部的构造(参照专利文献1)。根据这样的结构，能够拉开N型阱层与P型阱层的PN结至N+型体层的距离，能够增大基极电阻，从而能够使寄生PNP晶体管容易动作。因而，能够抑制向被保护元件施加过大电压的情况。
现有技术文献
专利文献
专利文献1:日本特开2013－8715号公报
但是，通过限定N+型体区域的形成位置，在GGMOS中的距N+型体区域较远的部分和较近的部分中动作定时产生偏差，无法均匀地使GGMOS动作。
发明内容
本发明的目的在于，提供能够使寄生PNP晶体管更容易动作并且使GGMOS更均匀地动作的结构的半导体装置。
本发明的1个观点的半导体装置，具有保护元件，该保护元件具备：半导体基板，具有彼此相接而构成的第1导电型阱层和第2导电型阱层；阴极区域，在第1导电型阱层的表层部中形成在从第1导电型阱层和第2导电型阱层所构成的PN结离开了的位置，与第2导电型阱层相比第2导电型杂质浓度较高；第1导电型的体区域，形成在第1导电型阱层的表层部中的与阴极区域不同的位置；阳极区域，在第2导电型阱层的表层部中形成在从PN结离开了的位置，与第2导电型阱层相比第2导电型杂质浓度较高；栅极绝缘膜，形成在第2导电型阱层中的位于阴极区域与阳极区域之间的部分的表面；栅极电极，形成在栅极绝缘膜之上；阴极电极，与阴极区域电连接，并且经由体区域而与第1导电型阱层电连接；以及阳极电极，与阳极区域电连接。通过阴极区域和第1导电型阱层及第2导电型阱层所形成的寄生晶体管导通而使阴极－阳极间导通，从而保护元件保护在该阴极－阳极间连接的被保护元件。体区域对于保护元件的1个单元被配置了多个，并且，对于阴极电极进行肖特基接触。
这样，对于GGMOS的1个单元将体区域配置多个，并且将体区域的杂质浓度设定得较低，从而与阴极电极进行肖特基接触。由此，能够提高体接触电阻，能够提高基极电阻，所以寄生PNP晶体管容易动作，能够更早使寄生晶体管导通。因而，能够可靠地抑制对被保护元件流过浪涌电流。
本发明的另1个观点的半导体装置中，体区域具有第1导电型的高电阻层，该高电阻层对于保护元件的1个单元被配置了多个，并且形成在第1导电型阱层之上的位置且与第1导电型阱层相比以高电阻构成，与阴极电极接触。
这样，在体区域具备高电阻层，也能够提高体接触电阻。因此，能够得到与上述的本发明的1个观点中的半导体装置相同的效果。
附图说明
图1是第1实施方式的具备GGMOS的半导体装置的平面布局图。
图2是图1的II－II截面图。
图3是图2的截面立体图。
图4是第1实施方式的将GGMOS用作保护元件的情况的等价电路图。
图5是第2实施方式的具备GGMOS的半导体装置的平面布局图。
图6是第3实施方式的具备GGMOS的半导体装置的平面布局图。
图7是第4实施方式的具备GGMOS的半导体装置的截面立体图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。另外，以下的各实施方式中，对于相互相同或等同的部分赋予同一附图标记而进行说明。
(第1实施方式)
对第1实施方式进行说明。本实施方式中说明的半导体装置，除了LDMOS等各种元件以外，还利用与LDMOS相同的构造而构成了成为保护元件的GGMOS，LDMOS等通常的元件与以往相同，所以主要对GGMOS进行说明。
半导体装置除了未图示的LDMOS以外，还具备图1～图3所示的结构的GGMOS100等。GGMOS100具有与LDMOS相同的基本构造，是对于与LDMOS相同的半导体基板1而形成的，具有以下的构造。另外，以下的说明中，将图1及图2的纸面左右方向设为x方向，将图1的纸面垂直方向以及图2的上下方向设为y方向，将图1的纸面上下方向、即图2的相对于与纸面平行的xy平面的法线方向设为z方向。x方向及z方向是与半导体基板1的表面平行的方向，是彼此正交的方向。y方向是相对于半导体基板1的表面的法线方向。图1虽非截面图，但为了使图容易观察而局部地示出了影线。
将图2的构造的GGMOS100作为半单元，将该构造如图1所示那样夹着直线L1线对称地布局从而构成1个单元，进一步做成将该单元夹着直线L2线对称地配置的结构。另外，这里图示了2个单元，但这是示意地表示平面布局的，也可以配置有2个以上的单元。
如图2所示，在例如由硅基板构成的半导体基板1的表层部，形成有N型阱层2及P型阱层3，通过将它们相邻配置而构成了PN结。本实施方式的情况下，N型阱层2及P型阱层3具有在z方向上延伸的直线状的部分，由它们构成的PN结的边界线也具有沿z方向延伸的直线状的部分。
另外，这里，做成了对半导体基板1分别形成了N型阱层2和P型阱层3的结构，但在半导体基板1由N型基板构成的情况下，还能将半导体基板1用作N型阱层2。此外，在半导体基板1由P型基板构成的情况下，还能将半导体基板1用作P型阱层3。此外，这里说明仅将硅基板用作半导体基板1的情况，但还能将利用埋入绝缘膜将有源层和支承基板绝缘的构造的SOI(Silicon On Insulator的简写)基板用作半导体基板1。该情况下，在有源层形成N型阱层2及P型阱层3，通过将有源层用N型或P型的任一种构成，还能使其作为N型阱层2和P型阱层3的任一个发挥功能。
在N型阱层2的表层部，形成有P+型阴极区域4。该P+型阴极区域4相当于LDMOS的P+型源极区域。
P+型阴极区域4形成在从PN结离开了的位置，至少沿PN结的边界线配置有多个。本实施方式的情况下，如图1所示，将图2及图3的构造的GGMOS100布局成四边形的框体形状的单元夹着直线L2排列有2个，以将各单元包围的方式配置有多个P+型阴极区域4。
各P+型阴极区域4等间隔地配置，在相邻的单元间P+型阴极区域4是共通的。各P+型阴极区域4的平面形状例如为四边形，其中的二边平行于PN结的边界线。例如，P+型阴极区域4相比于P型阱层3而言P型杂质浓度以更高的浓度构成，表面的P型杂质浓度为9×1020cm－3左右。
此外，在N型阱层2的表层部，配置有多个N型体区域5。本实施方式的情况下，N型体区域5被配置在P+型阴极区域4之间，从而将GGMOS100的单元包围而配置。
各N型体区域5等间隔地配置，在相邻的单元间N型体区域5是共通的。各N型体区域5的平面形状例如为四边形，其中的二边平行于PN结的边界线。例如，N型体区域5的表面的N型杂质浓度为7×1017cm－3左右，比P+型阴极区域4低。因此，对于后述的阴极电极11，P+型阴极区域4进行欧姆接触，N型体区域5进行肖特基接触。
另一方面，在P型阱层3的表层部，埋入了绝缘膜6。该绝缘膜6形成在从N型阱层2与P型阱层3的PN结离开了的位置，并且沿PN结的边界线延伸设置。例如，绝缘膜6由STI(Shallow Trench Isolation)膜、LOCOS氧化膜等构成，以从P型阱层3的表层部向深度方向进入的方式而被埋入。
此外，在P型阱层3中的夹着绝缘膜6而与N型阱层2相反的一侧的位置形成有P+型阳极区域7。P型阳极区域7的平面布局为直线状，平行于PN结的边界线，更详细而言沿着直线L1形成，是夹着直线L1而配置在两侧的各半单元的共通的部分。例如，P+型阳极区域7相比于P型阱层3而言P型杂质浓度以高浓度构成，表面的P型杂质浓度为9×1020cm－3左右。
进而，在N型阱层2及P型阱层3中的位于P+型阴极区域4与绝缘膜6及P+型阳极区域7之间的部分的表面，形成有栅极绝缘膜8，进而在该栅极绝缘膜8之上形成有栅极电极9。栅极电极9在LDMOS中被用作被施加栅极电压的部分，但在GGMOS100中，通过与后述的阴极电极11电连接从而被设为源极电位即接地电位。
此外，如图2所示，将栅极电极9覆盖而形成有层间绝缘膜10。在层间绝缘膜10，形成有使P+型阴极区域4及N型体区域5露出的接触孔，通过该接触孔，P+型阴极区域4及N型体区域5对于阴极电极11电连接。进而，在层间绝缘膜10，形成有使P+型阳极区域7露出的接触孔，通过该接触孔，P+型阳极区域7对于阳极电极12电连接。
另外，如图1所示，GGMOS100的单元的外周被分离构造110包围。分离构造110例如由沟槽分离构造、PN结分离构造等构成，通过用该分离构造110将GGMOS100包围，从而将GGMOS100与其他元件电分离。
通过以上那样的构造，构成了图1～图3所示的GGMOS100。这样的结构的GGMOS100如上述那样，成为N型阱层2及P型阱层3在z方向上以直线状延伸的构造。同样，P+型阴极区域4及N型体区域5也在z方向上以直线状交替地排列有多个，P+型阳极区域7也在z方向上以直线状延伸设置。因此，成为将GGMOS100的各单元以条状布局的条构造。
这样的GGMOS的等价电路成为图4所示的电路结构。即，通过P+型阴极区域4和N型阱层2及P型阱层3所形成的PNP结，构成寄生PNP晶体管20。该寄生PNP晶体管中，P+型阴极区域4作为阴极换言之作为发射极发挥功能，N型阱层2作为基极发挥功能，P型阱层3作为阳极换言之作为集电极发挥功能。P+型阴极区域4与成为阴极端子的阴极电极11电连接，P型阱层3经由内部电阻构成的漂移电阻21而与成为阳极端子的阳极电极12电连接。此外，通过N型阱层2与P型阱层3的PN结构成二极管22，并构成了将其连接在寄生PNP晶体管的基极－阳极间的结构。进而，做成了将N型阱层2的内部电阻、N型体区域5与阴极电极11的体接触电阻所形成的基极电阻23配置在寄生PNP晶体管的基极－阴极间的结构。
另外，栅极电极9被设为接地电位，所以在GGMOS100中成为不特别产生影响的部分，从电路结构中排除了。
这样的电路结构的GGMOS100例如如图4中所示那样，阳极－阴极被连接在LDMOS200的漏极－源极间，从而实现作为保护元件的作用。例如，如果设LDMOS200的耐压为电压V1，则寄生PNP晶体管20以比电压V1低的电压V2进行动作。具体而言，如果阳极－阴极间的电压成为规定值以上，则二极管22导通，在漂移电阻21和二极管22及基极电阻23的路线中流过电流，通过与流过的电流量对应的基极电阻23的电压下降，寄生PNP晶体管20的阴极－基极间电压上升。由此，寄生PNP晶体管20导通，通过寄生PNP晶体管20使阴极－阳极间导通，所以能够抑制对LDMOS200流过浪涌电流，能够保护LDMOS200不受损坏。
此时，如果漂移电阻21引起的P型阱层3的电压上升较大，则有可能超过作为LDMOS200的耐压的电压V1而不再能够保护LDMOS200。例如，如果由于P型阱层3中的成为与N型阱层2的边界的PN结至P+型阳极区域7的距离、即漂移长度较长从而漂移电阻21变高，则容易引起上述电压上升，不再能使GGMOS100作为适当的保护元件发挥功能。
但是，本实施方式的GGMOS100中，使N型体区域5的N型杂质浓度为低浓度，使N型体区域5相对于阴极电极11进行肖特基接触。因此，体接触电阻变高，结果，基极电阻23变高，由基极电阻23的电压下降导致的阴极－基极间电压上升。由此，能够更早地使寄生PNP晶体管20导通，能够可靠地抑制对作为被保护元件的LDMOS200流过浪涌电流。
如以上说明的那样，本实施方式的半导体装置中，对GGMOS100的1个单元配置有多个N型体区域5，并且将N型体区域5的N型杂质浓度设定得较低，从而使得与阴极电极11进行肖特基接触。具体而言，将构成GGMOS100的单元包围而配置有多个N型体区域5。由此，能够提高体接触电阻，能够提高基极电阻23，所以寄生PNP晶体管20容易动作，能够更早地使寄生PNP晶体管20导通。因此，能够可靠地抑制对被保护元件流过浪涌电流。
另外，关于这样的构造的GGMOS100的制造方法，基本上能够采用与以往同样的制造方法。例如，在通过离子注入形成N型体区域5的情况下，使离子注入时的剂量较少而使N型体区域5的N型杂质浓度成为低浓度即可。
(第2实施方式)
对第2实施方式进行说明。本实施方式相对于第1实施方式将GGMOS100的平面布局进行了变更，其他与第1实施方式相同，所以仅对与第1实施方式不同的部分进行说明。
如图5所示，将包围N型体区域5的周围而同心状地配置P+型阴极区域4得到的结构作为1组，将多个组以格子状排列。即，将在图5中的x方向上等间隔地排列有多个而成的组在z方向上空出间隔配置多个从而以格子状配置。图5中，将在x方向上排列有5个的结构在z方向上空出间隔配置5个，从而以5×5的配置而配置了N型体区域5以及P+型阴极区域4的组，但这是示意性地表示平面布局的，不限于5×5的配置。
此外，P+型阳极区域7也以格子状配置有多个。具体而言，将P+型阳极区域7在从N型体区域5及P+型阴极区域4的组离开了的位置上在图5中的x方向上等间隔地排列有多个而成的结构，在z方向上空出间隔配置多个从而配置成格子状。更详细而言，各P+型阳极区域7，在N型体区域5及P+型阴极区域4的组中的邻接4组之间、即以四边形状配置的四组的中心位置配置有P+型阳极区域7。因此，图5中，通过将在x方向上排列有4个而成的结构在z方向上空出间隔配置4个，从而以4×4的配置而配置了P+型阳极区域7，但这是示意地表示平面布局的，不限于4×4的配置。
并且，以在这样配置的P+型阳极区域7、N型体区域5及P+型阴极区域4的组的间隙中铺满的方式而配置绝缘膜6、栅极电极9，从而使栅极电极9为网格状。图5中虽未示出，但N型阱层2至少形成在与N型体区域5及P+型阴极区域4的组对应的位置及其周围。同样，图5中虽未示出，但P型阱层3至少形成在与P+型阳极区域7对应的位置及其周围。并且，N型阱层2和P型阱层3的某一方为网格状，另一方形成在网格状的一方的网眼位置。通过这样的结构，构成了具有网格构造的GGMOS100的半导体装置。另外，图5中的II－II线的截面图成为与图2相同的截面。
这样，在将P+型阳极区域7、N型体区域5及P+型阴极区域4的组配置成格子状、栅极电极9为网格构造的平面布局的GGMOS100中，也能够实现与第1实施方式相同的截面构造。因而，能够得到与第1实施方式相同的效果。
(第3实施方式)
对第3实施方式进行说明。本实施方式也相对于第1实施方式将GGMOS100的平面布局进行了变更，其他与第1实施方式相同，所以仅说明与第1实施方式不同的部分。
如图6所示，本实施方式中，将P+型阳极区域7构成为圆形。此外，图6中虽未示出，但P型阱层3以将P+型阳极区域7作为同心圆的圆形而构成，在其周围形成有N型阱层2。进而，将P+型阳极区域7的周围包围而配置了N型阱层2、绝缘膜6、栅极电极9。进而，将栅极电极9的周围包围而交替地配置了N型体区域5以及P+型阴极区域4。这样，得到以P+型阳极区域7为中心而将各结构以同心圆状配置的构造。通过这样的结构，构成了具有同心圆构造的GGMOS100的半导体装置。另外，图6中的II－II线的截面图成为与图2相同的截面。
这样，在以P+型阳极区域7为中心而将各结构以同心圆状配置的平面布局的GGMOS100中，也能够实现与第1实施方式相同的截面构造。因而，能够得到与第1实施方式相同的效果。
(第4实施方式)
对第4实施方式进行说明。本实施方式相对于第1～第3实施方式将体接触电阻的结构进行了变更，其他与第1～第3实施方式相同，所以仅说明与第1～第3实施方式不同的部分。
如图7所示，本实施方式中，在N型体区域5中具备N型高电阻层5a。也可以是如下结构，即：将N型体区域5仅由N型高电阻层5a构成，N型高电阻层5a之下成为N型阱层2。也可以是虽未图示但在N型高电阻层5a之下形成了高浓度N型层的结构。
例如，N型高电阻层5a由高电阻多晶硅、高电阻硅化物层等构成。例如，N型高电阻层5a被设定为与阴极电极11的接触成为肖特基接触的N型杂质浓度。
这样，在N型体区域5中具备N型高电阻层5a，也能够提高体接触电阻。因此，能够得到与第1实施方式相同的效果。
关于这样的构造的GGMOS100的制造方法，基本上能够采用与以往相同的制造方法，但是使N型高电阻层5a在栅极电极9的形成工序时同时地形成。具体而言，GGMOS100之中，在形成N型高电阻层5a以外的各杂质区域等后，形成栅极绝缘膜8，然后，进行如下那样的工序。首先，将栅极绝缘膜8构图，在N型体区域5的预定形成区域使栅极绝缘膜8开口。接着，在将多晶硅成膜后，在栅极电极9的预定形成位置、N型体区域5的预定形成位置离子注入N型杂质。但是，向栅极电极9和N型体区域5的N型杂质的注入量不同，与栅极电极9相比，N型体区域5的注入量少。因此，通过利用未图示的掩模进行离子注入的划分，从而向各个区域依次进行离子注入。然后，通过将多晶硅构图，将栅极电极9及N型体区域5同时形成。然后，与以往同样，进行层间绝缘膜10的形成工序、接触孔的形成工序、阴极电极11及阳极电极12的形成工序等，从而能够制造本实施方式的GGMOS100。
(其他实施方式)
本发明依据上述的实施方式进行了记载，但不限于该实施方式，也包含各种变形例及均等范围内的变形。除此以外，各种各样的组合及形态、进而在它们中仅包含一要素、其以上或其以下的其他组合及形态也包含在本发明的范畴及思想范围中。
例如，上述各实施方式中，构成实施方式的要素，除了特别明示了是必须的情况以及可以认为在原理上明显是必须的情况等之外，当然不是必须的。此外，上述各实施方式中，在提及了实施方式的构成要素的个数、数值、量、范围等数值的情况下，除了明示了是特别必须的情况以及在原理上明显限定于特定数量的情况等之外，不限于该特定的数量。此外，上述各实施方式中，当提及构成要素等的形状、位置关系等时，除了特别明示的情况以及在原理上限定于特定的形状、位置关系等的情况等之外，不限于该形状、位置关系等。
此外，上述各实施方式中说明了利用第1导电型为n型、第2导电型为p型的p沟道型LDMOS构成GGMOS100的情况。但是，这只不过表示一例，也可以利用第1导电型为p型、第2导电型为n型的n沟道型LDMOS构成GGMOS100。

Claims (9)

1.一种半导体装置，构成保护元件，其特征在于，
具有上述保护元件，该保护元件具备：
半导体基板(1)，具有彼此相接而构成的第1导电型阱层(2)和第2导电型阱层(3)；
阴极区域(4)，在上述第1导电型阱层的表层部中形成在从上述第1导电型阱层和上述第2导电型阱层所构成的PN结离开了的位置，与上述第2导电型阱层相比第2导电型杂质浓度较高；
第1导电型的体区域(5)，形成在上述第1导电型阱层的表层部中的与上述阴极区域不同的位置；
阳极区域(7)，在上述第2导电型阱层的表层部中形成在从上述PN结离开了的位置，与上述第2导电型阱层相比第2导电型杂质浓度较高；
栅极绝缘膜(8)，形成在上述第2导电型阱层中的位于上述阴极区域与上述阳极区域之间的部分的表面；
栅极电极(9)，形成在上述栅极绝缘膜之上；
阴极电极(11)，与上述阴极区域电连接，并且经由上述体区域而与上述第1导电型阱层电连接；以及
阳极电极(12)，与上述阳极区域电连接，
通过上述阴极区域和上述第1导电型阱层及上述第2导电型阱层所形成的寄生晶体管(20)导通而使阴极－阳极间导通，从而上述保护元件保护在该阴极－阳极间连接的被保护元件(200)，
上述体区域对于上述保护元件的1个单元被配置了多个，并且，对于上述阴极电极进行肖特基接触。
2.如权利要求1所述的半导体装置，其特征在于，
上述第1导电型阱层以及上述第2导电型阱层具有在与上述半导体基板的表面平行的一个方向上延伸设置的直线状的部分，上述PN结的边界线也具有沿着上述一个方向的直线状的部分，
上述阴极区域以及上述体区域沿着上述一个方向排列有多个，
上述阳极区域沿着上述一个方向延伸设置。
3.如权利要求1所述的半导体装置，其特征在于，
上述第1导电型阱层以及上述第2导电型阱层的至少一方为网格状，另一方形成在上述一方所构成的网格状的网眼的位置，
上述阴极区域以及上述体区域在形成上述第1导电型阱层的位置以格子状配置有多个，
上述阳极区域在形成上述第2导电型阱层的位置以格子状配置有多个。
4.如权利要求1所述的半导体装置，其特征在于，
上述第2导电型阱层以及上述阳极区域是成为同心圆的圆形，
上述第1导电型阱层以上述阳极区域为中心而以同心圆状配置，
上述阴极区域以及上述体区域将上述阳极区域包围而以圆形交替地各配置有多个。
5.一种半导体装置，构成保护元件，其特征在于，
具有上述保护元件，该保护元件具备：
半导体基板(1)，具有彼此相接而构成的第1导电型阱层(2)和第2导电型阱层(3)；
阴极区域(4)，在上述第1导电型阱层的表层部中形成在从上述第1导电型阱层与上述第2导电型阱层所构成的PN结离开了的位置，与上述第2导电型阱层相比第2导电型杂质浓度较高；
第1导电型的体区域(5)，形成在上述第1导电型阱层的表层部中的与上述阴极区域不同的位置；
阳极区域(7)，在上述第2导电型阱层的表层部中形成在从上述PN结离开了的位置，与上述第2导电型阱层相比第2导电型杂质浓度较高；
栅极绝缘膜(8)，形成在上述第2导电型阱层中的位于上述阴极区域与上述阳极区域之间的部分的表面；
栅极电极(9)，形成在上述栅极绝缘膜之上；
阴极电极(11)，与上述阴极区域电连接，并且经由上述体区域而与上述第1导电型阱层电连接；以及
阳极电极(12)，与上述阳极区域电连接，
通过上述阴极区域和上述第1导电型阱层以及上述第2导电型阱层所形成的寄生晶体管(20)导通而使阴极－阳极间导通，从而上述保护元件保护在该阴极－阳极间连接的被保护元件(200)，
上述体区域具有第1导电型的高电阻层(5a)，该高电阻层(5a)对于上述保护元件的1个单元被配置了多个，并且形成在上述第1导电型阱层之上的位置且与上述第1导电型阱层相比以高电阻构成，与上述阴极电极接触。
6.如权利要求5所述的半导体装置，其特征在于，
上述高电阻层是高电阻多晶硅或高电阻硅化物层。
7.如权利要求5或6所述的半导体装置，其特征在于，
上述第1导电型阱层以及上述第2导电型阱层具有在与上述半导体基板的表面平行的一个方向上延伸设置的直线状的部分，上述PN结的边界线也具有沿着上述一个方向的直线状的部分，
上述阴极区域以及上述体区域沿着上述一个方向排列有多个，
上述阳极区域沿着上述一个方向延伸设置。
8.如权利要求5或6所述的半导体装置，其特征在于，
上述第1导电型阱层以及上述第2导电型阱层的至少一方为网格状，另一方形成在上述一方所构成的网格状的网眼的位置，
上述阴极区域以及上述体区域在形成上述第1导电型阱层的位置以格子状配置有多个，
上述阳极区域在形成上述第2导电型阱层的位置以格子状配置有多个。
9.如权利要求5或6所述的半导体装置，其特征在于，
上述第2导电型阱层以及上述阳极区域是成为同心圆的圆形，
上述第1导电型阱层以上述阳极区域为中心而以同心圆状配置，
上述阴极区域以及上述体区域将上述阳极区域包围而以圆形交替地各配置有多个。
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