CN105378931A - 内置有二极管的igbt - Google Patents

内置有二极管的igbt Download PDF

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CN105378931A
CN105378931A CN201380076833.XA CN201380076833A CN105378931A CN 105378931 A CN105378931 A CN 105378931A CN 201380076833 A CN201380076833 A CN 201380076833A CN 105378931 A CN105378931 A CN 105378931A
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斋藤顺
町田悟
山下侑佑
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Toyota Motor Corp
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Abstract

当在IGBT中附加分离出上部体区(8a)和下部体区(8b)的势垒层(10)时，电导率调制活化从而导通电阻下降，当附加到达至势垒层(10)的肖特基接触区(6)时，能够实现二极管结构，但会附加经由势垒层(10)和肖特基接触区(6)到达至发射区(4)的电流路径，从而饱和电流增大，短路耐量降低。肖特基接触区(6)与发射区(4)通过上部体区(8a)而被分离，通过选择上部体区(8a)的杂质浓度，从而能够避免饱和电流的增大。或者，也可以在分离肖特基接触区(6)和发射区(4)的范围内附加隔断结构，该隔断结构使从肖特基接触区(6)向上部体区(8a)内延伸的耗尽层和从发射区(4)向上部体区(8a)内延伸的耗尽层不相连。

Description

内置有二极管的IGBT
技术领域
在本说明书中公开一种在同一半导体基板上制作有IGBT(InsulatedGateBipolarTransistor，绝缘栅双极性晶体管)和二极管双方的半导体装置(称为内置有二极管的IGBT)。特别公开一种使IGBT的导通电压降低，并且防止饱和电流的增大从而防止短路耐量的降低的技术。
背景技术
IGBT具备通过第二导电型(例如p型)的体区而将第一导电型(例如n型)的发射区和第一导电型的漂移区分离的结构。如专利文献1所记载的那样，已知一种在第二导电型的体区中插入第一导电型的势垒层，通过该势垒层而分离为与发射区相接的体区和与漂移区相接的体区的技术。通过该技术，能够抑制少数载流子从漂移区逸出到发射极的情况，从而能够使电导率调制活化由此降低IGBT导通时的电阻(导通电压降低)。
专利文献1还公开了一种通过将IGBT和续流二极管(FreeWheelingDiode)制作在同一半导体基板上从而实现反向导通IGBT(RC(ReverseConducting)-IGBT)的技术。或者，还已知一种通过将IGBT和二极管制作在同一半导体基板上从而防止栅绝缘膜的破坏等的技术。
在先技术文献
专利文献
专利文献1：日本特开2012-43890号公报
发明内容
发明所要解决的课题
在并用向体区插入势垒层而使电导率调制活化的技术与将IGBT和二极管制作在同一半导体基板上的技术的情况下，设置从半导体基板的表面起贯穿与发射区相接的体区并到达势垒层的半导体区域是较为有效的。利用从半导体基板的表面起贯穿第二导电型体区并到达至第一导电型势垒层的第一导电型半导体区域来形成肖特基二极管的技术在日本特愿2012-166576号的说明书和附图中被公开。然而，该申请在本申请的申请时间点尚未被公开。
图1为示意性地表示将利用从半导体基板的表面起到达至势垒层的区域(称为肖特基接触区)来形成肖特基二极管的技术组合到IGBT中的情况的一个示例的图。附图标记2为半导体基板的表面，4为发射区，6为肖特基接触区，8为体区，10为势垒层，12为漂移区，14为集电区，16为栅电极，18为栅绝缘膜，20为半导体基板的背面。发射区4、肖特基接触区6、势垒层10、漂移区12为第一导电型(例如n型)，体区8和集电区14为第二导电型(例如p型)。体区8通过势垒层10而被分离为与发射区4相接的上部体区8a和与漏极区12相接的下部体区8b。肖特基接触区6从半导体基板的表面2起贯穿上部体区8a并到达至势垒层10。在半导体基板的表面2上形成有未图示的发射极。发射极与发射区4和上部体区8a欧姆接触，与肖特基接触区6肖特基接触，并通过栅绝缘膜18而与栅电极16绝缘。在半导体基板的背面20上形成有未图示集电极。集电极与集电区14欧姆接触。发射极为肖特基二极管的阳极电极，集电极为肖特基二极管的阴极电极。
通常以发射极被接地，在集电极上施加有正电压的状态而使用。该状态相当于反向偏压被施加于肖特基二极管上的状态。在以下，例示第一导电型为n型，第二导电型为p型的情况。当向栅电极16施加正电压时，隔着栅绝缘膜18而与栅电极16对置的范围内的体区8反转为n型，从而发射区4、反转的上部体区8a、势垒层10、反转的下部体区8b、漂移区12导通，电子从发射极向漂移区12注入。于是，空穴从集电极经由集电区14而向漂移区12注入，从而在漂移区12内产生电导率调制，发射极与集电极之间导通。由于利用电导率调制，因此导通电压较低。由于当存在势垒层10时，将抑制被注入到漂移区12内的空穴逸出到发射极的情况，因此电导率调制活化，从而进一步降低导通电压。当停止向栅电极16施加正电压时，被形成在体区8内的反转层将消失，从而发射极与集电极之间被断开。通过发射区4、上部体区8a、势垒层10、下部体区8b、漂移区12、集电区14、栅电极16、栅绝缘膜18等而形成了IGBT。
发射极与集电极之间被断开时，由于与IGBT连接的负载电路的感应成分，发射极的电位将高于集电极的电位。该情况下，正向偏压将施加于发射极(二极管的阳极电极)与肖特基接触区6之间的肖特基界面上，从而在肖特基二极管中将流通有正向电流。肖特基二极管作为续流二极管而动作。当感应成分的影响消失从而发射极的电位低于集电极的电位时，反向偏压将施加在发射极与肖特基接触区6之间的肖特基界面上，从而阻止电流在两者之间流通的情况。通过发射极与肖特基接触区6等而形成了肖特基二极管。虽然在上述内容中，对肖特基二极管作为续流二极管而动作的示例进行了说明，但有时也会为了防止在发射极与集电极之间的电压增大时栅绝缘膜18受到损伤的情况，而在IGBT中组装二极管。
利用势垒层10与肖特基接触区6的内置有二极管的IGBT具有IGBT导通时的集电极与发射极之间的电阻较低，从而漏电流较低的特性，因而为低损耗。相反地，存在饱和电流较高，从而在负载电路等发生短路时容易遭到破坏的问题。在本说明书中，公开一种利用势垒层10与肖特基接触区6，并且不容被破坏的技术。
本说明书所记载的技术基于如下的分析，即，当利用势垒层10与肖特基接触区6来改善特性时，为何短路耐量会降低的分析。图1中的箭头A表示经由在IGBT导通时所形成的反转层的电流路径。未同时设置有二极管的IGBT的电流路径仅为箭头A。与此相对，箭头B表示从被形成在下部体区8b内的反转层起经由势垒层10与肖特基接触区6并到达至发射区4的电流路径。当利用势垒层10与肖特基接触区6而同时设置二极管时，将产生新的电流路径B。尽管在肖特基接触区6与发射区4之间夹有相反导电型的上部体区8a，但当实际测量时，电流将从肖特基接触区6起经由上部体区8a而流向发射区4。另外，在IGBT导通的期间，在肖特基接触区6与发射极之间作用有反向偏压，从而电流不会从肖特基接触区6流向发射极。
上部体区8a通过从半导体基板的表面2注入杂质后扩散而形成。这时，由于以侵入至距表面2一定程度的距离的深度处的能量注入杂质，因此与从表面侵入了一定程度的深度处的杂质浓度相比，表面2的附近的杂质浓度较低。明确了在电流从肖特基接触区6经由上部体区8a而向发射区4流通的情况下，与包含较多的相反导电型的杂质的上部体区8a的深部相比，电流将沿着相反导电型的杂质浓度较低的上部体区8a的表面流通。即，明确了在沿着杂质浓度较低的上部体区8a的表面的位置处，发生了从肖特基接触区6向上部体区8a延伸的耗尽层与从发射区4向上部体区8a延伸的耗尽层连通的击穿(punchthrough)，因此电流从肖特基接触区6经由上部体区8a而向发射区4流通。
图2表示发射极与集电极之间的电压同电流的关系。曲线C1表示未同时设置有二极管的IGBT的测量结果，曲线C2表示同时设置有利用势垒层10与肖特基接触区6的二极管的IGBT的测量结果。未同时设置有二极管的IGBT的饱和电流为IA，与此相对，同时设置有势垒层10与肖特基接触区6的IGBT的饱和电流增加至IA+IB。分析的结果明确了IA为箭头A的电流路径的电流，IB为箭头B的电流路径的电流。明确了当同时设置势垒层10与肖特基接触区6时，由于附加了电流路径B，因而饱和电流增大。
图2的VCC表示被施加于IGBT与负载电路的电源电压。当负载电路短路时，电源电压VCC将被施加于IGBT。在负载电路短路时，在半导体装置中每单位时间将产生饱和电流×电源电压(W＝J/sec)的能量，从而内置有二极管的IGBT会发热。可知当同时设置势垒层10与肖特基接触区6时，短路时在内置有二极管的IGBT中产生的能量将从VCC×IA增加至VCC×(IA+IB)。明确了当同时设置势垒层10与肖特基接触区6时，由于每单位时间的发热量增大，因此内置有二极管的IGBT的升温速度变大，达到破坏温度的时间变短，从而短路耐量降低。
在本说明书中公开一种在利用势垒层与肖特基接触区来改善半导体装置的特性的同时，内置有二极管的IGBT不易被破坏的技术。
用于解决课题的方法
上述的分析的结果明确了在已知的内置有二极管的IGBT中，由于在上部体区的表面附近，肖特基接触区与发射区之间发生击穿，从而短路耐量降低。在本说明书中公开一种防止击穿的发生从而防止短路耐量的降低的技术。
(第一解决方法)
当将从肖特基接触区延伸至上部体区内的耗尽层的距离与从发射区延伸至上部体区内的耗尽层的距离合计而得到的距离(合计距离)成为肖特基接触区与发射区之间的距离以上时，将发生击穿。该合计距离取决于肖特基接触区与发射区之间的电位差(由于在IGBT导通的状态下，反向偏压将作用于发射极与肖特基接触区之间，因而肖特基接触区的电位与发射极的电位(等于发射区的电位)不同)与存在于上部体区内的电荷量。如果电位差较大则合计距离较长，如果电荷量较大则合计距离较短。电位差能够通过测量或分析来掌握。只要调节为成为“通过该电位差而产生的合计距离小于肖特基接触区与发射区之间的距离”的关系的电荷量，便能够防止击穿的发生。通常通过注入一价的离子来调节上部体区的导电型。该情况下，电荷量与杂质浓度成比例。
在耗尽层向上部体区内延伸的距离W、上部体区的杂质浓度N、肖特基接触区与发射区的电压差V之间，下式成立。
W2＝2·Es·(Vbi―V)/(q·N)(1)
在上述中，Es为半导体的介电常数、Vbi为内置电位、q为元电荷。
当将肖特基接触区与发射区之间的距离设为L时，由式(1)可知，在
N＞2·Es·(Vbi―V)/(q·L2)(2)
的情况下，成为W＜L，从而能够获得肖特基接触区与发射区之间不会发生击穿的结果。在式(2)中，介电常数Es与元电荷q为已知，内置电位Vbi、肖特基接触区与发射区之间的距离L、肖特基接触区与发射区之间的电压差V能够测量出。因此，能够根据式(2)而确定不使肖特基接触区与发射区之间发生击穿所需要的杂质浓度。
如上所述，采用现有技术时的上部体区的表面附近的杂质浓度较低，不满足式(2)。当提高该浓度时，将能够获得肖特基接触区与发射区之间不发生击穿的结果。当进一步提升该浓度时，能够获得如下的结果，即，不会形成图1的箭头B所示的电流路径，从而不会产生饱和电流增大的问题，由此短路时的升温速度不会上升，短路耐量不会降低的结果。
当使上部体区的至少表面附近的杂质浓度上升至不使肖特基接触区与发射区之间发生击穿的浓度时，即使形成势垒层与肖特基接触区，短路耐量也不会降低。
(第二解决方法)
可以在肖特基接触区与发射区之间形成防止击穿的发生的区域。例如，可以在位于肖特基接触区与发射区之间的上部体区的表面上形成从表面起在深度方向上延伸的绝缘区域。也可以代替绝缘区域，而使用沟槽栅电极与栅绝缘膜的组合。或者也可以在上部体区的表面附近形成与上部体区相比为高浓度的区域。无论采用哪种方式，都会对从肖特基接触区向上部体区延伸的耗尽层与从发射区向上部体区延伸的耗尽层之间进行隔断，从而防止击穿的发生。无论是哪一个隔断区域，只需以横穿击穿发生的位置的方式而形成即可，无需遍及上部体区的整个厚度部分，并且也无需完全包围肖特基接触区或发射区。
发明效果
根据本说明书所记载的技术，
(1)能够利用势垒层而抑制少数载流子从漂移区逸出至发射极的情况，从而使电导率调制活化。
(2)能够形成肖特基二极管结构，该肖特基二极管结构利用发射极(成为肖特基电极)、肖特基接触区和势垒层。
(3)当IGBT导通时，能够不使从势垒层经由肖特基接触区和上部体区并到达至发射区的电流路径形成，从而能够抑制饱和电流的增大。能够防止短路耐量的降低。
附图说明
图1为示意性地表示内置有二极管的IGBT的半导体结构的图。
图2为表示势垒层和肖特基接触区存在时和不存在时的饱和电流的图。
图3为示意性地表示第二实施例的内置有二极管的IGBT的半导体结构的图。
图4为俯视观察图3的内置有二极管的IGBT时的图。
图5为俯视观察第三实施例的内置有二极管的IGBT时的图。
图6为俯视观察第四实施例的内置有二极管的IGBT时的图。
图7为俯视观察第五实施例的内置有二极管的IGBT时的图。
具体实施方式
首先列出在以下进行说明的实施例的特征。
(第一实施例的特征)在分离肖特基接触区与发射区的上部体区中未形成有与上部体区不同的组成的区域。分离肖特基接触区和发射区的范围内的上部体区的杂质浓度相同。
(第二实施例的特征)在p型的上部体区中形成有与其相比为高浓度的p型区域。在俯视观察半导体基板时，该高浓度p型区域包围肖特基接触区。
(第五实施例的特征)被形成在沟槽的内部的绝缘体和所述高浓度p型区域复合并包围肖特基接触区。
实施例
通过实施例对本说明书中公开的技术的详细内容和进一步的改良进行说明。
(第一实施例)
第一实施例的半导体结构如同图1所示。省略已进行了说明的事项的重复说明。如图1所示，在分离肖特基接触区6与发射区4的范围内的上部体区8a中，未形成有与上部体区8a不同的组成的区域。第一实施例的半导体结构如同图1所示。在第一实施例的内置有二极管的IGBT中，半导体基板的表面2的附近的上部体区8a的杂质浓度较浓，从而禁止了肖特基接触区6与发射区4发生击穿的情况。由此防止了短路耐量的降低。也可以在漂移区12与集电区14之间设置防止耗尽层到达至集电区14的隔断区域。对于该隔断区域将在第二实施例中进行说明。
在图1中，将在俯视观察半导体基板的表面2时，肖特基接触区6与发射区4之间的最短距离设为L。此外，将上部体区8a的表面附近的杂质浓度设为N。该杂质设为1价杂质。该情况下，如果杂质浓度N满足下式，则肖特基接触区6和发射区4之间就不会发生击穿。
N＞2·Es·(Vbi-V)/(q·L2)(2)
在上述中，Es为半导体的介电常数，Vbi为内置电位，q为元电荷。
在第一实施例的内置有二极管的IGBT中，半导体基板的表面2的附近的上部体区8a的杂质浓度N满足式(2)，从而禁止了肖特基接触区6和发射区4发生击穿的情况。由此防止了短路耐量的降低。
当将IGBT的栅极导通电压设为Vg，将IGBT的阈值电压设为Vth时，肖特基接触区6和势垒层10的电位不会超过Vg-Vth。在Vg＝15V，Vth＝6V的情况下，Vg-Vth＝9V，由式(2)可知，防止发生击穿所需的电荷量(L·N)为1.2E12cm—2。由此，能够决定杂质浓度N和距离L。
(第二实施例)
参照图3和图4对第二实施例进行说明。下面只对与图1不同的点进行说明，而省略重复说明。在第二实施例的内置有二极管的IGBT中，形成有二极管和IGBT双方的范围C与只形成有二极管的范围D被交替地设置。
在范围C中，形成有发射区4和肖特基接触区6双方。在第二实施例中，在栅电极16的长度方向上，发射区4和肖特基接触区6被形成在不同的位置。在p型的上部体区8a的表面附近形成有与其相比p型杂质的浓度较浓的高浓度区域22。当俯视观察半导体基板的表面2时，高浓度区域22被形成在包围肖特基接触区6的范围内。高浓度区域22被形成在上部体区8a的表面附近并且分离肖特基接触区6和发射区4的范围内。当形成高浓度区域22时，通过高浓度区域22能够满足所述式(2)。因此，能够自由地调节上部体区8a的杂质浓度。能够降低体区8的杂质浓度从而降低IGBT的阈值电压。此外，当形成高浓度区域22时，即使将肖特基接触区6和发射区4之间的最短距离缩短为L，也能够不使击穿发生，从而能够实现元件的小型化。
在第二实施例中，漂移区12和集电区14之间形成有防止耗尽层到达至集电区14的隔断区域13。隔断区域13通过以高浓度注入有n型的杂质的区域而形成。
此外，在只形成有二极管的范围D内，未形成有发射区4，并且代替p型的集电区14而形成有n型的阴极区15。在范围D内，由于不存在发射区，从而不需要高浓度区域22。虽然不需要，但也可以与范围C相同，形成高浓度区域22。
高浓度区域22与发射极欧姆接触，使体区8的电位与发射极的电位相等。当体区8的电位稳定时，IGBT的运转状态稳定。高浓度区域22防止发射区4和肖特基接触区6发生击穿的情况，并成为使体区8的电位稳定的体接触区。
(第三实施例)
如图5所示，高浓度区域22a只需被形成在半导体基板的表面2附近的分离肖特基接触区6和发射区4的范围内即可，也可以被形成在从肖特基接触区6分离的范围内。肖特基接触区6和高浓度区域22a为相反导电型，当分离两者时，能够防止因制造时的公差而使杂质的注入范围重叠的情况，从而易于使肖特基接触区6的杂质浓度和高浓度区域22a的杂质浓度分别最佳化。或者，防止由于高浓度区域22a的制造而使肖特基接触区6的尺寸发生变动的情况。
(第四实施例)
如图6所示，存在有在半导体基板的表面2上，栅电极16和栅绝缘膜18以格子状延伸的情况。该情况下，能够使用图6所示的形状的高浓度区域22b。
(第五实施例)
如图7所示，通过并用高浓度区域22c和栅绝缘膜18也能够对肖特基接触区6和发射区4进行分离。由于高浓度区域22c和栅绝缘膜18都能够阻止耗尽层的伸长，因而能够通过并用高浓度区域22c和栅绝缘膜18来防止肖特基接触区6和发射区4发生击穿的情况。
(第六实施例)
虽然未图示，但也可以代替图3至图7中例示的高浓度区域22、22a、22b、22c，而使用覆盖沟槽的壁面的绝缘膜。该情况下也能够防止肖特基接触区6和发射区4发生击穿的情况。当用绝缘膜来防止击穿的发生的情况下，用较薄的绝缘层即可，从而能够实现元件的小型化。
(第七实施例)
当使用第六实施例的沟槽的情况下，既可以向沟槽中填充绝缘体，也可以用绝缘膜覆盖沟槽的壁面，并向其内侧填充导体。后者的情况下，通过栅绝缘膜而将肖特基接触区6和发射区4分离。
参照附图，对本发明的代表性且非限定性的具体示例进行了详细说明。该详细说明只是旨在向本领域技术人员示出用于实施本发明的优选示例的详细内容，而并非旨在对本发明的范围进行限定。此外，所公开的追加特征以及发明能够与其他的特征或发明分开或者一起使用，以提供进一步被改善的半导体装置及其制造方法。
此外，在上述的详细说明中所公开的特征或工序的组合并非为在最广泛的意义上实施本发明时所必须的，其只不过是用于特别地对本发明的代表性的具体示例进行说明而被记载的。而且，上述的代表性的具体示例的各种特征以及独立和从属权利要求中所述的各种特征，在提供本发明的追加且有用的实施方式时，并不一定要如在此所记载的具体示例那样或如所列举的顺序那样进行组合。
本说明书和/或权利要求书中所记载的全部特征旨在独立于实施例和/或权利要求中所记载的特征的结构，作为对申请原始的公开以及权利要求书中所记载的特定事项的限定，而单独地且互相独立地被公开。而且，关于所有的数值范围以及组或集合的记载的意图在于，作为对申请原始的公开以及权利要求书中所记载的特定事项的限定，而公开它们的中间的结构。
以上，虽然对本发明的具体示例进行了详细说明，但是这些只不过是示例，并不对权利要求书进行限定。权利要求书中所记载的技术包含对以上所例示的具体示例进行了各种的改变、变更的内容。在本说明书或附图中所说明的技术要素以单独或者各种组合的方式而发挥技术上的有用性，并不限定于申请时权利要求所记载的组合。此外，本说明书或者附图所例示的技术能够同时实现多个目的，并且实现其中一个目的本身便具有技术上的有用性。
符号说明
2：半导体基板的表面；
4：发射区；
6：肖特基接触区；
8：体区；
8a：上部体区；
8b：下部体区；
10：势垒层；
12：漂移区；
13：隔断区域；
14：集电区；
15：阴极区；
16：栅电极；
18：栅绝缘膜；
20：半导体基板的背面；
22、22a、22b、22c：高浓度区域。

Claims (2)

1.一种内置有二极管的绝缘栅双极性晶体管，其在半导体基板内依次配置有发射区、上部体区、势垒层、下部体区、漂移区和集电区，并混合具有绝缘栅双极性晶体管结构和肖特基二极管结构，
在绝缘栅双极性晶体管结构中，
形成有从半导体基板的表面起贯穿发射区、上部体区、势垒层、下部体区并到达至漂移区的沟槽，
该沟槽的壁面被绝缘膜所覆盖，
在壁面被绝缘膜所覆盖的沟槽的内部配置有栅电极，
在半导体基板的表面上形成有与发射区导通的发射极，
在半导体基板的背面上形成有与集电区导通的集电极，
在肖特基二极管结构中，具备贯穿上部体区并到达至势垒层且与发射极肖特基接触的肖特基接触区，
在半导体基板的表面处，肖特基接触区与发射区通过上部体区而被分离，该分离部的杂质浓度被设定为满足如下的关系的浓度，即，被形成在分离部中的耗尽层的距离小于肖特基接触区与发射区的分离距离的关系。
2.一种内置有二极管的绝缘栅双极性晶体管，其在半导体基板内依次配置有发射区、上部体区、势垒层、下部体区、漂移区和集电区，并混合具有绝缘栅双极性晶体管结构和肖特基二极管结构，
在绝缘栅双极性晶体管结构中，
形成有从半导体基板的表面起贯穿发射区、上部体区、势垒层、下部体区并到达至漂移区的沟槽，
该沟槽的壁面被绝缘膜所覆盖，
在壁面被绝缘膜所覆盖的沟槽的内部配置有栅电极，
在半导体基板的表面上形成有与发射区导通的发射极，
在半导体基板的背面上形成有与集电区导通的集电极，
在肖特基二极管结构中，具备贯穿上部体区并到达至势垒层且与发射极肖特基接触的肖特基接触区，
在半导体基板的表面处，肖特基接触区与发射区通过上部体区而被分离，
在该分离部中形成有隔断区域，该隔断区域对从肖特基接触区向分离部延伸的耗尽层和从发射区向分离部延伸的耗尽层进行隔断。
CN201380076833.XA 2013-05-23 2013-05-23 内置有二极管的igbt Pending CN105378931A (zh)

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