JP6483843B2 - アレイ基板及びその製造方法、表示装置 - Google Patents
アレイ基板及びその製造方法、表示装置 Download PDFInfo
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Description
11 ゲートライン
12 データライン
13 薄膜トランジスター
131 ゲート電極
132 ゲート絶縁層
1321 第1ゲート絶縁部
1322 第2ゲート絶縁部
133 活性層
134 ソース電極
135 ドレイン電極
136 遮光層
137 絶縁層
14 導電性パッド
15 第1ビアホール
16 第2ビアホール
17 パッシベーション層
18 画素電極
Claims (10)
- ベース基板と、前記ベース基板上で横縦方向に交差して配置されたゲートラインおよびデータラインとを備え、画素ユニットが前記ゲートライン及び前記データラインに囲まれてなり、前記画素ユニット内に薄膜トランジスターが設置され、前記薄膜トランジスターがゲート電極、ゲート絶縁層、活性層、ソース電極、及びドレイン電極を含み、前記ゲート絶縁層が第1ゲート絶縁部及び第2ゲート絶縁部を含み、前記ゲート電極が前記第1ゲート絶縁部と前記第2ゲート絶縁部との間に位置し、前記第2ゲート絶縁部が前記ゲート電極と前記活性層との間に位置し、
アレイ基板が、前記ゲートラインと前記データラインとの交差位置に位置する導電性パッドを更に備え、
前記第1ゲート絶縁部、前記第2ゲート絶縁部および前記ゲートラインが前記導電性パッドの前記ベース基板と反対の側に配置されており、
前記ゲートラインの両側に位置する前記ゲート絶縁層に、前記導電性パッドに対応する第1ビアホールが設置され、前記データラインが前記第1ビアホールを介して前記導電性パッドに接続されるアレイ基板。 - 前記ゲートラインに垂直な方向において、前記導電性パッドの寸法が前記ゲートラインの寸法よりも大きい請求項1に記載のアレイ基板。
- 前記薄膜トランジスターの箇所において、前記第1ゲート絶縁部、前記ゲート電極、前記第2ゲート絶縁部、前記活性層、同一層に設置された前記ソース電極及びドレイン電極が、前記ベース基板から離れる方向に向けて前記ベース基板上に順次に設置され、
前記ゲートラインと前記データラインとが交差する箇所において、前記導電性パッド、前記第1ゲート絶縁部、前記ゲートライン、前記第2ゲート絶縁部、及び前記データラインが、前記ベース基板から離れる方向に向けて前記ベース基板上に順次に設置される、請求項1または2に記載のアレイ基板。 - 前記薄膜トランジスターの箇所において、同一層に設置された前記ソース電極及びドレイン電極、前記活性層、前記第2ゲート絶縁部、前記ゲート電極、前記第1ゲート絶縁部が、前記ベース基板から離れる方向に向けて前記ベース基板上に順次に設置され、前記データラインが前記ゲート絶縁層における第2ビアホールを介して前記ソース電極に接続され、
前記ゲートラインと前記データラインとが交差する箇所において、前記導電性パッド、前記第2ゲート絶縁部、前記ゲートライン、前記第1ゲート絶縁部、及び前記データラインが、前記ベース基板上に順次に設置される、請求項1または2に記載のアレイ基板。 - 前記第2ゲート絶縁部の誘電率が前記第1ゲート絶縁部の誘電率よりも大きい請求項1から4のいずれか1項に記載のアレイ基板。
- 前記第1ゲート絶縁部の厚みが1000Å〜3000Åであり、前記第2ゲート絶縁部の厚みが1000Å〜3000Åである請求項5に記載のアレイ基板。
- 請求項1から6のいずれか1項に記載のアレイ基板を備える表示装置。
- ベース基板上に導電性パッド金属層を形成し、パターニング工程によって導電性パッドを含むパターンを形成し、
前記導電性パッドを含むパターンが形成された前記ベース基板上に、第1ゲート絶縁部を形成し、
前記第1ゲート絶縁部が形成された前記ベース基板上に、ゲート電極金属層を形成し、パターニング工程によってゲートライン及びゲート電極を含むパターンを形成し、
前記ゲートライン及び前記ゲート電極を含むパターンが形成された前記ベース基板上に、第2ゲート電極絶縁薄膜を形成し、パターニング工程によって第2ゲート絶縁部を形成し、
前記第2ゲート絶縁部が形成された前記ベース基板上に、半導体層を形成し、パターニング工程によって活性層を含むパターンを形成し、
パターニング工程によって、前記ゲートラインの両側における前記第1ゲート絶縁部および前記第2ゲート絶縁部に、前記導電性パッドに対応する第1ビアホールを形成し、
前記第1ビアホールが形成された前記ベース基板上に、ソース・ドレイン電極金属層を形成し、パターニング工程によってデータライン、ソース電極、及びドレイン電極を含むパターンを形成し、前記データラインと前記ゲートラインとが前記導電性パッドの上方で交差し、前記データラインが前記第1ビアホールを介して前記導電性パッドに接続される、アレイ基板の製造方法。 - ベース基板上にソース・ドレイン電極金属層を形成し、パターニング工程によってソース電極、ドレイン電極、及び導電性パッドを含むパターンを形成し、
前記ソース電極、前記ドレイン電極、及び前記導電性パッドを含むパターンが形成された前記ベース基板上に、半導体層を形成し、パターニング工程によって活性層を含むパターンを形成し、
前記活性層を含むパターンが形成された前記ベース基板上に、第2ゲート絶縁薄膜を形成し、パターニング工程によって第2ゲート絶縁部を形成し、
前記第2ゲート絶縁部が形成された前記ベース基板上に、ゲート電極金属層を形成し、パターニング工程によってゲートライン及びゲート電極を含むパターンを形成し、
前記ゲートライン及び前記ゲート電極を含むパターンが形成された前記ベース基板上に、第1ゲート絶縁部を形成し、
パターニング工程によって、前記第1ゲート絶縁部および前記第2ゲート絶縁部に、前記導電性パッドに対応する第1ビアホールと前記ソース電極に対応する第2ビアホールとを形成し、
前記第1ビアホール及び前記第2ビアホールが形成された前記ゲート絶縁層上にデータライン金属層を形成し、パターニング工程によってデータラインを含むパターンを形成し、前記データラインは、前記第1ビアホールを介して前記導電性パッドに接続され、前記第2ビアホールを介して前記ソース電極に接続される、アレイ基板の製造方法。 - 前記第1ゲート絶縁部及び前記第2ゲート電極絶縁薄膜を蒸着形成し、且つ、パターニング工程によって形成された前記第2ゲート絶縁部の誘電率が前記第1ゲート絶縁部の誘電率よりも大きくなるように、前記第2ゲート電極絶縁薄膜を蒸着形成する工程パラメータが前記第1ゲート絶縁部を蒸着形成する工程パラメータと異なる、請求項8または9に記載のアレイ基板の製造方法。
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