WO2020006717A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2020006717A1
WO2020006717A1 PCT/CN2018/094558 CN2018094558W WO2020006717A1 WO 2020006717 A1 WO2020006717 A1 WO 2020006717A1 CN 2018094558 W CN2018094558 W CN 2018094558W WO 2020006717 A1 WO2020006717 A1 WO 2020006717A1
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Prior art keywords
layer
gate
region
array substrate
thin film
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PCT/CN2018/094558
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English (en)
French (fr)
Inventor
管曦萌
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深圳市柔宇科技有限公司
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Priority to CN201880093834.8A priority Critical patent/CN112534566A/zh
Priority to PCT/CN2018/094558 priority patent/WO2020006717A1/zh
Publication of WO2020006717A1 publication Critical patent/WO2020006717A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • the capacitance value of the storage capacitor region of the array substrate is low, which cannot meet the requirements of high resolution of the display panel.
  • the present invention provides an array substrate manufacturing method, an array substrate, and a display device.
  • the present invention provides an array substrate manufacturing method, which includes the following steps:
  • At least one barrier layer is deposited on the substrate, and the thickness of the at least one barrier layer in the storage capacitor region is reduced by a patterning process.
  • an array substrate including:
  • a substrate including a thin film transistor region and a storage capacitor region
  • At least one barrier layer is located in the thin film transistor region and the storage capacitor region.
  • the thickness of the barrier layer in the thin film transistor region is smaller than the thickness of the barrier layer in the storage capacitor region.
  • the present invention provides a display device including the above array substrate.
  • FIG. 1 is a schematic cross-sectional view of an array substrate provided by a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of an array substrate provided by a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of an array substrate manufacturing method according to an embodiment of the present invention.
  • 5 to 22 are schematic cross-sectional views of a first embodiment of each manufacturing process of the manufacturing method of the array substrate shown in FIG. 4.
  • 23 to 41 are schematic cross-sectional views of a second embodiment of each manufacturing process of the manufacturing method of the array substrate shown in FIG. 4.
  • FIG. 1 is a schematic cross-sectional view of an array substrate provided by a first embodiment of the present invention.
  • the array substrate 100 includes a substrate 10.
  • the substrate 10 includes a thin film transistor region 101, a storage capacitor region 102 and a lead region 103.
  • the substrate 10 may be a flexible or inflexible substrate, and is configured to support the entire thin film transistor region 101, the storage capacitor region 102, and the lead region 103.
  • the substrate 10 is a polyimide (PI) substrate.
  • the substrate 10 may also be a polyamide (PA) substrate, a polycarbonate (PC) substrate, a polyethersulfone (PES) substrate, or poly (p-phenylene) Polyethylene terephthalate (PET) substrate, polyethylene naphthalate (PEN) substrate, polymethylmethacrylate (PMMA) substrate, cycloolefin copolymer COC) substrate.
  • the substrate 10 may be a curved curved surface whose curvature changes during use, or a fixed curved surface whose curvature does not change, and may also be a flat surface.
  • the thin film transistor region 101 includes a light shielding metal layer 21, a barrier layer 30, an active layer 41, a gate dielectric layer 51, a gate 61, and an interlayer insulating layer 70 disposed on the substrate 10 in this order.
  • the light-shielding metal layer 21 and the active layer 41 are spaced apart and oppositely disposed.
  • the light shielding metal layer 21 and the active layer 41 are stacked.
  • the light shielding metal layer 21 may be a light reflecting layer.
  • the light-reflecting layer is configured to reflect the light irradiated from the substrate 10 side, so as to block the light irradiated from the substrate 10 side, thereby preventing the light from irradiating the active layer 41 of the thin film transistor region 101.
  • the material of the light-shielding metal layer 21 may be a metal having a good reflection effect.
  • the metal is, for example, but is not limited to aluminum or silver. Since aluminum has a high reflectance in a wide spectral range, it can have a good reflection effect on the light used during peeling, so the material of the light-shielding metal layer 21 is preferably aluminum. In addition, aluminum is widely used and reasonably priced. It can be understood that, in other embodiments, the material of the light-shielding metal layer 21 may also be an organic reflective material.
  • the blocking layer 30 is disposed above the light-shielding metal layer 21 and covers the light-shielding metal layer 21.
  • the material of the barrier layer 30 is an inorganic insulating material.
  • the inorganic insulating material is, for example, but is not limited to, silicon nitride (SiNx) or silicon oxide (SiOx). It can be understood that, in other embodiments, the barrier layer 30 may also be another water-oxygen barrier layer.
  • the active layer 41 is disposed above the blocking layer 30.
  • the active layer 41 includes a contact doped region 411 disposed at both ends thereof and a channel 412 disposed between the two contact doped regions.
  • the contact doped region 411 includes a source region 4111 and a drain region 4112.
  • the gate dielectric layer 51 is disposed above the active layer 41.
  • the gate dielectric layer 51 is overlapped with the channel 412 of the active layer 41.
  • the gate 61 is disposed above the gate dielectric layer 51 and is spaced from and opposite to the channel 412 of the active layer 41. In this embodiment, the gate electrode 61 and the channel 412 of the active layer 41 are arranged one above the other.
  • the interlayer insulating layer 70 is disposed above the gate 61 and covers the gate 61, the gate dielectric layer 51, the active layer 41, and the barrier layer 30.
  • the interlayer insulation layer 70 defines two opposite source contact holes 701 and drain contact holes 702, and the source contact holes 701 and the drain contact holes 702 penetrate the interlayer insulation layer 70 and make The contact doped region 411 of the active layer 41 is exposed.
  • the thin film transistor region 101 further includes a source electrode 81 and a drain electrode 82.
  • the thin film transistor region 101 is in the form of a top gate, that is, the source electrode 81 and the leakage level 82 are disposed on the same side of the gate 61 opposite to the active layer 41.
  • the source electrode 81 and the drain electrode 82 are both disposed on the interlayer insulating layer 70, and are in contact with the active layer 41 through the source contact hole 701 and the drain contact hole 702, respectively.
  • the doped regions 411 are electrically connected.
  • the storage capacitor region 102 includes a first pole piece 22, a dielectric barrier layer 32, a capacitor dielectric layer 53, and a second pole piece 62 that are sequentially stacked on the substrate 10.
  • the capacitive dielectric layer 53 is disposed between the first pole piece 22 and the second pole piece 62 and is spaced from the gate dielectric layer 51 of the thin film transistor region 101.
  • the thickness of the capacitor dielectric layer 53 is smaller than the thickness of the gate dielectric layer 51, so that the distance between the first pole piece 22 and the second pole piece 62 is reduced, thereby increasing the storage capacitor area 102. Capacitor value.
  • the first pole piece 22 of the storage capacitor area 102 and the light-shielding metal layer 21 of the thin film transistor area 101 are disposed on the same layer, and the distance between the first pole piece 22 and the second pole piece 62 is less than A distance between the light shielding metal layer 21 and the gate electrode 61.
  • the dielectric barrier layer 32 of the storage capacitor region 102 is in contact with the barrier layer 30 of the thin film transistor region 101, and the dielectric barrier layer 32 is disposed on the same layer as the barrier layer 30.
  • the material of the dielectric barrier layer 32 is the same as the material of the barrier layer 30.
  • the dielectric barrier layer 32 may be a barrier layer 30 of the thin film transistor region 101.
  • the thickness of the dielectric barrier layer 32 is smaller than the thickness of the barrier layer 30, thereby further reducing the distance between the first pole piece 22 and the second pole piece 62, thereby increasing the Capacitance.
  • the “same layer setting” means that both structures are formed by the same material layer through the same step of deposition and the same step of the patterning process, so the two are at the same level in the stacked relationship.
  • the storage capacitor region 102 further includes a third pole piece 83, and the third pole piece 83 is connected to the drain electrode 82 of the thin film transistor area 101 so that it becomes a part of a circuit.
  • the third pole piece 83 may be a part of the drain electrode 82 of the thin film transistor region.
  • the second pole piece 62 and the third pole piece 83 are connected to form an electrode of the storage capacitor region 102 together. It can be understood that, in other embodiments, the third pole piece 83 may not be connected to the drain electrode 82 of the thin film transistor region 101, that is, the user may perform a connection design between electrodes according to an actual circuit line.
  • An interlayer insulation layer 70 of the thin film transistor region 101 is further sandwiched between the second pole piece 62 and the third pole piece 83, and an interlayer insulation layer is opened in the interlayer insulation layer 70 and penetrates the interlayer insulation layer 70
  • the capacitor pole piece of 70 contacts the hole 703.
  • the third pole piece 83 is electrically connected to the second pole piece 62 through the capacitor pole piece contact hole 703.
  • the gate 61 can also be similar to the contact hole 703 in the storage capacitor region 102 again.
  • the third pole piece 83 is drawn out from a metal line provided in the same layer. Therefore, the third pole piece 83 provides a degree of freedom of routing for the gate 61, the source area 4111, and the drain area 4112 of the thin film transistor area 101 and the second pole piece 62 of the storage capacitor area 102, respectively.
  • the lead region 103 includes a conductive layer 23 and an electrode lead 84 disposed on the substrate 10.
  • a dielectric barrier layer 32 and an interlayer insulating layer 70 of the storage capacitor region 102 are sandwiched between the conductive layer 23 of the lead region 103 and the electrode lead 84, and penetrate through the dielectric barrier layer 32 and the layer.
  • the electrode lead 84 leads the conductive layer 23 through the via 704, that is, the conductive layer 23 is electrically connected to the electrode lead 84, so that the electrode lead 84 can be the first pole piece 22 of the storage capacitor region 102.
  • FIG. 2 is a schematic cross-sectional view of an array substrate according to a second embodiment of the present invention.
  • the structure of the array substrate 200 of the second embodiment is similar to that of the array substrate 100 described in the first embodiment. Therefore, the size, name, and positional relationship of each element included in the array substrate 200 can be referred to in the first embodiment.
  • the array substrate 100 is described, and is not repeated here.
  • the barrier layer 31 of the array substrate 200 includes a first barrier layer 311 and a second barrier layer 312.
  • the first barrier layer 311 is located in the thin film transistor region 201 and the storage capacitor region 202.
  • a lead region 203, the second blocking layer 312 is located in the thin film transistor region 201.
  • the first barrier layer 311 and the second barrier layer 312 may be made of different materials, or may be made of the same material but different impurity concentrations.
  • the dielectric constant of the first blocking layer 311 is greater than the dielectric constant of the second blocking layer 312.
  • the second blocking layer 312 is disposed between the first blocking layer 311 and the active layer 41.
  • the first barrier layer 311 is connected to the dielectric barrier layer 32 and is disposed in the same layer, that is, the first barrier layer 311 of the thin film transistor region 201 can be used as the dielectric barrier layer 32 of the storage capacitor region 202.
  • the second blocking layer 312 and the active layer 41 are stacked.
  • the thickness of the first blocking layer 311 is smaller than the thickness of the second blocking layer 312, so that the distance between the first pole piece 22 and the second pole piece 62 of the storage capacitor region 202 can be further reduced, thereby increasing the distance.
  • the capacitance value of the storage capacitor area 202 is smaller than the thickness of the second blocking layer 312, so that the distance between the first pole piece 22 and the second pole piece 62 of the storage capacitor region 202 can be further reduced, thereby increasing the distance.
  • the display device 1000 includes the array substrates 100 and 200 described in the first and second embodiments.
  • the array substrates 100 and 200 may include circuits for implementing different functions (such as a gate driving circuit and a pixel circuit). ), And thin film transistors and storage capacitors.
  • the display device 1000 may be a flexible display device or a non-flexible display device.
  • the flexible display device 1000 is, for example, but is not limited to, a liquid crystal display (LCD), a quantum dot display (Quantum Dot Light Emitting Diodes, QLED), a mobile phone, a tablet computer, a navigator and other products with a display function or component.
  • LCD liquid crystal display
  • QLED Quantum Dot Light Emitting Diodes
  • FIG. 4 is an implementation flow of the manufacturing method of the array substrate 100 according to the first embodiment of the present invention.
  • the manufacturing method of the array substrate 100 includes the following steps:
  • step 403 a substrate is provided, and a thin film transistor region and a storage capacitor region are formed on the substrate.
  • step 405 at least one barrier layer is sequentially deposited on the substrate, and the thickness of the at least one barrier layer in the storage capacitor region is reduced by a patterning process.
  • the method further includes:
  • the gate insulating layer and the semiconductor layer are sequentially patterned, a pattern including an active layer is formed through a single patterning process, and a pattern including a gate dielectric layer is formed through a second patterning process.
  • the specific steps of forming the thin film transistor region 101 and the storage capacitor region 102 on the substrate 10 are:
  • a first photoresist 1 is coated on the light shielding layer 20, and the light shielding layer 20 is patterned by using a first mask plate 2 to form a plurality of light shielding structures 204 arranged at intervals.
  • the thin film transistor region 101, the storage capacitor region 102, and the lead region 103 are defined on the substrate 10, that is, the light shielding structure 204 can be used as a light shielding metal of the thin film transistor region 101.
  • the method further includes:
  • An interlayer insulating layer and an electrode layer are sequentially deposited and patterned on the gate.
  • a gate metal layer is deposited on a side surface of the gate insulating layer, a side surface of the active layer, and an exposed surface of at least one of the barrier layers; and coating a third photoresist on the gate metal layer, And using the same third mask to pattern the gate metal layer and the gate insulating layer to form a pattern including a gate of the thin film transistor region, a gate dielectric layer, and a second pole piece of the storage capacitor region.
  • the method includes the following steps: sequentially depositing a capacitor insulating layer and the gate metal layer on a side surface of the gate insulating layer, a side surface of the active layer, and an exposed surface of at least one of the barrier layers; A third photoresist is coated on the layer, and the gate metal layer, the capacitor insulation layer, and the gate insulation layer are sequentially patterned using the same third reticle to form a gate including the thin film transistor region. A pattern of a pole and a gate dielectric layer, and a second pole piece and a capacitor dielectric layer of the storage capacitor region.
  • the barrier layer 30, the semiconductor layer 40 (that is, a metal oxide layer), and the barrier layer 30 are continuously deposited on the light shielding structures 204.
  • Mentioned gate insulating layer 50 since the semiconductor layer 40 and the gate insulating layer 50 are continuously deposited, that is, the semiconductor layer 40 is not subjected to photolithography and etching steps before the gate insulating layer 50 is deposited, so Avoiding directly coating the semiconductor layer 40 with photoresist and removing the photoresist from causing contamination to the channel surface of the subsequent preparation of the active layer, thereby improving the performance and reliability of the thin film transistor region 101.
  • the blocking layer 30 and the semiconductor layer 40 are both stacked on the substrate 10, and the blocking layer 30 covers the light shielding structures 204.
  • the material of the substrate 10 may be glass or plastic, and the substrate 10 may also be a flexible substrate.
  • the semiconductor layer 40 includes an interface 401 that is in contact with the gate insulating layer 50.
  • the method before the step of depositing the gate insulating layer 50, the method further includes cleaning an interface 401 between the semiconductor layer 40 and the gate insulating layer 50, so that the second light can be avoided.
  • the steps of coating, exposing, and developing the lithography 3 introduce pollution to the interface 401 where the semiconductor layer 40 and the gate insulating layer 50 are connected, thereby improving the performance and reliability of the thin film transistor region 101.
  • the gate insulating layer 50 is coated with the second photoresist 3, and the second mask 4 is used to continuously pattern the gate insulating layer 50 and the semiconductor.
  • Layer 40 so as to avoid introducing contaminants directly by coating the second photoresist 3 on the semiconductor layer 40.
  • the second photoresist 3 is disposed directly above the light-shielding metal layer 21 of the thin film transistor region 101, and a region of the second photoresist 3 is included in a region of the light-shielding metal layer 21, so that it can be avoided.
  • the light projected from the side of the substrate 10 facing away from the semiconductor layer 40 is irradiated to the semiconductor layer 40, thereby improving the performance and reliability of the thin film transistor region 101.
  • the light-shielding metal layer 21 is a reflective structure, that is, the light-shielding metal layer 21 may be coated with a light-reflecting material on a side close to the substrate 10, or the entire light-shielding metal layer 21 is made of a light-reflecting material to avoid light. Projected onto the thin film transistor region 101.
  • the gate insulating layer 50 and the semiconductor layer 40 are etched by using a photolithography and etching process, and the ones covered by the second photoresist 1 remain.
  • the gate insulating layer 50 and the semiconductor layer 40 to form a pattern including the active layer 41.
  • the exposed surface of the gate insulation layer 50 is first coated with the second photoresist 3, and the upper surface of the second photoresist 3 is a flat surface, and then the second mask A plate 4 is disposed on the second photoresist 3.
  • the working light is projected onto the second mask plate 4 to perform processing such as exposure and development on the second photoresist 3, so that the gates exposed on opposite sides of the second photoresist 3 are insulated.
  • the layer 50 and the semiconductor layer 40 (that is, the gate insulating layer 50 and the semiconductor layer 40 not covered by the second photoresist 3) are sequentially etched.
  • the action light may be ultraviolet light.
  • the thickness of the barrier layer 30 in the storage capacitor region 101 is reduced by a patterning process.
  • the blocking layer 30 can be used as the dielectric blocking layer 32 of the storage capacitor region 102.
  • the barrier layer 30 is lithographically and etched by using the second mask 4 using photolithography and etching processes, and the barriers exposed on opposite sides of the second photoresist 3 are exposed.
  • the layer 30 is partially etched, thereby reducing the thickness of the barrier layer 30 on opposite sides of the second photoresist 3, that is, reducing the thickness of the dielectric barrier layer 32 of the storage capacitor region 102, thereby increasing the thickness of the barrier layer 30.
  • the capacitance value of the storage capacitor region 102 is described.
  • the second photoresist 3 is peeled off, and the gate insulating layer 50 of the thin film transistor region 101 is exposed.
  • the barrier layer 30 has an exposed surface 301. It can be understood that the exposed surface 301 of the blocking layer 30 refers to a surface of the blocking layer 30 that is not shielded by the active layer 41.
  • the active layer 41 has two opposite side surfaces 402.
  • the gate insulating layer 50 also has two opposite side surfaces 501. The two side surfaces 402 of the active layer 41 are in contact with and flush with the two side surfaces 501 of the gate insulation layer 50, respectively, and are in contact with the exposed surface 301 of the barrier layer 30, so as to form a continuous surface so that The capacitor insulation layer 52 is deposited.
  • the capacitor insulation layer 52 covers the exposed surface 301 of the barrier layer 30, the side surface 402 of the active layer 41, and the side surface 501 of the gate insulation layer 50, thereby avoiding the thin film transistor.
  • the gate 61 of the region 101 and the semiconductor layer 40 are short-circuited at edges of both ends of the semiconductor layer 40.
  • the capacitor insulation layer 52 also covers the original gate insulation layer 50 and is in contact with the original gate insulation layer 50, thereby forming a continuous insulating dielectric layer. A portion of the capacitor insulation layer 52 covering the original gate insulation layer 50 and the original gate insulation layer 50 together form a new gate insulation layer with a larger thickness.
  • the material included in the capacitor insulating layer 52 is the same as the material included in the gate insulating layer 50.
  • the thickness of the capacitor insulating layer 52 is smaller than the thickness of the new gate insulating layer, thereby increasing the capacitance value of the storage capacitor region 102.
  • the active layer 41 is patterned, if the active layer 41 undercuts due to etching and the undercut is deep enough, The side surface 402 will be retracted inward relatively to the side surface 501 of the gate insulating layer 50. In the subsequent process of forming the gate 61, the gate 61 will not be able to communicate with the side surface 402 of the active layer 41. They are connected to each other, so that the step of forming the capacitor insulating layer 52 described above can be omitted.
  • the gate metal layer 60 is deposited on the gate insulating layer 50 and the capacitor insulating layer 52, and is coated on the gate metal layer 60.
  • the gate metal layer 60 covers the gate insulating layer 50 and the capacitor insulating layer 52.
  • the third photoresist 5 is formed on the gate metal layer 60.
  • the third photoresist 5 leaves two types of patterns after exposure and development.
  • One type of the pattern of the third photoresist 5 is disposed in the thin film transistor region 101 and is located in the thin film transistor region 101.
  • the middle portion of the active layer 41 is so that the two ends of the active layer 41 can be exposed to the same length after the etching process, which is beneficial to the subsequent formation of the source region 4111 and the drain region 4112 of the active layer 411.
  • the pattern of the third type of the third photoresist 5 is disposed in the storage capacitor region 102 and is overlapped with the first pole piece 22 of the storage capacitor region 102 so that the The second pole piece 62 and the first pole piece 22 have a larger projected area, thereby increasing the total area of the pole pieces of the storage capacitor area, and further increasing the capacitance value of the storage capacitor area 102.
  • the gate metal layer 60 is patterned by using the third mask 6 using photolithography and etching processes. Specifically, the gate metal layer 60 exposed on the opposite sides of each of the third photoresist 5 is etched, and the gate metal layer 60 covered by the third photoresist 5 is retained to form The gate 61 of the thin film transistor region 101 and the pattern of the second pole piece 62 of the storage capacitor region 102 are described. It can be understood that, in this embodiment, the gate electrode 61 and the second electrode piece 62 are disposed on the same layer.
  • the thickness of the capacitor insulating layer 52 is smaller than the thickness of the gate insulating layer 50, the distance between the first pole piece 22 and the second pole piece 62 of the storage capacitor region 102 can be further shortened, and the distance between The capacitance value of the storage capacitor region 102 is described.
  • the third photoresist 5 is retained, and the gate insulation layer 50 and the capacitor insulation layer 52 are respectively utilized by the third mask using an etching process. 6 to etch and retain the gate insulating layer 50 and the capacitor insulating layer 52 covered by the third photoresist 5 to form a gate dielectric layer 51 including the thin film transistor region 101 and the storage capacitor region 102 Pattern of the capacitive dielectric layer 53.
  • the third photoresist 5 may be removed first, and then the gate insulating layer 50 is etched by using the gate 61 of the thin film transistor region 101 to obtain the thin film transistor region 101.
  • the gate dielectric layer 51; the capacitor insulation layer 52 is etched by using the second pole piece 62 of the storage capacitor region 102 at the same time by using photolithography and etching processes to obtain the capacitor dielectric layer 53 of the storage capacitor region 102. It can be seen that the gate 61 of the thin film transistor region 101 and the second pole piece 62 of the storage capacitor region 102 can also be used to function as the third mask plate 6.
  • the method before depositing the interlayer insulating layer 70, the method further includes: using plasma to process both exposed ends of the active layer 41 to form a contact doped region 411.
  • the plasma is an Ar plasma or an NH3 plasma containing a large amount of hydrogen.
  • a part of the active layer 41 is converted into a contact doped region 411 by a plasma process, and a portion of the active layer 41 between the contact doped regions 411 forms a channel 412.
  • the channel 412 of the active layer 41 is overlapped with the gate insulating layer 50.
  • the contact-doped region 411 of the active layer 41 has an opposite inner edge 410, and the inner edge 410 is an interface 410 between the contact-doped region 411 and the channel 412.
  • the gate 61 has two opposite side surfaces 611, and the inner edge 410 of the contact doped region 411 is aligned with the side surface 611 of the gate 61.
  • the exposed two ends of the active layer 41 respectively form a source region 4111 (ie, a source conductor) and a drain region 4112 (ie, a drain conductor) of the thin film transistor region 101, thereby reducing Contact resistance between the source region 4111 and the drain region 4112, and since the side surface 611 of the gate 61 is flush with the inner edge 410 of the contact doped region 411, the source region 4111 and the drain are avoided.
  • the overlap of the region 4112 and the gate 61 generates a parasitic capacitance, which improves the performance of the device.
  • the third photoresist 5 is peeled from the gate insulating layer 50 and the capacitor dielectric layer 53.
  • the interlayer insulating layer 70 is deposited on a side of the gate 61 facing away from the gate insulating layer 50, and covers the contact of the barrier layer 30 and the active layer 41.
  • the interlayer insulating layer 70 is patterned by photolithography and etching processes to form small holes 7041 in the lead region 103. As shown in FIG. 21, the photolithography and etching processes are used again, but another mask is used to pattern the interlayer insulating layer 70 to form the source electrode contact hole 701 and the leakage level of the thin film transistor region 101.
  • the source electrode contact hole 701 and the leakage level contact hole 702 of the thin film transistor region 101 are separated from each other, and the source region 4111 and the drain region 4112 of the active layer 41 are respectively exposed to the source electrode contact hole 701 and the source electrode contact hole 701.
  • the capacitor pole piece contact hole 703 is separated from the source electrode contact hole 701 and the leakage level contact hole 702 and exposes the second pole piece 62 of the storage capacitor region 102.
  • the small hole 7041 and the large hole 7042 of the lead region 103 pass through to form a via 704, so that the conductive layer 23 of the lead region 103 is exposed.
  • the depth of the via hole 704 is greater than the depth of the source electrode contact hole 701 and the leakage level contact hole 702 and the depth of the capacitor electrode contact hole 703, the The via hole 704 is firstly subjected to a photolithography and etching process to form the small hole 7041, and then the second hole is subjected to a photolithography and etching process to form the large hole 7042.
  • the large hole 7042 wraps the small hole 7041, so that the large hole 7042 wraps the small hole 7041, so as to ensure the depth and size of the via hole 704.
  • the vias of the lead region 103 are formed into large holes during the first photolithography and etching, and then small holes in the large holes are further formed in the second photolithography and etching process. The final form of large holes and small holes is also formed.
  • the two mask design methods can be selected according to the characteristics of the actual process.
  • the source and leakage level contact holes 701 and 702 and the capacitor pole piece contact hole 703 may be formed simultaneously with the via hole 704 in a second photolithography and etching process.
  • the source electrode contact hole 701 and the leakage level contact hole 702 of the thin film transistor region 101, the capacitor pad contact hole 703 of the storage capacitor region 102, and the via hole 704 of the lead region 103 are filled.
  • the source electrode 81 and the drain electrode 82 are disposed on the interlayer insulating layer 70 and pass through the source electrode contact hole 701 and the leakage level contact hole 702 and the source of the contact doped region 411, respectively.
  • Region 4111 and drain region 4112 are electrically connected.
  • the third pole piece 83 is connected to the drain electrode 82, so that the second pole piece 62 of the storage capacitor region 102 leads to the interlayer insulating layer 70.
  • the electrode lead 84 is connected to the conductive layer 23, so that the conductive layer 23 of the lead region 103 leads to the interlayer insulating layer 70, thereby providing a bias for the first pole piece 22 of the storage capacitor region 102. Voltage.
  • FIG. 23 to FIG. 41 are process flow charts of the method for manufacturing the array substrate 200 according to the second embodiment of the present invention.
  • the manufacturing method of the array substrate 200 shown in the second embodiment is similar to the manufacturing method of the array substrate 100 shown in the first embodiment. Therefore, the process flow, parameters, and material selection of the manufacturing method of the array substrate 200 shown in the second embodiment can be changed.
  • the barrier layer 31 of the array substrate 200 includes a first barrier layer 311 and a second barrier layer 312.
  • the first barrier layer and the second barrier layer are sequentially deposited on the substrate, and the first barrier layer covers the plurality of light shielding structures.
  • Adopting a second mask to etch the partial barrier layer includes: using the second mask to etch the second barrier layer, and retaining the first barrier layer and the second mask layer covered by the second photoresist Second barrier layer.
  • a capacitor dielectric layer and a gate metal layer are sequentially deposited on a side surface of the gate insulating layer, a side surface of the semiconductor layer, and an exposed surface of at least one of the barrier layers, including: The side surface of the semiconductor layer, the side surface of the first barrier layer, and the exposed surface of the second barrier layer sequentially deposit the capacitor dielectric layer and the gate metal layer.
  • a light shielding layer 20 is deposited on the substrate 10 in advance, and the light shielding layer 20 is patterned with a first mask plate 2 to form a plurality of spaced arrays.
  • Light-shielding structure 204 A thin film transistor region 201, a storage capacitor region 202 and a lead region 203 are defined on the substrate 10 according to the light shielding structure 204.
  • the light shielding structure 204 can be used as the light shielding metal layer 21 of the thin film transistor region 201, the first pole piece 22 of the storage capacitor region 202, and the conductive layer 23 of the lead region 203.
  • the first barrier layer 311, the second barrier layer 312, the semiconductor layer 40, and the gate insulating layer 50 are continuously deposited on the plurality of light shielding structures 204. . It can be understood that since the semiconductor layer 40 and the gate insulating layer 50 are continuously deposited, that is, the semiconductor layer 40 is not subjected to photolithography and etching steps before the gate insulating layer 50 is deposited, so Avoiding directly coating the semiconductor layer 40 with photoresist and removing the photoresist from contaminating the channel surface of the subsequent preparation of the active layer, thereby improving the performance and reliability of the thin film transistor region 201.
  • a second photoresist 3 is coated on the gate insulating layer 50.
  • the first blocking layer 311 covers the plurality of light shielding structures 204, and the substrate 10 and the first blocking layer 311, the second blocking layer 312, the semiconductor layer 40, and the gate insulating layer 50 stacked settings.
  • the thickness of the first barrier layer 311 is smaller than the thickness of the second barrier layer 312.
  • the first barrier layer 311 and the second barrier layer 312 may be made of different materials, or may use the same material but different impurity concentrations.
  • the dielectric constant of the first blocking layer 311 is greater than the dielectric constant of the second blocking layer 312.
  • the second photoresist 3 is directly opposite to the light-shielding metal layer 21 of the thin film transistor region 201, and a region of the second photoresist 3 is included in a region of the light-shielding metal layer 21, thereby avoiding
  • the light projected from the side of the substrate 10 facing away from the semiconductor layer 40 is irradiated to the semiconductor layer 40, thereby improving the performance and reliability of the thin film transistor region 201.
  • the light-shielding metal layer 21 is a reflective structure, that is, the light-shielding metal layer 21 may be coated with a light-reflecting material on a side close to the substrate 10, or the entire light-shielding metal layer 21 is made of a light-reflecting material to avoid light. Projected onto the thin film transistor region 201.
  • the semiconductor layer 40 includes an interface 401 that is in contact with the gate insulating layer 50.
  • the method further includes cleaning an interface 401 between the semiconductor layer 40 and the gate insulating layer 50, so as to prevent the second photoresist 3 from being applied.
  • steps such as cloth, exposure, and development, introduce pollution to the interface 401 where the semiconductor layer 40 and the gate insulating layer 50 are in contact, thereby improving the performance and reliability of the thin film transistor region 201.
  • the gate insulating layer 50, the semiconductor layer 40, and the second barrier layer 312 are etched by using a photolithography and etching process, and the first A blocking layer 311 and the gate insulating layer 50, the semiconductor layer 40 and the second blocking layer 312 covered by the second photoresist 3.
  • the exposed surface of the gate insulation layer 50 is first coated with the second photoresist 3, and the upper surface of the second photoresist 3 is a flat surface, and then the second photoresist 3 is flat.
  • a reticle 4 is disposed on the second photoresist 3.
  • the working light is projected onto the second mask plate 4 to perform processing such as exposure and development on the second photoresist 3, so that the gates exposed on opposite sides of the second photoresist 3 are insulated.
  • the layer 50, the semiconductor layer 40, and the second blocking layer 312 (that is, the gate insulating layer 50, the semiconductor layer 40, and the second blocking layer 312 not covered by the second photoresist 3) are sequentially Etching and forming a pattern including the active layer 41.
  • the action light may be ultraviolet light. Because the first barrier layer 311 and the second barrier layer 312 are made of different materials, during the etching, the etching will automatically stop when it reaches the surface of the first barrier layer 311, which can further simplify the manufacturing process.
  • the active layer 41 has two opposite sides 402, the gate insulating layer 50 also has two opposite sides 501, the first blocking layer 311 has an exposed surface 3111, and the second The blocking layer 312 has two opposite sides 3121.
  • the exposed surface 3111 of the first blocking layer 311 refers to a surface that is not shielded by the second blocking layer 312.
  • the side surface 402 of the active layer 41 is in contact with and flush with the side surface 3121 of the second barrier layer 312 and the side surface 501 of the gate insulation layer 50, and the side surface 3121 of the second barrier layer 312 and The exposed surfaces 3111 of the first blocking layer 311 are in contact with each other.
  • the capacitor insulating layer 52 covers the exposed surface 3111 of the first barrier layer 311, the side surface 3121 of the second barrier layer 312, the side surface 402 of the active layer 41, and the gate
  • the side surface 502 of the insulating layer 50 prevents short-circuits at edges of the gate metal layer 60 to the active layer 41 of the thin film transistor region 101 at both ends of the active layer 41.
  • the capacitor insulating layer 52 also covers the original gate insulating layer 50 and is in contact with the original gate insulating layer 50, thereby forming a continuous insulating dielectric layer.
  • the capacitor insulating layer 52 covers a part of the original gate insulating layer 50 and forms a new gate insulating layer with a larger thickness together with the original gate insulating layer 50.
  • the material included in the capacitor insulating layer 52 is the same as the material included in the gate insulating layer 50.
  • the thickness of the capacitor insulating layer 52 is smaller than the thickness of the new gate insulating layer, thereby increasing the capacitance value of the storage capacitor region 102.
  • the side surface 402 of the active layer 41 will be opposite to the gate
  • the side surface 501 of the insulating layer 50 is retracted inwardly to a large extent.
  • the gate electrode 61 cannot be connected to the side surface 402 of the active layer 41, so the capacitor insulation can be omitted this time Step of forming the layer 52.
  • the gate metal layer 60 is deposited on the gate insulating layer 50 and the capacitor insulating layer 52, and the gate metal layer 60 is coated with Mentioned third photoresist 5.
  • the third photoresist 5 leaves multiple types of patterns after exposure and development.
  • One type of the pattern of the third photoresist 5 is disposed in the thin film transistor region 201 and is located in the thin film transistor region 201.
  • the middle portion of the active layer 41 is so that the two ends of the active layer 41 can be exposed to the same length after the etching process, which is beneficial to the subsequent formation of the source region 4111 and the drain region 4112 of the active layer 41.
  • the pattern of the third type of the third photoresist 5 is disposed in the storage capacitor region 202 and is overlapped with the first pole piece 22 of the storage capacitor region 202 so that the The second pole piece 62 and the first pole piece 22 have a larger projected area, thereby increasing the total area of the pole pieces of the storage capacitor area 202 and further increasing the capacitance value of the storage capacitor area 202.
  • the gate metal layer 60 is patterned by using the third mask 6 using a photolithography and etching process. Specifically, the gate metal layer 60 exposed on the opposite sides of each of the third photoresist 5 is etched, and the gate metal layer 60 covered by the third photoresist 5 is retained to form the gate metal layer 60.
  • the third photoresist 5 is retained, and the gate insulating layer 50 and the capacitor insulating layer 52 are etched by the third mask 6 using photolithography and etching processes, respectively.
  • the gate insulating layer 50 and the capacitor insulating layer 52 covered by the third photoresist 5 are retained to form the gate insulating layer 50 of the thin film transistor region 101 and the capacitor dielectric layer 53 of the storage capacitor region 202.
  • the third photoresist 5 may be removed first, and then the gate metal layer 60 of the thin film transistor region 201 is used for etching; at the same time, the capacitor insulating layer 52 is applied by photolithography and etching processes.
  • the second pole piece 62 of the storage capacitor region 202 is etched. It can be seen that the gate 61 of the thin film transistor region 201 and the second pole piece 62 of the storage capacitor region 202 can also be used to function as the third mask plate 6.
  • the method of sequentially depositing and patterning the interlayer insulating layer 70 and the electrode layer 80 on the gate 61 is the same as the steps of the manufacturing method of the array substrate 100 of the first embodiment. For details, refer to the manufacturing of the array substrate 100 of the first embodiment. The process steps of the method are described in detail in this step.
  • the capacitor dielectric layer in the storage capacitor region is thinned, thereby reducing the distance between the first pole piece and the second pole piece, thereby increasing the capacitance value of the storage capacitor.
  • the display device of the present invention uses the above array substrate, thereby improving its performance and reliability. Further, in the method for manufacturing an array substrate of the present invention, a gate insulating layer is first deposited and then a semiconductor layer is patterned, thereby avoiding contamination at the interface between the semiconductor layer and the gate insulating layer, thereby improving the performance and reliability of the array substrate.

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Abstract

本发明提供了一种阵列基板及其制造方法、显示装置。所述阵列基板制造方法包括如下步骤：提供基板，在所述基板上形成薄膜晶体管区和存储电容区；在所述基板上沉积至少一阻挡层，通过一次构图工艺减薄至少一所述阻挡层在所述存储电容区的厚度。本发明阵列基板制造方法，通过减薄至少一所述阻挡层在所述存储电容区的厚度，从而提高了所述存储电容区的电容值。

Description

阵列基板及其制造方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
随着显示技术的发展，消费者对于显示装置的显示方式、显示效果等需求越来越多样化、个性化。阵列基板作为显示面板的核心组件，其质量对最终产品的性能和可靠性起着关键的影响。
由于结构限制，阵列基板的存储电容区的电容值较低，不能满足显示面板高分辨率的要求。
发明内容
鉴于现有技术中存在的上述问题，本发明提供一种阵列基板制造方法、阵列基板及显示装置。
为了实现上述目的，本发明实施方式提供如下技术方案：
第一方面，本发明提供了一种阵列基板制造方法，其包括如下步骤:
提供基板，在所述基板上形成薄膜晶体管区和存储电容区；
在所述基板上沉积至少一阻挡层，通过一次构图工艺减薄至少一所述阻挡层在所述存储电容区的厚度。
第二方面，本发明提供了一种阵列基板，其包括：
基板，包括薄膜晶体管区和存储电容区；
至少一阻挡层，位于所述薄膜晶体管区和所述存储电容区，所述薄膜晶体管区的阻挡层的厚度小于所述存储电容区的阻挡层的厚度。
第三方面，本发明提供了一种显示装置，其包括上述阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的阵列基板的截面示意图。
图2是本发明第二实施例提供的阵列基板的截面示意图。
图3是本发明实施例提供的显示装置的结构示意图。
图4是本发明实施例提供的阵列基板制造方法的流程图。
图5至图22是图4所示的阵列基板的制造方法的各个制造流程的第一实施方式的截面示意图。
图23至图41是图4所示的阵列基板的制造方法的各个制造流程的第二实施方式的截面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，为本发明第一实施例提供的一种阵列基板的截面示意图。所述阵列基板100包括基板10。所述基板10设置薄膜晶体管区101、存储电容区102及引线区103。
所述基板10可以是可弯曲或不可弯曲的基板，且用于支撑整个所述薄膜晶体管区101、所述存储电容区102及所述引线区103。在本实施例中，所述基板10为聚酰亚胺(Polyimide，简称PI)基板。可以理解的，在其他实施例中，所述基板10还可以为聚酰胺(polyamide，PA)基板、聚碳酸酯(polycarbonate，PC)基板、聚苯醚砜(polyethersulfone，PES)基板、聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)基板、聚萘二甲酸乙二醇酯(polyethylene naphthalate，PEN)基板、聚甲基丙烯酸甲酯(polymethylmethacrylate，PMMA)基板、环烯烃共聚物(cycloolefin copolymer，COC)基板中的一种。所述基板10搭载于电子设备的形态中，可为曲率在使用时发生变化的弯曲曲面，也可为曲率不发生变化的固定曲面，另外还可为平面。
所述薄膜晶体管区101包括依次设置在所述基板10上的遮光金属层21、阻挡层30、有源层41、栅极介质层51、栅极61及层间绝缘层70。
在本实施例中，所述遮光金属层21与所述有源层41间隔且相对设置。所述遮光金属层21与所述有源层41叠置设置。所述遮光金属层21可为反光层。所述反光层用于反射从所述基板10一侧照射的光线，以实现阻挡从所述基板10一侧照射的光线，从而避免了光线对薄膜晶体管区101的有源层41的照射。
其中，所述遮光金属层21的材料可以为具有良好反射效果的金属。所述金属例如是，但不局限于铝或银。由于铝在很宽的光谱范围内都具有很高的反射率，可以对剥离时使用的光线具有很好的反射效果，因此所述遮光金属层21的材料优选为铝。此外，铝材料使用广泛且价格合理。可以理解的，在其他实施例中，所述遮光金属层21的材料还可以为有机反光材料。
所述阻挡层30设置在所述遮光金属层21的上方，且包覆所述遮光金属层21。所述阻挡层30的材料为无机绝缘材料。所述无机绝缘材料例如是，但不局限于氮化硅(SiNx)或氧化硅(SiOx)。可以理解的，在其他实施例中，所述阻挡层30还可以是其他水氧阻隔层。
所述有源层41设置在所述阻挡层30的上方。所述有源层41包括设置在其两端部的接触掺杂区411和设置在所述两接触掺杂区之间的沟道412。所述接触掺杂区411包括源区4111和漏区4112。
所述栅极介质层51设置在所述有源层41的上方。所述栅极介质层51与所述有源层41的沟道412叠置设置。所述栅极61设置在所述栅极介质层51的上方，且与所述有源层41的沟道412间隔且相对设置。在本实施例中，所述栅极61与所述有源层41的沟道412叠置设置。
所述层间绝缘层70设置于所述栅极61的上方，且包覆所述栅极61、所述栅极介质层51、所述有源层41及所述阻挡层30。所述层间绝缘层70开设两相对的源极接触孔701和漏极接触孔702，且所述源极接触孔701和所述漏极接触孔702贯穿所述层间绝缘层70，并使所述有源层41的接触掺杂区411暴露。
在本实施例中，所述薄膜晶体管区101还包括源电极81和漏电极82。所述薄膜晶体管区101为顶栅形式，也即所述源电极81和所述漏电级82设置在所述栅极61相对所述有源层41的同侧。所述源电极81 和所述漏电极82均设置在所述层间绝缘层70上，并分别通过所述源极接触孔701和所述漏极接触孔702与所述有源层41的接触掺杂区411电连接。
所述存储电容区102包括在所述基板10依次层叠的第一极片22、介质阻挡层32、电容介质层53及第二极片62。所述电容介质层53设置在所述第一极片22和所述第二极片62之间，且与所述薄膜晶体管区101的栅极介质层51间隔设置。所述电容介质层53的厚度小于所述栅极介质层51的厚度，从而减小所述第一极片22与所述第二极片62之间的距离，进而提高所述存储电容区102的电容值。
其中，所述存储电容区102的第一极片22与所述薄膜晶体管区101的遮光金属层21同层设置，所述第一极片22与所述第二极片62之间的间距小于所述遮光金属层21与所述栅极61之间的间距。所述存储电容区102的介质阻挡层32与所述薄膜晶体管区101的阻挡层30相接，且所述介质阻挡层32与所述阻挡层30同层设置。在本实施例中，所述介质阻挡层32包含的材料与所述阻挡层30的材料一样。所述介质阻挡层32可为所述薄膜晶体管区101的阻挡层30。所述介质阻挡层32的厚度小于所述阻挡层30的厚度，从而进一步减小所述第一极片22与所述第二极片62之间的距离，进而提高所述存储电容区102的电容值。
可以理解的，所述第一极片22与所述第二极片62之间的距离越小，所述存储电容区102的电容值越大。其中，所述“同层设置”是指两个结构均由同一材料层经过同一步沉积和同一步构图工艺形成，因此二者在层叠关系上处于同一个层级。
在本实施例中，所述存储电容区102还进一步包括第三极片83，所述第三极片83与所述薄膜晶体管区101的漏电极82相连接，从而使其成为电路的一部分。在本实施例中所述第三极片83可为所述薄膜晶体管区的漏极82的一部分。所述第二极片62与所述第三极片83相连接而共同构成所述存储电容区102的一个电极。可以理解的，在其他实施例中，所述第三极片83也可不与所述薄膜晶体管区101的漏电极82连接，也即用户可根据实际的电路线路执行电极间的连接设计。
所述第二极片62与所述第三极片83之间还夹设所述薄膜晶体管区101的层间绝缘层70，并在所述层间绝缘层70开设贯穿所述层间绝缘层70的电容极片接触孔703。所述第三极片83通过所述电容极片接触孔703与所述第二极片62电连接。
可以理解的，当所述栅极61沿着垂直于横截面的方向延伸到所述有源层41以外后，也可以通过类似所述存储电容区102中的接触孔703的方式又和所述第三极片83同层设置的金属线引出。从而所述第三极片83提供了分别将所述薄膜晶体管区101的栅极61、源区4111和漏区4112，以及所述存储电容区102的第二极片62引出的布线自由度。
所述引线区103包括设置在所述基板10上的导电层23及电极引线84。所述引线区103的导电层23及所述电极引线84之间夹设所述存储电容区102的介质阻挡层32和层间绝缘层70，并开设贯穿所述介质阻挡层32和所述层间绝缘层70的过孔704。所述电极引线84通过所述过孔704将所述导电层23引出，也即所述导电层23与所述电极引线84电连接，从而可为所述存储电容区102的第一极片22提供偏置电压。
请参阅图2，为本发明第二实施例提供了一种阵列基板的截面示意图。第二实施例的阵列基板200与第一实施例所述阵列基板100的结构相似，因此所述阵列基板200包含的各元件尺寸、元件名称、各元件位置关系等均可参考第一实施例所述阵列基板100，在此不再赘述。不同的是，在第二实施例中，所述阵 列基板200的阻挡层31包括第一阻挡层311和第二阻挡层312，所述第一阻挡层311位于薄膜晶体管区201、存储电容区202及引线区203，所述第二阻挡层312位于所述薄膜晶体管区201。
具体的，在本实施例中，所述第一阻挡层311与所述第二阻挡层312可采用不同的材料制成，或者采用相同的材料但不同的参杂浓度。所述第一阻挡层311的介电常数大于所述第二阻挡层312的介电常数。所述第二阻挡层312设置在第一阻挡层311和所述有源层41之间。所述第一阻挡层311与所述介质阻挡层32相连接且同层设置，也即所述薄膜晶体管区201的第一阻挡层311可作为所述存储电容区202的介质阻挡层32。所述第二阻挡层312与所述有源层41叠置设置。所述第一阻挡层311的厚度小于所述第二阻挡层312的厚度，从而可以进一步减小所述存储电容区202的第一极片22和第二极片62之间的距离，进而提高所述存储电容区202的电容值。
请参看图3，为本发明实施例提供的一种显示装置。所述显示装置1000包括第一实施例和第二实施例所述的阵列基板100，200，所述阵列基板100，200可包括用于实现不同功能的电路(如栅极驱动电路和像素电路等)，以及薄膜晶体管及存储电容等。
所述显示装置1000可以是柔性显示装置或是非柔性显示装置。所述柔性显示装置1000例如是，但不局限于液晶显示器(Liquid Crystal Display,LCD)、量子点显示器(Quantum Dot Light Emitting Diodes,QLED)、手机、平板电脑、导航仪等具有显示功能的产品或部件。
实施例一
请参看图4，为本发明第一实施例的阵列基板100制造方法的实现流程。所述阵列基板100制造方法包括如下步骤：
步骤403，提供基板，在所述基板上形成薄膜晶体管区和存储电容区。
步骤405，在所述基板上依次沉积至少一阻挡层，通过一次构图工艺减薄至少一所述阻挡层在所述存储电容区的厚度。
在通过一次构图工艺减薄至少一所述阻挡层在所述存储电容区的厚度之前，还包括：
在所述基板上连续沉积半导体层和栅极绝缘层；
依次图案化所述栅极绝缘层和所述半导体层，并且通过一次构图工艺形成包括有源层的图案，通过二次构图工艺形成包括栅极介质层的图案。
具体的，请一并参阅图5至图6，在本实施例中，在所述基板10上形成薄膜晶体管区101和存储电容区102的具体步骤为：
在所述基板10上沉积光屏蔽层20；
在所述光屏蔽层20上涂覆第一光刻胶1，并采用第一掩膜版2图案化所述光屏蔽层20，以形成间隔排列的若干遮光结构204。根据所述遮光结构204在所述基板10上界定形成所述薄膜晶体管区101、所述存储电容区102及引线区103，也即所述遮光结构204可以作为所述薄膜晶体管区101的遮光金属层21、所述存储电容区102的第一极片22及所述引线区103的导电层23。
在本实施例中，在所述基板10上沉积光屏蔽层20之后，还包括：
在所述遮光结构上连续沉积阻挡层、半导体层和栅极绝缘层；
在所述栅极绝缘层上涂覆第二光刻胶，并利用同一第二掩膜版图案化所述栅极绝缘层、所述半导体层和所述阻挡层，并保留被所述第二光刻胶覆盖的栅极绝缘层和半导体层，以形成包括有源层的图案，且减薄至少一所述阻挡层在所述存储电容区的厚度；
在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面沉积栅金属层；
在所述栅金属层上涂覆第三光刻胶，并利用同一第三掩膜版图案化所述栅金属层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅极介质层及存储电容区的第二极片的图案；
在所述栅栅极上依次沉积并图案化层间绝缘层及电极层。
进一步的，在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面沉积栅金属层；在所述栅金属层上涂覆第三光刻胶，并利用同一第三掩膜版图案化所述栅金属层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅极介质层及存储电容区的第二极片的图案，具体包括如下步骤：在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面依次沉积电容绝缘层和所述栅金属层；在所述栅金属层上涂覆第三光刻胶，并利用同一第三掩膜版依次图案化所述栅金属层、所述电容绝缘层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅介质层、及所述存储电容区的第二极片和电容介质层的图案。
具体的，如图7和图8所示，在本发明实施例中，在所述若干遮光结构204上连续沉积所述阻挡层30、所述半导体层40(也即金属氧化物层)和所述栅极绝缘层50。可以理解的，由于所述半导体层40和所述栅极绝缘层50是连续沉积，也即在沉积所述栅极绝缘层50之前所述半导体层40没有进行光刻和刻蚀步骤，因此可避免直接在所述半导体层40涂覆光刻胶及去除光刻胶造成对后续制备有源层的沟道表面的污染，进而提高了所述薄膜晶体管区101的性能和可靠性。所述阻挡层30及所述半导体层40均与所述基板10叠置设置，且所述阻挡层30包覆所述若干遮光结构204。其中，所述基板10的材料可以为玻璃或塑料，所述基板10还可以为柔性衬底。
如图8所示，所述半导体层40包括与所述栅极绝缘层50相接的界面401。作为一可选实施例，在沉积所述栅极绝缘层50的步骤之前，还包括清洁所述半导体层40与所述栅极绝缘层50相接的界面401，从而可避免所述第二光刻胶3涂布、曝光和显影等这些步骤对所述半导体层40和所述栅极绝缘层50相接的界面401引入污染，进而提高所述薄膜晶体管区101的性能和可靠性。
如图9所示，在所述栅极绝缘层50上涂覆所述第二光刻胶3，并采用所述第二掩膜版4连续图案化所述栅极绝缘层50和所述半导体层40，从而可避免直接在所述半导体层40上涂覆所述第二光刻胶3而引入污染物。所述第二光刻胶3设置在所述薄膜晶体管区101的遮光金属层21的正上方，所述第二光刻胶3的区域包含在所述遮光金属层21的区域内，从而可避免所述基板10背离所述半导体层40的一侧投射的光线照射至所述半导体层40，进而提高所述薄膜晶体管区101的性能和可靠性。所述遮光金属层21为反光结构，也即所述遮光金属层21可以在靠近所述基板10的一侧涂覆反光材料，或整个所述遮光金属层21由反光材料制成，以避免光线投射至所述薄膜晶体管区101。
如图10和图11所示，在本实施例中，采用光刻及蚀刻工艺进行蚀刻所述栅极绝缘层50和所述半导体层40，并保留被所述第二光刻胶覆盖1的栅极绝缘层50和半导体层40，以形成包括有源层41的图案。具 体的，先将所述栅极绝缘层50的裸露面涂覆所述第二光刻胶3，所述第二光刻胶3的上表面为平坦的表面，再将所述第二掩膜版4设置在所述第二光刻胶3上。随后，由作用光投射于所述第二掩膜版4，对所述第二光刻胶3进行曝光、显影等处理，使得暴露于所述第二光刻胶3相对两侧的栅极绝缘层50和所述半导体层40(即未被所述第二光刻胶3覆盖的栅极绝缘层50和半导体层40)依次被蚀刻。其中，所述作用光可为紫外光。
如图12所示，在本实施例中，通过一次构图工艺减薄所述阻挡层30在所述存储电容区101的厚度。可以理解的，在本实施例中，所述阻挡层30可作为所述存储电容区102的介质阻挡层32。具体的，采用光刻及蚀刻工艺将所述阻挡层30采用所述第二掩膜版4进行光刻和刻蚀，并将暴露在所述第二光刻胶3相对两侧的所述阻挡层30部分蚀刻，从而减薄了所述阻挡层30在所述第二光刻胶3相对两侧的厚度，也即减薄所述存储电容区102的介质阻挡层32的厚度，进而提升所述存储电容区102的电容值。随后，剥离去除所述第二光刻胶3，并露出所述薄膜晶体管区101的栅极绝缘层50。
如图12和图13所示，所述阻挡层30具有裸露面301。可以理解的，所述阻挡层30的裸露面301是指所述阻挡层30未被所述有源层41遮蔽的表面。所述有源层41具有相对的两侧面402。所述栅极绝缘层50也具有相对的两侧面501。所述有源层41的两侧面402分别与所述栅极绝缘层50的两侧面501相接且平齐，并且与所述阻挡层30的裸露面301相接，从而形成连续的表面，以便所述电容绝缘层52的沉积。在本实施例中，所述电容绝缘层52包覆所述阻挡层30裸露面301、所述有源层41的侧面402及所述栅极绝缘层50的侧面501，从而避免所述薄膜晶体管区101的栅极61与所述半导体层40在所述半导体层40两端部的边缘发生短路。具体的，在本实施例中，所述电容绝缘层52还覆盖原栅极绝缘层50并与原栅极绝缘层50相接，从而形成连续的绝缘介质层。所述电容绝缘层52覆盖原栅极绝缘层50的部分与原栅极绝缘层50共同形成厚度更大的新栅极绝缘层。其中，所述电容绝缘层52包含的材料与所述栅极绝缘层50包含的材料一样。所述电容绝缘层52的厚度小于新栅极绝缘层的厚度，从而提高了所述存储电容区102的电容值。可以理解地，当在图案化所述有源层41的过程中，如果所述有源层41由于蚀刻出现了切底(under-cut)且切底足够深时，所述有源层41的侧面402会相对所述栅极绝缘层50的侧面501向内缩进较大幅度，在后续的形成栅极61的制程中，所述栅极61将无法与所述有源层41的侧面402相接，因而可省略本次所述电容绝缘层52的形成步骤。
如图14和图15所示，在本实施例中，在所述栅极绝缘层50和所述电容绝缘层52上沉积所述栅金属层60，并在所述栅金属层60上涂覆所述第三光刻胶层5。如图14所示，所述栅金属层60包覆所述栅极绝缘层50及所述电容绝缘层52。
如图15所示，所述第三光刻胶5形成在所述栅金属层60上。在本实施例中，所述第三光刻胶5在曝光和显影后留下两类图案，其中一类所述第三光刻胶5的图案设置在所述薄膜晶体管区101，且位于所述有源层41的中部，以便所述有源层41的两端部进行蚀刻工艺后可显露相同长度，以利于后续形成有源层411的源区4111和漏区4112。其中另一类所述第三光刻胶5的图案设置在所述存储电容区102，且与所述存储电容区102的第一极片22叠置设置，以使所述存储电容区102的第二极片62与所述第一极片22具有更大的投影面积，从而增大存储电容区的极片总面积，进而提高所述存储电容区102的电容值。
如图16所示，在本实施例中，采用光刻及蚀刻工艺将所述栅金属层60采用所述第三掩膜版6进行图案化。具体的，将暴露在每一所述第三光刻胶5相对两侧的所述栅金属层60蚀刻，并保留被所述第三光刻胶5覆盖的栅金属层60，以形成包括所述薄膜晶体管区101的栅极61和所述存储电容区102的第二极片62的图案。可以理解的，在本实施例中，所述栅极61与所述第二极片62同层设置。由于所述电容绝缘层52的厚度小于所述栅极绝缘层50的厚度，从而可进一步缩短所述存储电容区102的第一极片22和第二极片62之间的间距，进而提高所述存储电容区102的电容值。
如图17所示，在本实施例中，保留所述第三光刻胶5，并采用蚀刻工艺分别将所述栅极绝缘层50和所述电容绝缘层52利用所述第三掩膜版6进行蚀刻，并保留被所述第三光刻胶5覆盖的栅极绝缘层50和电容绝缘层52，以形成包括所述薄膜晶体管区101的栅极介质层51和所述存储电容区102的电容介质层53的图案。在其他实施例中，可以先去除所述第三光刻胶5，再利用所述薄膜晶体管区101的栅极61将所述栅极绝缘层50进行蚀刻，以得到所述薄膜晶体管区101的栅极介质层51；同时采用光刻及蚀刻工艺将所述电容绝缘层52利用所述存储电容区102的第二极片62进行蚀刻，以得到存储电容区102的电容介质层53。可见，所述薄膜晶体管区101的栅极61和所述存储电容区102的第二极片62也可用于充当所述第三掩膜版6的作用。
如图18所示，在本实施例中，在沉积所述层间绝缘层70之前，还包括：采用等离子体处理所述有源层41暴露的两端部，以形成接触掺杂区411。其中，所述等离子体为Ar等离子体或者含氢较多的NH3等离子体。在本实施例中，通过等离子体过程将部分有源层41转化为接触掺杂区411，并且所述有源层41在所述接触掺杂区411之间的部分形成沟道412。所述有源层41的沟道412与所述栅极绝缘层50叠置设置。所述有源层41的接触掺杂区411具有相对的内边缘410，所述内边缘410为所述接触掺杂区411与所述沟道412相接的界面410。所述栅极61具有相对的两侧面611，所述接触掺杂区411的内边缘410与所述栅极61的侧面611相对准。具体的，所述有源层41暴露的两端部分别形成所述薄膜晶体管区101的源区4111(也即源极导体)和漏区4112(也即漏极导体)，从而减小了所述源区4111和所述漏区4112的接触电阻，并且由于所述栅极61的侧面611与所述接触掺杂区411的内边缘410平齐，从而避免所述源区4111和所述漏区4112与所述栅极61的叠置而产生寄生电容，提高了器件的性能。随后，从所述栅极绝缘层50及所述电容介质层53上剥离所述第三光刻胶5。
如图19所示，所述层间绝缘层70沉积于所述栅极61的背离所述栅极绝缘层50的一侧，且包覆所述阻挡层30、所述有源层41的接触掺杂区411、所述栅极绝缘层50及所述栅极61。
如图20所示，通过光刻及蚀刻工艺来图案化所述层间绝缘层70，以形成所述引线区103的小孔7041。如图21所示，再次通过光刻及蚀刻工艺，但使用另一张掩膜版来图案化所述层间绝缘层70，以形成所述薄膜晶体管区101的源电极接触孔701和漏电级接触孔702、所述存储电容区102的电容极片接触孔703及所述引线区103的大孔7042。所述薄膜晶体管区101的源电极接触孔701和漏电级接触孔702隔离设置，并且使得所述有源层41的源区4111和漏区4112分别暴露于所述源电极接触孔701和所述漏电级接触孔702。所述电容极片接触孔703与所述源电极接触孔701和所述漏电级接触孔702隔开设置，且使所述存储电容区102的第二极片62暴露。所述引线区103的小孔7041和大孔7042相贯通而形成过孔704，以使所 述引线区103的导电层23暴露。
可以理解的，由于所述过孔704的深度较所述源电极接触孔701和所述漏电级接触孔702的深度及所述电容极片接触孔703的深度大，因此所述引线区103的过孔704先第一次采用光刻和蚀刻工艺，以形成所述小孔7041，再第二次采用光刻和蚀刻工艺，以形成所述大孔7042。所述大孔7042包所述小孔7041，以使所述大孔7042包所述小孔7041错位，以确保所述过孔704的深度和大小。在另一种实施方式中，所述引线区103的过孔在第一次光刻和刻蚀时形成大孔，再在第二次光刻和刻蚀工艺中进一步形成大孔内的小孔，同样形成大孔包小孔的最终形式。两种掩膜版的设计方式可以根据实际工艺的特点进行选用。所述源、漏电级接触孔701、702、所述电容极片接触孔703可在第二次光刻和蚀刻工艺与所述过孔704同时形成。
如图22所示，在所述薄膜晶体管区101的源电极接触孔701和漏电级接触孔702、所述存储电容区102的电容极片接触孔703及所述引线区103的过孔704填充导电材料，以形成电极层80，并图案化所述电极层80以形成所述薄膜晶体管区101的源电极81和漏电级82，所述存储电容区102的第三极片83及所述引线区103的电极引线84。所述源电极81和所述漏电极82设置在所述层间绝缘层70上，并分别通过所述源电极接触孔701及所述漏电级接触孔702与所述接触掺杂区411的源区4111和漏区4112电连接。所述第三极片83与所述漏电极82连接，从而实现所述存储电容区102的第二极片62引出所述层间绝缘层70。所述电极引线84与所述导电层23连接，从而实现所述引线区103的导电层23引出所述层间绝缘层70，进而为所述存储电容区102的第一极片22提供偏置电压。
实施例二
请一并参看图23至图41，为本发明第二实施例的阵列基板200制造方法的工艺流程图。第二实施例所示的阵列基板200制造方法与第一实施例所示的阵列基板100制造方法相似，因此第二实施例所示的阵列基板200制造方法的工艺流程及参数、材料选择等可参考第一实施例所示的阵列基板100制造方法，在此不再赘述。不同的是，所述阵列基板200的阻挡层31包括第一阻挡层311和第二阻挡层312。
具体的，在本实施例中，所述第一阻挡层和所述第二阻挡层依次沉积在所述基板，且所述第一阻挡层包覆所述若干遮光结构。采用第二掩膜版蚀刻所述部分阻挡层，包括：利用所述第二掩膜版蚀刻所述第二阻挡层，并保留所述第一阻挡层及被所述第二光刻胶覆盖的第二阻挡层。
在所述栅极绝缘层的侧面、所述半导体层的侧面及至少一所述阻挡层的裸露面依次沉积电容介质层和栅金属层，包括：在所述栅极绝缘层的侧面、所述半导体层的侧面、所述第一阻挡层的侧面及所述第二阻挡层的裸露面依次沉积所述电容介质层和所述栅金属层。
如图23至图24所示，在本实施例中，在所述基板10上预先沉积光屏蔽层20，并用第一掩膜版2图案化所述光屏蔽层20，以形成间隔排列的若干遮光结构204。根据所述遮光结构204在所述基板10上界定形成薄膜晶体管区201、存储电容区202及引线区203。具体的，所述遮光结构204可以作为所述薄膜晶体管区201的遮光金属层21、所述存储电容区202的第一极片22及所述引线区203的导电层23。
在本实施例中，如图25至图28所示，在所述若干遮光结构204上连续沉积所述第一阻挡层311、所述第二阻挡层312、半导体层40和栅极绝缘层50。可以理解的，由于所述半导体层40和所述栅极绝缘层 50是连续沉积，也即在沉积所述栅极绝缘层50之前所述半导体层40没有进行光刻和刻蚀步骤，因此可避免直接在所述半导体层40涂覆光刻胶及去除光刻胶造成对后续制备有源层的沟道表面的污染，进而提高了所述薄膜晶体管区201的性能和可靠性。
具体的，在所述栅极绝缘层50上涂覆第二光刻胶3。所述第一阻挡层311包覆所述若干遮光结构204，且所述基板10与所述第一阻挡层311、所述第二阻挡层312、所述半导体层40及所述栅极绝缘层50叠置设置。所述第一阻挡层311的厚度小于所述第二阻挡层312的厚度。所述第一阻挡层311与所述第二阻挡层312可采用不同的材料制成，或者采用相同的材料但不同的参杂浓度。所述第一阻挡层311的介电常数大于所述第二阻挡层312的介电常数。
所述第二光刻胶3与所述薄膜晶体管区201的遮光金属层21正相对，且所述第二光刻胶3的区域包含于所述遮光金属层21的区域内，从而可避免所述基板10背离所述半导体层40的一侧投射的光线照射至所述半导体层40，进而提高所述薄膜晶体管区201的性能和可靠性。所述遮光金属层21为反光结构，也即所述遮光金属层21可以在靠近所述基板10的一侧涂覆反光材料，或整个所述遮光金属层21由反光材料制成，以避免光线投射至所述薄膜晶体管区201。
如图27所示，所述半导体层40包括与所述栅极绝缘层50相接的界面401。优选的，在沉积所述栅极绝缘层50的步骤之前，还包括清洁所述半导体层40与所述栅极绝缘层50相接的界面401，从而可避免所述第二光刻胶3涂布、曝光和显影等这些步骤对所述半导体层40和所述栅极绝缘层50相接的界面401引入污染，进而提高所述薄膜晶体管区201的性能和可靠性。
如图29至图31所示，在本实施例中，采用光刻及蚀刻工艺进行蚀刻所述栅极绝缘层50、所述半导体层40及所述第二阻挡层312，并保留所述第一阻挡层311及被所述第二光刻胶3覆盖1的栅极绝缘层50、半导体层40及所述第二阻挡层312。具体的，先将所述栅极绝缘层50的裸露面涂覆所述第二光刻胶3，并使所述第二光刻胶3的上表面为平坦的表面，再将所述第二掩膜版4设置在所述第二光刻胶3上。随后，由作用光投射于所述第二掩膜版4，对所述第二光刻胶3进行曝光、显影等处理，使得暴露于所述第二光刻胶3相对两侧的栅极绝缘层50、所述半导体层40及所述第二阻挡层312(即未被所述第二光刻胶3覆盖的栅极绝缘层50、半导体层40及所述第二阻挡层312)依次被蚀刻，并形成包括有源层41的图案。其中，所述作用光可为紫外光。由于第一阻挡层311与第二阻挡层312为不同材料制成，因而在蚀刻时，蚀刻到达第一阻挡层311的表面即会自动停止，可进一步简化制程。
如图32所示，所述有源层41具有相对的两侧面402，所述栅极绝缘层50也具有相对的两侧面501，所述第一阻挡层311具有裸露面3111，所述第二阻挡层312具有相对的两侧面3121。可以理解的，所述第一阻挡层311的裸露面3111是指未被所述第二阻挡层312所遮蔽的表面。所述有源层41的侧面402分别与所述第二阻挡层312的侧面3121及所述栅极绝缘层50的侧面501相接且平齐，并且所述第二阻挡层312的侧面3121与所述第一阻挡层311的裸露面3111相接。
在本实施例中，所述电容绝缘层52包覆所述第一阻挡层311裸露面3111、所述第二阻挡层312的侧面3121、所述有源层41的侧面402及所述栅极绝缘层50的侧面502，从而避免所述薄膜晶体管区101的所述栅金属层60至所述有源层41在所述有源层41两端部的边缘发生短路。此外，所述电容绝缘层52还 覆盖原栅极绝缘层50并与原栅极绝缘层50相接，从而形成连续的绝缘介质层。电容绝缘层52覆盖原栅极绝缘层50的部分，并且与原栅极绝缘层50共同形成厚度更大的新栅极绝缘层。其中，所述电容绝缘层52包含的材料与所述栅极绝缘层50包含的材料一样。所述电容绝缘层52的厚度小于所述新栅极绝缘层的厚度，从而提高了所述存储电容区102的电容值。可以理解地，当在图案化有源层41的过程中，如果有源层41由于蚀刻出现了切底(under-cut)且切底足够深时，有源层41的侧面402会相对栅极绝缘层50的侧面501向内缩进较大幅度，在后续的形成栅极61的制程中，所述栅极61将无法与有源层41的侧面402相接，因而可省略本次电容绝缘层52的形成步骤。
如图33和图34所示，在本实施例中，在所述栅极绝缘层50和所述电容绝缘层52沉积所述栅金属层60，并在所述栅金属层60上涂覆所述第三光刻胶5。在本实施例中，所述第三光刻胶5在曝光和显影后留下多类图案，其中一类所述第三光刻胶5的图案设置在所述薄膜晶体管区201，且位于所述有源层41的中部，以便所述有源层41的两端部进行蚀刻工艺后可显露相同长度，以利于后续形成有源层41的源区4111和漏区4112。其中另一类所述第三光刻胶5的图案设置在所述存储电容区202，且与所述存储电容区202的第一极片22叠置设置，以使所述存储电容区202的第二极片62与所述第一极片22具有更大的投影面积，从而增大存储电容区202的极片总面积，进而提高所述存储电容区202的电容值。
如图35至图36所示，在本实施例中，采用光刻及蚀刻工艺将所述栅金属层60利用所述第三掩膜版6进行图案化。具体的，将暴露在每一所述第三光刻胶5相对两侧的所述栅金属层60蚀刻，并保留被所述第三光刻胶5覆盖的栅金属层60，以形成所述薄膜晶体管区201的栅极61和所述存储电容区202的第二极片62。由于所述电容绝缘层52的厚度小于所述栅极绝缘层50的厚度，从而可进一步缩短所述存储电容区202的第一极片22和第二极片62之间的间距，进而提高所述存储电容区202的电容值。
在一实施例中，保留所述第三光刻胶5，采用光刻和蚀刻工艺分别将所述栅极绝缘层50和所述电容绝缘层52利用所述第三掩膜版6进行蚀刻，并保留被所述第三光刻胶5覆盖的栅极绝缘层50和电容绝缘层52，以形成所述薄膜晶体管区101的栅极绝缘层50和所述存储电容区202的电容介质层53。在另一实施例中，可先去除所述第三光刻胶5，再利用所述薄膜晶体管区201的栅金属层60进行蚀刻；同时采用光刻及蚀刻工艺将所述电容绝缘层52采用所述存储电容区202的第二极片62进行蚀刻。可见，所述薄膜晶体管区201的栅极61和所述存储电容区202的第二极片62也可用于充当所述第三掩膜版6的作用。
在所述栅极61上依次沉积并图案化层间绝缘层70及电极层80的方法与第一实施例的阵列基板100制造方法的步骤相同，具体可参考第一实施例的阵列基板100制造方法的工艺流程步骤，在此步骤赘述。
本发明的阵列基板，其存储电容区的电容介质层减薄，从而缩短了第一极片与第二极片之间的距离，进而提高了存储电容的电容值。本发明的显示装置应用上述阵列基板，从而提高其性能及可靠性。进一步的，本发明的阵列基板制造方法，通过先沉积栅极绝缘层再图案化半导体层，从而避免半导体层与栅极绝缘层的相接界面引入污染，进而提高阵列基板的性能和可靠性。
以上所述的实施方式，并不构成对该技术方案保护范围的限制。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (20)

  1. 一种阵列基板制造方法，其特征在于，包括如下步骤:
    提供基板，在所述基板上形成薄膜晶体管区和存储电容区；
    在所述基板上沉积至少一阻挡层，通过一次构图工艺减薄至少一所述阻挡层在所述存储电容区的厚度。
  2. 如权利要求1所述的阵列基板制造方法，其特征在于，在所述基板上形成薄膜晶体管区和存储电容区具体为：
    在所述基板上沉积光屏蔽层；
    在所述光屏蔽层上涂覆第一光刻胶，并采用第一掩膜版图案化所述光屏蔽层，以形成间隔排列的若干遮光结构；
    根据所述遮光结构在所述基板上界定形成所述薄膜晶体管区、所述电容存储区及引线区，且其中一个所述遮光结构作为所述电容存储区的第一极片。
  3. 如权利要求2所述的阵列基板制造方法，其特征在于，在所述基板上沉积光屏蔽层之后还包括：
    在所述遮光结构上连续沉积至少一所述阻挡层、半导体层和栅极绝缘层；
    在所述栅极绝缘层上涂覆第二光刻胶，并利用同一第二掩膜版连续图案化所述栅极绝缘层、所述半导体层和至少一所述阻挡层，并保留被所述第二光刻胶覆盖的栅极绝缘层和半导体层，以形成包括有源层的图案，且减薄至少一所述阻挡层在所述存储电容区的厚度；
    在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面沉积栅金属层；
    在所述栅金属层上涂覆第三光刻胶，并利用同一第三掩膜版依次图案化所述栅金属层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅极介质层及存储电容区的第二极片的图案；
    在所述栅极上依次沉积并图案化层间绝缘层及电极层。
  4. 如权利要求3所述的阵列基板制造方法，其特征在于，在沉积所述栅极绝缘层之前，还包括可选步骤：清洁所述半导体层与所述栅极绝缘层相接的界面。
  5. 如权利要求3所述的阵列基板制造方法，其特征在于，在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面沉积栅金属层；在所述栅金属层上涂覆第三光刻胶，并利用同一第三掩膜版依次图案化所述栅金属层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅极介质层及存储电容区的第二极片的图案，具体包括：在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面连续沉积电容绝缘层和所述栅金属层；在所述栅金属层上涂覆所述第三光刻胶，并利用同一第三掩膜版依次图案化所述栅金属层、所述电容绝缘层及所述栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅介质层、及所述存储电容区的第二极片和电容介质层的图案。
  6. 如权利要求3或5任意一项所述的阵列基板制造方法，其特征在于，至少一所述阻挡层包括第一阻挡层和第二阻挡层，所述第一阻挡层和所述第二阻挡层依次沉积在所述基板上。
  7. 如权利要求6所述的阵列基板制造方法，其特征在于，所述第一阻挡层的介电常数大于所述第二阻挡层的介电常数。
  8. 如权利要求6所述的阵列基板制造方法，其特征在于，通过一次构图工艺减薄至少一所述阻挡层在 所述存储电容区的厚度，包括：
    利用所述第二掩膜版蚀刻所述第二阻挡层，并保留所述第一阻挡层及被所述第二光刻胶覆盖的第二阻挡层。
  9. 如权利要求6所述的阵列基板制造方法，其特征在于，在所述栅极绝缘层的侧面、所述有源层的侧面及至少一所述阻挡层的裸露面沉积电容绝缘层，包括：
    在所述栅极绝缘层的侧面、所述有源层的侧面、所述第一阻挡层的侧面及所述第二阻挡层的裸露面沉积所述电容绝缘层。
  10. 如权利要求5所述的阵列基板制造方法，其特征在于，利用同一所述第三掩膜版依次图案化所述栅金属层及所述栅极绝缘层具体包括：
    利用所述第三掩膜版依次蚀刻所述栅金属层和所述栅极绝缘层，并保留被所述第三光刻胶覆盖的栅金属层和栅极绝缘层，以形成包括所述薄膜晶体管区的栅极和栅极介质层及存储电容区的第二极片的图案，且所述有源层的两端部暴露；
    采用等离子体处理所述有源层的两端部，以形成两接触掺杂区。
  11. 如权利要求10所述的阵列基板制造方法，其特征在于，所述栅极的两侧面分别与所述有源层的两接触掺杂区的内边缘对准。
  12. 如权利要求3所述的阵列基板制造方法，其特征在于，所述第二光刻胶设置在所述薄膜晶体管区的遮光结构的正上方，且所述第二光刻胶的区域包含在所述遮光结构的区域内。
  13. 如权利要求3所述的阵列基板制造方法，其特征在于，所述第三光刻胶具有多类图案，其中一类所述第三光刻胶的图案设置在所述薄膜晶体管区，且位于所述有源层的中部，其中另一类所述第三光刻胶的图案设置在所述存储电容区，且与所述电容存储区的第一极片叠置设置。
  14. 一种阵列基板，其特征在于，所述阵列基板包括：
    基板，包括薄膜晶体管区和存储电容区；
    至少一阻挡层，位于所述薄膜晶体管区和所述存储电容区，且所述薄膜晶体管区的阻挡层的厚度小于所述存储电容区的阻挡层的厚度。
  15. 如权利要求14所述的阵列基板，其特征在于，所述阵列基板还包括至少一所述阻挡层包括第一阻挡层和第二阻挡层，所述第一阻挡层位于所述薄膜晶体管区和所述存储电容区，所述第二阻挡层位于所述薄膜晶体管区，且所述第一阻挡层和所述第二阻挡层依次层叠设置在所述基板上。
  16. 如权利要求14所述的阵列基板，其特征在于，所述阵列基板还包括：
    栅极介质层，位于所述薄膜晶体管区；
    电容介质层，位于所述存储电容区，所述电容介质层的厚度小于所述栅极介质层的厚度。
  17. 如权利要求14所述的阵列基板，其特征在于，所述阵列基板还包括第一极片和第二极片，所述第一极片和所述第二极片均位于所述存储电容区，且所述第一极片与所述第二极片相对且间隔设置。
  18. 如权利要求17所述的阵列基板，其特征在于，所述阵列基板还包括遮光金属层和栅极，所述遮光金属层和所述栅极均位于所述薄膜晶体管区，所述遮光金属层与所述第一极片同层设置，且与所述栅极相 对且间隔设置。
  19. 如权利要求18所述的阵列基板，其特征在于，所述遮光金属层与所述栅极之间的间距大于所述第一极片与所述第二极片之间的间距。
  20. 一种显示装置，其特征在于，所述显示装置包括权利要求14-19任一项所述的阵列基板。
PCT/CN2018/094558 2018-07-04 2018-07-04 阵列基板及其制造方法、显示装置 WO2020006717A1 (zh)

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