JP6433655B2 - プログラマブルロジックデバイス及び半導体装置 - Google Patents
プログラマブルロジックデバイス及び半導体装置 Download PDFInfo
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- JP6433655B2 JP6433655B2 JP2013260256A JP2013260256A JP6433655B2 JP 6433655 B2 JP6433655 B2 JP 6433655B2 JP 2013260256 A JP2013260256 A JP 2013260256A JP 2013260256 A JP2013260256 A JP 2013260256A JP 6433655 B2 JP6433655 B2 JP 6433655B2
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Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013260256A JP6433655B2 (ja) | 2012-12-24 | 2013-12-17 | プログラマブルロジックデバイス及び半導体装置 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012280383 | 2012-12-24 | ||
| JP2012280383 | 2012-12-24 | ||
| JP2013260256A JP6433655B2 (ja) | 2012-12-24 | 2013-12-17 | プログラマブルロジックデバイス及び半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014143680A JP2014143680A (ja) | 2014-08-07 |
| JP2014143680A5 JP2014143680A5 (enExample) | 2017-01-12 |
| JP6433655B2 true JP6433655B2 (ja) | 2018-12-05 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013260256A Expired - Fee Related JP6433655B2 (ja) | 2012-12-24 | 2013-12-17 | プログラマブルロジックデバイス及び半導体装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9391620B2 (enExample) |
| JP (1) | JP6433655B2 (enExample) |
| KR (1) | KR102103372B1 (enExample) |
| DE (1) | DE102013227153A1 (enExample) |
| TW (1) | TWI611419B (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104321967B (zh) * | 2012-05-25 | 2018-01-09 | 株式会社半导体能源研究所 | 可编程逻辑装置及半导体装置 |
| JP6272713B2 (ja) | 2013-03-25 | 2018-01-31 | 株式会社半導体エネルギー研究所 | プログラマブルロジックデバイス及び半導体装置 |
| US9294096B2 (en) * | 2014-02-28 | 2016-03-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP6541376B2 (ja) | 2014-03-13 | 2019-07-10 | 株式会社半導体エネルギー研究所 | プログラマブルロジックデバイスの動作方法 |
| JP6677449B2 (ja) | 2014-03-13 | 2020-04-08 | 株式会社半導体エネルギー研究所 | 半導体装置の駆動方法 |
| US9875332B2 (en) * | 2015-09-11 | 2018-01-23 | Arm Limited | Contact resistance mitigation |
| CN108352837A (zh) * | 2015-11-13 | 2018-07-31 | 株式会社半导体能源研究所 | 半导体装置、电子构件及电子设备 |
| JP6917168B2 (ja) | 2016-04-01 | 2021-08-11 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| WO2018069787A1 (en) | 2016-10-14 | 2018-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, broadcasting system, and electronic device |
| CN111766935B (zh) * | 2019-04-02 | 2022-06-21 | 瑞昱半导体股份有限公司 | 集成电路芯片及用于集成电路芯片的组态调整方法 |
| WO2023281652A1 (ja) * | 2021-07-07 | 2023-01-12 | 日本電信電話株式会社 | 再構成可能な回路装置 |
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| JPS60198861A (ja) | 1984-03-23 | 1985-10-08 | Fujitsu Ltd | 薄膜トランジスタ |
| JPH0244256B2 (ja) | 1987-01-28 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | Ingazn2o5deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho |
| JPH0244260B2 (ja) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | Ingazn5o8deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho |
| JPS63210023A (ja) | 1987-02-24 | 1988-08-31 | Natl Inst For Res In Inorg Mater | InGaZn↓4O↓7で示される六方晶系の層状構造を有する化合物およびその製造法 |
| JPH0244258B2 (ja) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | Ingazn3o6deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho |
| JPH0244262B2 (ja) | 1987-02-27 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | Ingazn6o9deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho |
| JPH0244263B2 (ja) | 1987-04-22 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | Ingazn7o10deshimesarerurotsuhoshokeinosojokozoojusurukagobutsuoyobisonoseizoho |
| US5343406A (en) | 1989-07-28 | 1994-08-30 | Xilinx, Inc. | Distributed memory architecture for a configurable logic array and method for using distributed memory |
| JP2544020B2 (ja) * | 1990-11-19 | 1996-10-16 | 川崎製鉄株式会社 | プログラマブル論理素子 |
| JPH05251705A (ja) | 1992-03-04 | 1993-09-28 | Fuji Xerox Co Ltd | 薄膜トランジスタ |
| US5352940A (en) | 1993-05-27 | 1994-10-04 | Altera Corporation | Ram convertible look-up table based macrocell for PLDs |
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| JP3479375B2 (ja) | 1995-03-27 | 2003-12-15 | 科学技術振興事業団 | 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとpn接合を形成した金属酸化物半導体装置およびそれらの製造方法 |
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| KR20140082566A (ko) | 2014-07-02 |
| TWI611419B (zh) | 2018-01-11 |
| US9391620B2 (en) | 2016-07-12 |
| DE102013227153A1 (de) | 2014-06-26 |
| KR102103372B1 (ko) | 2020-04-22 |
| JP2014143680A (ja) | 2014-08-07 |
| TW201428765A (zh) | 2014-07-16 |
| US20140176185A1 (en) | 2014-06-26 |
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