JP6429877B2 - フリップチップ・タイプの電子デバイス、およびフリップチップ・タイプの電子デバイスを製造するための方法 - Google Patents
フリップチップ・タイプの電子デバイス、およびフリップチップ・タイプの電子デバイスを製造するための方法 Download PDFInfo
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- JP6429877B2 JP6429877B2 JP2016535229A JP2016535229A JP6429877B2 JP 6429877 B2 JP6429877 B2 JP 6429877B2 JP 2016535229 A JP2016535229 A JP 2016535229A JP 2016535229 A JP2016535229 A JP 2016535229A JP 6429877 B2 JP6429877 B2 JP 6429877B2
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Description
Claims (6)
- フリップチップ・タイプの電子デバイスであって、
キャリア面を有する少なくとも1つのチップ・キャリアであって、前記キャリア面上に導電性材料の1つまたは複数の接点要素を備える、前記チップ・キャリアと、
チップ面を有する少なくとも1つの集積回路チップであって、対応する接点要素に各々が向く、前記チップ面上の導電性材料の1つまたは複数の端子を備える、前記集積回路チップと、
各端子を前記対応する接点要素にはんだ付けするはんだ材料と、
前記接点要素への前記端子のはんだ付けの期間に、前記はんだ材料を制限するための前記接点要素の周りの制限手段と、
を備える電子デバイスにおいて、
前記キャリアが、前記端子からずれた前記チップ面に向く前記キャリア面上の熱的に伝導性の材料の1つまたは複数の熱放散要素を備え、前記放散要素には何らはんだマスクがなく、
前記制限手段が、対応する接点要素の周りに各々がある1つまたは複数のリングを画定するように形状を定めたはんだマスク層の1つまたは複数の部分を備え、
前記制限手段が、隣接するリングの対応する対の間に各々が延在する、1つまたは複数のタイバーを画定するように形状を定めた、前記はんだマスク層の1つまたは複数のさらなる部分を備える、
電子デバイス。 - 前記接点要素および前記熱放散要素が共通の金属層の部分である、請求項1に記載の電子デバイス。
- 前記キャリアと前記チップの間の空間を充たす、熱的に伝導性の材料の充填材をさらに備える、請求項1または2に記載の電子デバイス。
- 各チップが、前記チップ面と反対の追加のチップ面を有し、前記チップが、前記追加のチップ面上の導電性材料の1つまたは複数のさらなる接点要素を備え、前記電子デバイスが、さらなるチップ面を有する少なくとも1つのさらなる集積回路チップをさらに備え、前記さらなるチップが、対応するさらなる接点要素に各々が向く前記さらなるチップ面上の導電性材料の1つまたは複数のさらなる端子を備え、さらなるはんだ材料が、各さらなる端子を前記対応するさらなる接点要素にはんだ付けし、前記さらなる接点要素の周りのさらなる制限手段が、前記さらなる接点要素への前記さらなる端子のはんだ付け期間に前記さらなるはんだ材料を制限するためであり、前記チップが、前記さらなる端子からずれた前記さらなるチップ面に向く、前記追加のチップ面上の熱的に伝導性の材料の1つまたは複数のさらなる熱放散要素を備え、前記さらなる放散要素には何らはんだマスクがない、または
前記キャリアが、さらに別の集積回路チップである、
あるいはその両方の、請求項1ないし3のいずれかに記載の電子デバイス。 - フリップチップ・タイプの電子デバイスを製造するための方法であって、
少なくとも1つのチップ・キャリアのキャリア面上に導電性材料の1つまたは複数の接点要素を形成するステップと、
前記接点要素の周りに制限手段を形成するステップと、
前記接点要素上、または、少なくとも1つの集積回路チップのチップ面上の導電性材料の1つまたは複数の端子上、あるいはその両方上に、はんだ材料を堆積するステップと、
各端子を対応する接点要素に向けて前記チップを置くステップと、
はんだ材料により前記対応する接点要素に各端子をはんだ付けするステップであって、前記はんだ材料が、前記接点要素への前記端子のはんだ付けの期間、前記制限手段によって制限される、前記ステップと、
を含む方法において、
前記端子からずれた前記チップ面に向けるために前記キャリア面上に、熱的に伝導性の材料の1つまたは複数の熱放散要素を形成するステップであって、前記放散要素には何らはんだマスクがなく、
制限手段を形成する前記ステップが、
はんだマスク層を堆積するステップと、
前記はんだマスク層をパターン形成して、対応する接点要素の周りに各々がある1つまたは複数のリングを画定し、隣接するリングの対応する対の間に各々が延在する1つまたは複数のタイバーを画定するステップと、
を含む、
方法。 - 1つまたは複数の接点要素を形成する前記ステップおよび1つまたは複数の熱放散要素を形成する前記ステップが、
共通の金属層を堆積するステップと、
前記共通の金属層を、前記接点要素および前記放散要素を画定する部分へとパターン形成するステップと、
を含む、請求項5に記載の方法。
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GB1321370.7A GB2520952A (en) | 2013-12-04 | 2013-12-04 | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
GB1321370.7 | 2013-12-04 | ||
PCT/IB2014/066356 WO2015083043A1 (en) | 2013-12-04 | 2014-11-26 | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
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US11437333B2 (en) * | 2016-12-30 | 2022-09-06 | Texas Instruments Incorporated | Packaged semiconductor device with a reflow wall |
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US10566313B1 (en) * | 2018-08-21 | 2020-02-18 | International Business Machines Corporation | Integrated circuit chip carrier with in-plane thermal conductance layer |
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-
2013
- 2013-12-04 GB GB1321370.7A patent/GB2520952A/en not_active Withdrawn
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2014
- 2014-11-26 US US15/102,011 patent/US10153250B2/en active Active
- 2014-11-26 WO PCT/IB2014/066356 patent/WO2015083043A1/en active Application Filing
- 2014-11-26 CN CN201480066438.8A patent/CN105793982B/zh active Active
- 2014-11-26 GB GB1610765.8A patent/GB2536383B/en active Active
- 2014-11-26 JP JP2016535229A patent/JP6429877B2/ja active Active
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CN105793982A (zh) | 2016-07-20 |
US10153250B2 (en) | 2018-12-11 |
US10886254B2 (en) | 2021-01-05 |
GB2536383B (en) | 2017-02-01 |
GB201610765D0 (en) | 2016-08-03 |
GB2520952A (en) | 2015-06-10 |
JP2017504189A (ja) | 2017-02-02 |
CN105793982B (zh) | 2019-08-13 |
GB201321370D0 (en) | 2014-01-15 |
WO2015083043A1 (en) | 2015-06-11 |
US20200357774A1 (en) | 2020-11-12 |
US11251160B2 (en) | 2022-02-15 |
US20160307874A1 (en) | 2016-10-20 |
GB2536383A (en) | 2016-09-14 |
US20190043838A1 (en) | 2019-02-07 |
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