CN105793982B - 具有不含焊接掩模的热消散元件的载体的倒装芯片电子装置 - Google Patents
具有不含焊接掩模的热消散元件的载体的倒装芯片电子装置 Download PDFInfo
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- CN105793982B CN105793982B CN201480066438.8A CN201480066438A CN105793982B CN 105793982 B CN105793982 B CN 105793982B CN 201480066438 A CN201480066438 A CN 201480066438A CN 105793982 B CN105793982 B CN 105793982B
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Abstract
提出了一种涉及倒装芯片类型的电子装置的技术方案。特别是,一种倒装芯片类型的电子装置(200,300;400;700;800),包括:具有载体表面(135;835)的至少一个芯片载体(110;805),该载体包括在该载体表面上的导电材料的一个或多个接触元件(140s,140p;740s,740p;840s,840p),具有芯片表面(120;720)的至少一个集成电路芯片(105;705),该芯片包括在该芯片表面上的导电材料的一个或多个端子(125s,125p;725s,725p),每个芯片端子面对对应的接触元件,将每个端子焊接到该对应的接触元件的焊料材料(150;750),以及围绕该接触元件的限制装置(210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p),用于在将该端子焊接到该接触元件期间限制该焊料材料,其中,该载体包括在该载体表面上的导热材料的一个或多个热消散元件(205s,205p;785s,785p;885s,885p),一个或多个热消散元件从该端子移位,该载体表面面对该芯片表面,该消散元件不含任何焊接掩模。
Description
技术领域
本公开涉及电子学领域。更具体地,本公开涉及基于倒装芯片技术的电子装置。
背景技术
若干电子装置包括一个或多个电子部件,每个电子部件由在对应的芯片(例如,硅)上的(单片)集成电路(IC)来实现;在这些电子装置中,芯片通常被安装在(芯片)载体上,以便保护芯片免受机械应力并将他们电连接。每个芯片具备用于访问其集成电路(即,用于交换信号并接收电源)的端子;端子被连接到实现电子器件的任何输入/输出功能的载体的对应的电接触(例如,以球栅阵列(BGA)类型的电子器件中的球的栅格的形式)。
特别是,在倒装芯片类型(也称为控制塌陷芯片连接,C4)的电子装置中,芯片被翻转以使得具有端子的(前)活性表面面对载体的对应焊盘(lands);焊盘在载体的表面上布置成栅格(在其间没有任何其它导电材料,以限制任何短路的风险),并且焊盘通常(例如,通过通孔、或简单地通路)被连接到布置在载体的相反表面上的电接触。然后端子被直接焊接到焊盘,即通过利用附加的熔化的焊料材料接合,而不熔化邻接部件。在芯片和载体之间的空间填充有电绝缘材料的填料(例如,颗粒填充的环氧树脂),以便于改善它们的机械连接并补偿它们不同的热膨胀系数。
通常,回流焊接技术用于将端子焊接到焊盘。简言之,采用行业中可用的各种技术之一(例如,蒸镀、电镀、丝网印刷),焊料凸块被沉积在芯片的端子上。使焊料凸块与也可以用焊料沉积预处理的对应焊盘接触,以便暂时附接到焊盘(由于焊膏或添加的助焊剂的粘性性质)。这样获得的装配件被加热到熔化包含在焊料凸块中的焊料材料。然后该装配件被冷却从而硬化焊料材料,以便在每个端子和对应的焊盘之间创建焊料连接。上述的焊接操作需要使用焊接掩模(或阻焊剂)。焊接掩模限制焊料材料,从而当焊料在液体状态时,限制焊料在焊接期间扩展(以便防止在载体的可能暴露的导体上的焊料材料的未限定的润湿,并防止创建意外的短路的任何焊桥的形成)。为了该目的,焊接掩模包括分布在整个载体上的绝缘材料层(以便确保所需的绝缘功能),其中打开的窗口用于仅暴露焊盘(以便允许焊盘焊接)。
用于将端子连接到电接触的不同的连接技术在本领域中也是已知的。例如,在引线键合技术中,芯片用其(背部)非活性表面安装在载体上(以便使其端子背向载体);每个端子通过用端部焊接的导电材料的导线被连接到对应的焊盘。在这种情况下,焊接掩模设置在载体上,以防止任何焊桥的形成(并且保护任何可能暴露的导体防止氧化)。也已经提出了基于引线键合技术的上述电子装置的替代结构。例如,EP-A-1918992(其全部公开内容通过引用并入本文)公开了使用黑色氧化物层以防止焊料沿导电迹线的长度向下流动,并促进在基板上的裸芯的粘合。此外,US-A-2010/00176503(其全部公开内容通过引用并入本文)公开了具有热通道(via)的基板;焊接掩模被放置在基板上,并且使用焊接掩模在热通道上形成导热凸块,裸芯的非活性表面随后被附接于其上。最后,US-A-2009/0008768(其全部公开内容通过引用并入本文)公开了具有热释放体(thermal relief)的基板;焊接掩模被沉积在热释放体上并被图案化,以便于部分地覆盖热释放体,并且附接裸芯使裸芯的非活性表面在热释放体上,以便改进对应的粘合剂的接合。
一般地,芯片在操作中可能会受到显著的加热,特别是当它们涉及相对高的功率消耗(例如,0.01-1kW的数量级)时;此外,芯片的加热可能是不均匀的,因为它可能集中在其集成电路的具有更多的功率需求部分的区域(例如,微处理器的核)中。由芯片产生的热应被传输到外部环境用于它的耗散,以确保电子装置的正确操作。
然而,在倒装芯片类型的电子装置中,进入或通过载体的热消散效率可能是不完全令人满意(与基于引线键合技术的电子装置相反,在引线键合技术的电子装置中,芯片的非活性表面被附接到载体,使得热量可以从大量芯片被传递到载体)。事实上,在这种情况下,芯片到载体的连接具有差的导热性。特别是,热传输主要通过具有相当有限的尺寸(例如,对于被直径为焊料连接节距一半的焊盘完全填充的栅格的活性表面的15-25%数量级)的焊料连接而发生;相反地,大部分芯片的活性表面与载体(特别是对于仅具有周围端子的芯片)热绝缘,因为两个附加的不良热导体,即,填料和焊接掩模,被插入在它们之间。导热材料的填料也可能被用于改善在焊料连接之间的热消散;然而,在载体上的焊接掩模仍然代表阻碍热消散的热屏障。
若干应用将从进入或通过载体的改进的热消散受益,例如,如果没有足够的空间可用于将大体积的散热器附接到芯片的非活性表面以消散热量的话,或者如果来自芯片的两侧的热量的消散将允许使用不太复杂的、然后有成本效益的热材料和导热片(heatspreader)/散热器,以确保所需要的热消散特性的话。
相反,电子装置的差的热消散效率可能不利地影响它们的性能和可靠性(例如,在智能电话应用中)。此外,它可能需要使用复杂的、然后昂贵的热材料以增强热传输。
发明内容
本文呈现了本公开的简化的发明内容,以便提供其基本的理解;然而,该发明内容的唯一目的是,以简化的形式作为下面更详细的描述的前奏来介绍本公开的一些概念,并且不被解释为它的主要元件的标识,也不作为其范围的限定。
总体而言,本公开是基于在芯片载体上提供热消散元件的构思。
特别地,本公开的一个或多个方面在独立权利要求中陈述,并且其有利的特征在从属权利要求中陈述,所有权利要求的用于通过引用逐字并入本文(任何有利的特征具有参考参照适用每个其他方面的特定方面)。
更具体地,一个方面提供了包括至少一个芯片载体的倒装芯片类型的电子装置,其中载体包括免于任何焊接掩模的一个或多个(导热材料的)热消散元件。
另外的方面提供了在该电子装置中使用的芯片载体。
另外的方面提供了在该电子装置中使用的集成电路芯片。
另外的方面提供了对应的制造方法。
附图说明
本公开的技术方案,以及其进一步的特征和优点,将参照仅仅通过非限制性的指示给出的下面的详细描述,结合附图(其中,为了简化,对应的元件以相同或相似的附图标记表示且不重复它们的说明,并且每个物体的名称一般用于表示它的类型及其属性-诸如值、内容和表示)来阅读进行最好的理解。在这个方面,明确地希望的是,附图没有必要按比例绘制(有一些细节可能被夸大和/或简化的),而且,除非另外指出,它们仅仅用于概念地说明本文描述的结构和过程。特别是:
图1示出了本领域中已知的电子装置的一部分的示意性截面侧视图,可以将根据本公开的实施例的技术方案应用到该电子装置,
图2示出了根据本公开的实施例的电子装置的一部分的示意性截面侧视图,
图3示出了根据本公开的实施例的电子装置的一部分的示意性截面俯视图,
图4示出了根据本公开的实施例的电子装置的一部分的示意性截面侧视图,
图5A-图5D示出了根据本公开的实施例的电子装置的制造方法的主要步骤,
图6A-图6D示出了根据本公开的实施例的电子装置的制造方法的主要步骤,
图7示出了根据本公开的实施例的电子装置的一部分的示意性截面侧视图,以及
图8示出了根据本公开的实施例的电子装置的一部分的示意性截面侧视图。
具体实施方式
特别参照图1,示出了本领域中已知的电子装置100的一部分的示意性截面侧视图,可以将根据本公开的实施例的技术方案应用到该电子装置100。
电子装置100是倒装芯片类型,其中集成电路芯片(或简称芯片)105(或更多)被翻转,然后直接连接到芯片载体(或简称载体)110(或更多)。
更具体地,该芯片105包括半导体材料的裸芯115(例如,硅具有5-20mm×5-20mm×0.5-2mm的量级的尺寸),其上实现电子部件(例如,微处理器)的电路被集成;集成电路具有在操作中相对高的功耗(例如,0.01-1kW的数量级)。导电材料的一个或多个端子(例如,具有数量级50-100μm的宽度的铜的焊垫)被暴露在裸芯115的(芯片活性)表面120(通常覆盖有电绝缘材料的保护层,在图中未示出,诸如氧化硅)上。端子被用于访问芯片105的集成电路;特别是,用标记125s表示的一些(信号)端子用于交换信号(即,由集成电路根据其功能处理的输入/输出电量),且用标记125p表示的一些(电源)端子用于接收芯片105的电源(即,接地电压和参考电源电压)。芯片105具有相对高数量(例如,2000-30000的数量级)的端子125s、125p,其被布置为在表面120上的具有相对小(例如,50-300μιη)节距的栅格图案。
载体110包括电路化基板130(例如,具有10-70mm×10-70mm×1-3mm的数量级的尺寸的玻璃纤维、树脂和金属的层叠体)。导电材料的一个或多个接触元件(例如,具有数量级50-100μm的宽度的铜的焊盘)被暴露在基板130的(由电绝缘材料的最后层限定的)(载体前)表面135上。接触元件被直接焊接到端子125s、125P;特别是,对于(信号)端子125s,接触元件呈不同的(信号)焊盘的形式,其由标记140s表示,并且对于(电源)端子125p,接触元件呈(电源)焊盘的形式,其由标记140p表示并且由一个或多个不同的电源轨145的对应部分限定(由图中的虚线标识)。端子125s、125p通过焊料材料的对应的焊料凸块150被焊接到焊盘140s、140p;例如,焊料凸块150由焊膏组成,即,一种混合物,其包括用于清洁要被焊接元件的助焊剂、在焊接之前用于暂时保持元件的粘合剂以及用于实际焊接元件的焊料粉末(例如,锡-银-铜合金)。为了这个目的,焊接掩模155被设置在表面135上;焊接掩模155是具有用于焊料凸块150(用于在焊接期间限制他们)的开口的电绝缘材料层(例如,环氧树脂)。电绝缘材料的填料160(例如,颗粒填充的环氧树脂)填充芯片105与载体110之间的空间(以改进它们的机械连接,并补偿它们的不同的热膨胀系数)。焊盘140s、140p被连接到导电材料(例如,铜)的对应的电接触180,该电接触180实现电子装置100的任何输入/输出功能;特别是,电子装置100是BGA类型,其中电接触180包括在基板130的与表面135相反的(背面载体)表面165上布置成栅格图案的引线和球,球通过在基板130内形成的通路和金属迹线(在图中未示出)被连接到焊盘140s、140p。整个装配件通常被嵌入在电绝缘材料的壳体170中,其保护芯片150免受外部环境影响而留下暴露的用于接入的电接触180。
现在参照图2,示出了根据本公开的实施例的电子装置200的一部分的示意性截面侧视图。
电子装置200与上述的电子装置不同,其中,导热材料的一个或多个(热)消散元件(例如,由焊盘140s、140p的相同的金属层形成)被提供在表面135上;消散元件面对裸芯115的表面120,但它们从端子125s、125p移位;特别地,消散元件被添加在与它们间隔开的焊盘140s和电源轨145之间(用标记205s表示),并且它们由没有被焊盘140p使用的且留下空闲的电源轨145的剩余部分(用标记205p表示)限定。
此外,焊接掩模由不同的限制结构代替(在下面详细描述),在将端子125s、125p焊接到焊盘140s、140p期间,焊接掩模被布置在用于限制焊料凸块150的焊盘140s、140p的周围;然而,限制结构现在使得消散元件205s、205p不含任何焊接掩模。
上述结构显著地改进了进入或通过载体110的电子装置的热消散效率。特别地,消散元件205s、205p也有助于传输由芯片105在操作中所产生热量进入载体110(在一定程度上可以堪比焊料凸块150的一个)和/或通过载体110(例如,通过将每个消散元件205s、205p与在载体110中形成的一个或多个热通道耦合,在图中未示出)。结果,芯片105的加热和在焊料凸块150处的传传输的浓度被降低。这对电子装置200的性能和可靠性具有有益效果。特别是,即使当没有足够的空间可用于将大体积的散热器附接到芯片105的非活性表面以消散热量时,或当不太复杂的、然后有成本效益的热材料和导热器/散热器被使用时,进入或通过载体110的改进的热消散可以允许获得所需的热消散特性。当电子装置200涉及相对高的功率的消耗时,尤其是当因为它在集成电路的具有更多功率要求的部分的区域(例如,微处理器核)中集中而芯片105的加热是不均匀时,可以清楚的看到上述的优点。
在所讨论的具体实施例中,限制结构包括被成形以限定对应的环的焊接掩模层的一个或多个部分;每个环被布置在对应的焊盘140s、140p周围;特别是,对于(信号)焊盘140s的环(用标记210s表示)被布置在将焊盘410s与消散元件205(或与电源轨145)分离的表面135的空闲部分上,并且,对于(电源)焊盘140p,环(用标记210p表示)被布置在电源轨145的周围部分上(以便限定对应的消散元件205p,由图中的虚线标识)。环210s、210p是相对薄的;例如,环210s、210p具有的宽度约为焊盘140s、140p的直径的约0.1-0.5倍,优选约为0.2-0.4倍,并且还更优选地约为0.25-0.35倍,诸如约为0.3倍(例如,用于具有直径45-75μm的焊盘140s、140p和具有节距140-160μm的焊料凸块的15-25μm的数量级)。这增加了消散元件205s、205p的范围,然后它们帮助由芯片105产生的热量传输进入或通过载体110。
优选地,填料160由导热(但总是电绝缘)材料,例如,填充有导热粒子的环氧树脂构成。定量的,填料160可以具有消散元件205s、205p的热导率的0.01-10%、优选0.25-5%、且还更优选0.5-2%(诸如1%)的数量级的热导率(例如,对于由铜制成的消散元件205s、205p的340W/mK,填料160的1-4W/mK的范围中)。这进一步改进由芯片105产生的热量通过载体110传输到外部的能力(因为它基本上限制了对应的热接口)。
现在参照图3,示出了根据本公开的实施例的电子装置300的一部分的示意性截面俯视图。
在这种情况下,限制结构包括被成形以限定对应的拉杆(tie-bar)310的相同的焊接掩模层的一个或多个另外的部分;每个拉杆310在相邻的环210s、210p的相应对之间(在表面135和/或电源轨145上)延伸。拉杆310也相对较薄(例如,具有与环210s、210p的宽度相同数量级的宽度)。
拉杆310增强在焊料凸块(图中未示出)上的环210s、210p的限制作用;此外,它们增加了(由环210s、210p和拉杆310形成的)整个限制结构的粘附性。然而,这样获得的限制结构的带图案(webbing pattern)暴露具有消散元件205s、205p的大区域。特别地,消散元件205s、205p的尺寸与焊盘140s、140p的区域可以是基本相同的(例如,在芯片的足印(footprint)的10-30%数量级的两种情况下,图中未示出);因此,将由芯片所产生的热量进入或通过载体110传输到外部的能力基本上不受附加的拉杆310的影响。
现在参照图4,示出了根据本公开的实施例的电子装置400的一部分的示意性截面侧视图。
在这种情况下,限制结构包括已经被处理的(例如,氧化的)消散元件205s、205p的一个或多个憎恶(phobic)表面(或者至少部分)以便于憎恶焊料材料;特别地,憎恶表面为消散元件205s的整个暴露的表面(用标记410sd表示)、焊盘140s的侧向表面(用标记410sl表示)和电源轨145的围绕焊盘140p的部分的整个暴露的表面(用标记410p表示)。憎恶表面410sd、410sl、410p防止焊料凸块150遍布它们(因为在液体状态焊料凸块150到空气界面的表面自由能大于憎恶表面410sd、410sl、410p到空气界面的表面自由能)。憎恶表面410sd、410sl、410p比焊盘140s、140p向焊料材料提供更低程度的润湿(润湿性);例如,憎恶表面410sd、410sl、410p的接触角(即,通过液体测量的角度,其中液-气界面满足固-液界面)是焊盘140s、140p的接触角的2-10倍、优选3-8倍且更优选4-6倍,诸如5倍(例如,对于焊盘140s、140p,低于50℃,优选低于20℃,对于憎恶表面410sd、410sl、410p,高于90℃)。上述的结构进一步改进了由芯片105产生热量进入或通过载体110传输到外部的能力。的确,任何的缺少除去了对应的热界面。相反,憎恶表面410sd、410sl、410p比任何焊接掩模是更好的热导体;例如,憎恶表面410sd,410sl、410p可以由无机材料,诸如氧化铜(代替焊接掩模的典型的聚合物材料)来制成,并且它们可以是相对薄的(例如,其厚度低于1μm,而不是焊接掩模的高于10μm的典型的厚度)。
现在参照图5A-5D,示出了用于制造根据本公开的实施例的电子装置的方法的主要步骤;特别地,图指向载体和要被安装在载体上的芯片之间的界面的构造。
从图5A开始,提供大面板505,其中对应于多个相同载体的相同的结构(即,通道和迹线)被大量(例如,几百)复制。金属层510(例如,具有10-30μm的高度的铜)沉积在大面板505的上表面535(对应于载体的前表面)。
金属层510用标准光刻技术图案化(例如,通过使用正性光致抗蚀剂层覆盖金属层510,仅通过金属层510必须被除去之处的光掩模将光致抗蚀剂层暴露于光,显影曝光的光致抗蚀剂层以溶解它从而获得光致抗蚀剂掩模,干法蚀刻没有被光致抗蚀剂掩模保护的金属层510,然后剥离光致抗蚀剂掩模)。
如图5B所示,这种操作产生(信号)焊盘140s、(信号)消散元件205s和电源轨145。
移到图5C,焊接掩模层515(例如,具有20-40μm的高度的环氧树脂)在这样获得的大面板结构(即,表面155、焊盘140s、消散元件205s和电源轨145)上沉积并平面化。
焊接掩模层515用标准光刻技术被图案化。如图5D所示,这种操作产生在焊盘140s周围的(信号)环210s、限定(电源)焊盘140p的(电源)环210p和在电源轨145中的消散元件205p(由图中的虚线标识)。在相同的操作期间,还可能通过适当地改变焊接掩模层的图案在环210s、210p之间形成拉杆(图中未示出)。
然后,制造工艺继续像往常一样依旧使用大面板(或在芯片安装之前单一化成单独的载体)。特别地,助焊剂材料被分配在芯片安装结构上,以便从焊盘140s、104p(和消散元件205s、205p)的暴露的表面除去天然的氧化物层,以防止其进一步氧化并改进焊料材料的润湿性。在端子上沉积焊料凸块的芯片被放置在大平板结构上,它们的活性表面面对它,且焊料凸块与对应的焊盘140s、140p对准(由于焊料材料的粘着性,焊料凸块保持附接到焊盘140s、140p)。然后使用回流焊接技术(例如,在具有用于防止任何对部件损坏的预热区、用于激活焊膏的助焊剂的均热区、用于熔化焊料膏的焊料粉末的回流区、和用于固化焊料连接的冷却区的烤箱(oven)中)将端子焊接到对应的焊盘140s、140p。填充材料被分配到每个芯片和大面板结构之间的空间中,然后被固化以形成对应的填料。对应的电子装置的电接触在大面板505的下表面(对应于载体的背表面)上形成。此时,对应于不同载体的大面板结构的部分通过切割操作被分离。这样获得的每个结构被嵌入(例如,通过模制操作)在对应的壳体中,以便得到图2(或图3)的对应的电子装置。
上述工艺具有电子装置的任何生产商的通用且准备好的适用性;的确,该工艺可以用标准的工艺步骤,仅通过改变金属层(用于获得消散元件)和焊接掩模层(用于获得具有可能的拉杆的环)的光掩模来实现。
现在参照图6A-图6D,示出了用于制造根据本公开的实施例的电子装置的方法的主要步骤。
从图6A开始,获得如上述的图5B的相同的大面板结构(具有焊盘140s、消散元件205s和电源轨145)。
移到图6B,光致抗蚀剂掩模605用标准光刻技术在大面板结构上形成,以便仅覆盖焊盘140s和电源轨145的部分,其中对应的电源焊盘要被限定。优选的,光致抗蚀剂掩模605与每个(信号)焊盘140s对准,以便覆盖其操作表面(与表面535间隔开),但使得其侧向表面(在表面535和操作表面之间延伸)被暴露。
移到图6C,大面板结构受到热氧化处理(例如,在150-500℃的开放空气中)或湿式化学氧化过程。该操作将焊盘140s、消散元件205s和电源轨145的铜的外部层(没有被光致抗蚀剂掩模605覆盖)转换成对应的(功能)氧化物层;特别地,在消散元件205s的整个表面上形成功能氧化物层(以便产生对应的憎恶表面410sd),在焊盘140s的侧向表面上形成功能氧化物层(以便产生对应的憎恶表面410sl),并且在电源轨145的暴露表面上形成功能氧化物层(以便产生对应的憎恶表面410p)。氧化过程足够长(例如,10-120分钟的数量级)以形成具有比自发地形成在焊盘140s、140p上的天然氧化物层实质上更大的厚度的功能氧化物(在室温);例如,功能氧化物层的厚度是天然氧化物层的厚度(例如,50-300nm的数量级)的5-200倍,优选10-100倍,更优选30-70倍,诸如50倍。
此时,光致抗蚀剂掩模605被剥离,如图6D所示。然后该制造工艺如上继续进行,以便获得多件图4的电子装置。在这个方面,应该注意的是,因为功能氧化物层的高得多的厚度,被分配在芯片安装结构上用于除去焊盘的天然氧化物层的助焊剂材料对功能氧化物层基本上是无效的,因此这不会损坏在焊料材料上的功能氧化物层的限制作用。
上述工艺是稍微更加复杂的(因为它需要附加的氧化工艺),但它提供了更好的热消散效率(由于提供薄的导热层而不是任何焊接掩模)。
现在参照图7,示出了根据本公开的实施例的电子装置700的一部分的示意性截面侧视图。
在这种情况下,电子装置700包括另外的芯片705。如上所述,芯片705包括半导体材料的裸芯715,其上实现电子部件(例如,存储器)的电路被集成。导电材料的一个或多个端子被暴露在裸芯715的(芯片活性)表面720上,特别是(信号)端子725s和(电源)端子725p。
导电材料的一个或多个接触元件被暴露在裸芯115的附加的(芯片非活性)表面735(与表面120相反)上,特别是(信号)焊盘740s和(电源)焊盘740p(后者由一个或多个电源轨745的对应的部分来限定)。端子725s、725p通过焊料材料的对应的(另外的)焊料凸块750被焊接到焊盘740s、740p。电绝缘(但优选为导热)材料的填料760填充在芯片705和芯片105之间的空间。一些焊盘740s、740p还可以被连接到对应的端子125s、125p,然后被连接到(例如,通过在裸芯115内形成的通道和金属迹线,图中未示出)载体110的电接触180。
同样,在这种情况下,在表面735上提供导热材料的一个或多个消散元件(面对裸芯715的表面720,但是从其端子725s、725p移位),特别是(信号)消散元件785s和(电源)消散元件785p。此外,限制结构被布置在焊盘740s、740p的周围,用于在将端子725s、725p焊接到焊盘740s、740p期间,限制焊料凸块750(使消散元件785s、785p不含任何焊接掩模)。在所讨论的具体实施例中,限制结构包括焊接掩模层的一个或多个部分,其中焊接掩模层成形以限定对应的环,特别是每一个布置在对应的焊盘740s周围的(信号)环790s和每一个布置在对应的焊盘740p周围的(电源)环790p(优选的,通过相同的焊接掩模层的拉杆彼此连接,图中未示出)。如果限制结构包括已经被处理(例如,氧化)的消散元件785s、785p(或者其至少部分)的一个或多个憎恶表面(图中未示出)以便憎恶焊料材料,类似的考虑也适用。
以这种方式,可以获得3维(3-D)堆叠(具有可能通过附加一个或多个另外的芯片和/或载体进行复制的相同的结构);这提供了电子装置700的高紧凑性。同时,该结构保持可接受的热消散效率(尤其是对于被夹在其他芯片/载体之间的中间芯片)。
现在参照图8,示出了根据本公开的实施例的电子装置800的一部分的示意性截面侧视图。
在这种情况下,载体由另外的芯片805来实现。如上所述,芯片805包括半导体材料的裸芯815,其上实现电子部件(例如,电压调节器)的电路被集成。导电材料的一个或多个端子被暴露在裸芯815的(芯片活性)表面820上,特别是(信号)端子825s和(电源)端子825p。
导电材料的一个或多个接触元件被暴露在裸芯815的附加的(芯片非活性)表面835(与表面820相反)上,特别是(信号)焊盘840s和(电源)焊盘840p(后者由一个或多个电源轨845的对应的部分来限定)。一些焊盘840s、840p还可以被连接到对应的端子825s、825p(例如,通过在裸芯815内形成的通道和金属迹线,图中未示出)。
同样,在这种情况下,在表面835上提供导热材料的一个或多个消散元件(面对裸芯115的表面120,但是从端子125s、125p移位),特别是(信号)消散元件885s和(电源)消散元件885p。此外,限制结构被布置在焊盘840s、840p的周围,用于在将端子125s、125p焊接到焊盘840s、840p期间,限制焊料凸块150(使消散元件885s、885p不含任何焊接掩模)。在所讨论的具体实施例中,限制结构包括成形以限定对应的环的焊接掩模层的一个或多个部分,特别是每一个布置在对应的焊盘840s周围的(信号)环890s和每一个布置在对应的焊盘840p周围的(电源)环890p(优选的,通过相同的焊接掩模层的拉杆彼此连接,图中未示出)。如果限制结构包括已经被处理(例如,氧化)的消散元件885s、885p(或者其至少部分)的一个或多个憎恶表面(图中未示出)以便憎焊料材料,类似的考虑也适用。
以这种方式,可以获得3-D堆叠(具有可以通过附加一个或多个另外的芯片进行复制的相同的结构),而不使用任何载体(例如,用于没有任何壳体的裸芯片应用),其中3-D堆叠紧凑且具有可接受的热消散效率。
自然地,为了满足局部和特定的要求,本领域的技术人员可以将很多逻辑和/或物理的修改和变化应用到本公开。更具体地,尽管本公开已经以一定程度特别地参照其一个或多个实施例进行描述,但应该理解的是,在形式和细节中的各种省略、替换和变化以及其它实施例是可能的。特别地,本公开的不同实施例甚至可以没有前面的描述中阐述的具体细节(诸如数值)来实践,以提供其更透彻的理解;相反地,已知的特征可以被省略或简化以免不必要细节模糊描述。此外,明确的意图是,在与本公开的任何实施例有关的描述的具体元件和/或方法步骤可以作为一般设计选择的问题被结合在任何其它实施例中。在任何情况下,序号或其他限定符只用作标记以区分具有相同名称的元素,但本身不意味着任何的优先权、优先级或顺序。此外,术语包含、包括、具有、含有、涉及(以及它们的任何形式)应旨在以开放的、非穷举的意思(即,不限定于列举的项目),术语基于、依赖于、根据、功能(以及它们的任何形式)应旨在作为非排他的关系(即,具有涉及的可能的另外的变量),以及术语一/一个应旨在作为一个或多个项目(除非另外明确说明)。
例如,实施例提供了倒装芯片类型的电子装置。该电子装置包括至少一个芯片载体,该芯片载体具有载体表面;该载体包括在该载体表面上的导电材料的一个或多个接触元件。该电子装置包括至少一个集成电路芯片,该集成电路芯片具有芯片表面;该芯片包括在该芯片表面上的导电材料的一个或多个端子,每个端子面对对应的接触元件。焊料材料将每个端子焊接到对应的接触元件。在该接触元件的周围提供限制装置,用于在将该端子焊接到该接触元件期间限制该焊料材料。载体包括在该载体表面上且从该端子移位的导热材料的一个或多个热消散元件,该载体表面面对该芯片表面;该消散元件不含任何焊接掩模。
然而,该电子装置可以是任何类型(例如,CSP)的。特别地,该载体可以是任何类型(例如,具有用于每个热消散元件的任何类型和数目的热通道,下至无(down to none))、材料和尺寸(例如,无引线(lead-less)),具有任何类型、形状、尺寸、在任意位置和任何数量的接触元件;在任何情况下,该载体旨在作为适于支撑一个或多个芯片的任何部件的术语的最广泛的意义(包括严格意义上的芯片载体、安装板、其他芯片)。同样地,芯片可以是任何类型、材料和尺寸(例如,DAC)的,具有任何类型、形状、尺寸、在任意位置和任何数量的端子。该电子装置可以包括任何数量的载体和芯片。该焊料材料可以是任何类型(例如,无铅合金)的。该限制装置可以以几种不同的方式(见下文)来实现。消散元件可以是任何类型、形状、尺寸、在任意位置和任何数量(例如,总是与接触元件分离)的。该消散元件不含任何类型的焊接掩模(即,代替的任何类型的绝缘材料层通常用于保护导电迹线免受氧化并防止焊料材料在焊接期间在导体之间桥接,例如,符合在标准IPC-SM-840中陈述的要求)。
在实施例中,接触元件和热消散元件是公共金属层的部分。
然而,该接触元件和该热消散元件可以分别是任何导电材料和任何导热材料,甚至是非金属的且彼此不同(例如,铝)。
在实施例中,该限制装置包括焊接掩模层的一个或多个部分,其被成形以限定每一个围绕对应的接触元件的一个或多个环。
然而,该环可以由任何电绝缘材料形成,并且该环可以具有任何形状和尺寸。
在实施例中,该限制装置包括焊接掩模层的一个或多个另外的部分,其被成形以限定一个或多个拉杆,每一个拉杆在对应的相邻环的对之间延伸。
然而,该拉杆可以具有任何形状和尺寸,并且该拉杆可以被布置在任何位置。在任何情况下,不排除制成不同的材料的拉杆或完全省略拉杆的可能性(例如,当环是较大的,且具有更高的附着力)。
在实施例中,该限制装置包括每个消散元件的至少部分的一个或多个憎恶表面,该一个或多个憎恶表面被处理以憎恶该焊料材料。
然而,该憎恶表面可以具有任何形状、尺寸,并且该憎恶表面可以在任意位置和具有任何数量。例如,可能形成仅围绕该接触元件的该憎恶表面;这提供了更好的热消散效果,由于消散元件的未处理表面比憎恶表面是更好的热导体(但是以用于形成憎恶表面的更精确的掩模操作为代价)。而且,该消散元件可以以任何方式来处理以获得憎恶表面(见下文)。
在实施例中,每个接触元件具有面对对应的端子(与载体表面隔开)的操作表面,以及在载体表面与操作表面之间延伸的横向表面;该限制装置包括每个接触元件的至少部分横向表面的一个或多个另外的憎恶表面,该一个或多个另外的憎恶表面被处理以憎恶该焊料材料。
然而,如上的另外的憎恶表面可以具有任何形状、尺寸,并且它们可以在任意位置和具有任何数量;此外,它们可以通过以任何方式处理接触元件来获得,甚至可以不同于憎恶表面之一(见下文)。在任何情况下,上述特征也可被省略;在这种情况下,为了形成憎恶表面所需的掩模操作的精确度可以放宽,因为对应的掩模可以超出接触元件的边界,而不需要再对准(但是以减小对焊料材料限制作用为代价)。
在实施例中,每个憎恶表面是氧化的表面和/或每个另外的憎恶表面是另外的氧化的表面。
然而,氧化的表面可以具有任何厚度;在任何情况下,不排除憎恶表面、另外的憎恶表面或两者的其他处理(例如,通过用其他金属、衍生物、化合物或复合物镀覆它们)。
更一般地,限制结构的不同、附加或替代的实现方式是可能的。例如,有可能将环(具有或不具有拉杆)与憎恶表面(有或没有另外的憎恶表面)结合。特别地,在实施例中,仅在布置环(和可能的拉杆)之处形成氧化的表面。在这种方式中,氧化的表面增加了环(和拉杆)的粘附力,从而允许减少它们的宽度和/或除去拉杆;同时,消散元件的其他(空闲)部分没有被氧化,然后它们是更好的热导体(但是以用于氧化工艺的更精确的掩模操作为代价)。
在实施例中,该电子装置还包括导热材料的填料,该填料填充载体和芯片之间的空间。
然而,该填料可以由任何材料制成,甚至非导热的(例如,标准的环氧树脂),或者它也可以完全省略。
在实施例中,每个芯片具有与芯片表面相反的附加芯片表面;该芯片包括在附加芯片表面上的导电材料的一个或多个另外的接触元件。该电子装置还包括至少一个另外的集成电路芯片,该另外的集成电路芯片具有芯片表面;该另外的芯片包括在该另外的芯片表面上的导电材料的一个或多个另外导电材料的端子,每个另外的端子面对对应的另外的接触元件。另外的焊料材料将每个另外的端子焊接到对应的另外的接触元件。在该另外的接触元件的周围提供另外的限制装置,用于在将该另外的端子焊接到该另外的接触元件期间限制该另外的焊料材料。该芯片包括在该附加芯片表面上且从该另外的端子移位的导热材料的一个或多个另外的热消散元件,该另外的附加芯片表面面对该另外的芯片表面;该另外的消散元件不含任何焊接掩模。
在附加或替代中,在实施中,载体是又一个另外的集成电路芯片。
然而,另外的芯片和又一个另外的芯片可以是任何类型、材料和尺寸的,具有任何类型、形状、尺寸、在任意位置和任何数目(与芯片/载体相同或不同)的端子/接触元件。另外,与上述相同的附加特征也可以以相同的方式应用在这种情况下。更一般地,电子装置可以包括任何数量的载体和/或芯片,以任何组合。
另一个实施例提供了在上述电子装置中使用的芯片载体;该载体具有载体表面并包括在载体表面上的导电材料的一个或多个接触元件,围绕该接触元件的限制装置,用于在将至少一个芯片的端子焊接到接触元件期间限制焊料材料,以及在载体表面上的一个或多个导热材料的热消散元件,该消散元件不含任何焊接掩模。
另一个实施例提供了在电子装置中使用的集成电路芯片。该芯片具有芯片表面和与该芯片表面相反的附加的芯片表面;该芯片包括在该芯片表面上的导电材料的一个或多个端子,在该附加的芯片表面上的导电材料的一个或多个接触元件,围绕该接触元件的限制装置,用于在将至少一个另外的芯片的端子焊接到接触元件期间限制焊料,以及在该附加的芯片表面上的导热材料的一个或多个热消散元件,该消散元件不含任何焊接掩模。
一般地,如果电子装置、芯片载体和芯片的每个具有不同的结构或包括等同部件(例如,不同的材料),或其具有其它操作特性,类似的考虑适用。在任何情况下,其每个部件可被分离成多个元件,或者两个或多个部件可以组合在一起成为单个元件;而且,每个部件可以被复制,以支持对应的操作的并行执行。此外,除非另有指定,不同的部件之间的任何相互作用通常不需要是连续的,它可以是直接的或通过一个或多个中介部分是间接的。
另一个实施例提供了一种用于制造倒装芯片类型的电子装置的方法。该方法包括以下步骤。导电材料的一个或多个接触元件被形成在至少一个芯片载体的载体表面。限制装置围绕接触元件形成。焊料材料被沉积在接触元件上和/或至少一个集成电路芯片的芯片表面上的导电材料的一个或多个端子上。该芯片被放置以使每个端子面对对应的接触元件。每个端子通过焊料材料被焊接到对应的接触元件(在将端子焊接到接触元件期间,由限制装置限制焊料材料)。在该载体表面上形成从该端子移位的导热材料的一个或多个热消散元件,该载体表面面对该芯片表面;该消散元件不含任何焊接掩模。
然而,该方法可以在任何级别(在大面板或已经单一化的面板中的一个或多个载体上和/或在晶片或已经单一化的晶片中的一个或多个芯片上)执行;端子可以以任何方式被焊接到接触元件(例如,通过将焊料材料沉积在端子、接触元件或两者上,其中焊料材料然后以任何方式熔化,诸如红外线灯)。接触元件、消散元件和限制装置可以以任何方式来形成(见下文)。
在实施例中,所述形成一个或多个接触元件和所述形成一个或多个热消散元件包括沉积公共金属层,以及图案化该公共金属层成定义接触元件和热消散元件的部分。
然而,公共金属层可以以任何方式被图案化(例如,用剥离技术);此外,可以选择性地沉积金属层以直接形成接触元件和消散元件。在任何情况下,不排除用不同的金属层(分别用于接触元件和用于消散元件)重复相同的操作。
在实施例中,所述形成限制装置包括沉积焊接掩模层,并图案化该焊接掩模层以限定围绕对应的接触元件的一个或多个环。
然而,在这种情况下,此外,焊接掩模层可以以任何方式被图案化,或者可以选择性地沉积。
在实施例中,所述形成限制装置包括图案化该焊接掩模层,以限定一个或多个拉杆,每一个拉杆在对应的相邻环的对之间延伸。
然而,上述的类似的考虑在这种情况下也适用。
在实施例中,所述形成限制装置的步骤包括处理每个消散元件的至少部分,以获得憎恶焊料材料的一个或多个憎恶表面。
然而,该消散元件可以以任何方式来处理以获得憎恶表面(见上文)。
在实施例中,所述形成限制装置包括处理每个接触元件的侧向表面的至少部分,在载体表面和接触元件的操作表面之间延伸,以获得憎恶焊料材料的一个或多个另外的憎恶表面,其中接触元件的操作表面面对与载体表面间隔开的对应的端子。
然而,该接触元件可以以任何方式来处理以获得另外的憎恶表面(见上文)。
在实施例中,所述处理每个消散元件的至少部分和所述处理每个接触元件的侧向表面的至少部分的步骤分别包括氧化每个消散元件的至少部分和氧化每个接触元件的侧向表面的至少部分。
然而,该氧化操作可以以任何方式来执行(例如,在不同的温度下,在不同的空气中)。
在实施例中,该方法还包括用导热材料的填料填充在载体和芯片之间的空间。
然而,填料可以以任何方式来提供(例如,通过加入或不加入固化剂和/或加速剂来固化填料);此外,填料可以有任何其它材料制成,并且也可以省略(见上文)。
在实施例中,该方法还包括以下步骤。另外的限制装置围绕与每个芯片的芯片表面相反的附加的芯片表面上的导电材料的一个或多个另外的接触元件来形成。另外的焊料材料被沉积在另外的接触元件上和/或至少一个另外的集成电路芯片的另外的芯片表面上的导电材料的一个或多个另外的端子上。该另外的芯片被放置以使每个另外的端子面对对应的另外的接触元件。每个另外的端子被焊接到对应的另外的接触元件(在将另外的端子焊接到另外的接触元件期间,由另外的限制装置限制另外的焊料材料)。在附加的芯片表面上形成从另外的端子移位的导热材料的一个或多个另外的热消散元件,附加的芯片表面面对另外的芯片表面;另外的消散元件不含任何焊接掩模。
在附加或替代中,在实施中,载体是又一个另外的集成电路芯片。
然而,上述的步骤可以以任何组合重复任意次数(上述的相同的附加的特征也可以以相同的方式应用在这种情况中)。
更一般地,电子装置可以用不同的技术、利用数量和类型不同的掩模,或用其他工艺参数来制造。特别地,如果相同的技术方案用等同方法来实现(通过使用具有其更多步骤或部分的相同功能的类似的步骤、除去不必要的一些步骤、或增加另外的可选的步骤),类似的考虑适用;此外,步骤可以以不同的顺序、同时或以交错的方式(至少部分地)来执行。
Claims (15)
1.一种倒装芯片类型的电子装置(200,300;400;700,800),包括:
具有载体表面(135;835)的至少一个芯片载体(110;805),所述载体包括在所述载体表面上的导电材料的一个或多个接触元件(140s,140p;740s,740p;840s,840p);
具有芯片表面(120;720)的至少一个集成电路芯片(105;705),所述芯片包括在所述芯片表面上的导电材料的一个或多个端子(125s,125p;725s,725p),每个所述端子面对对应的接触元件;
将每个所述端子焊接到对应的所述接触元件的焊料材料(150;750);以及
围绕所述接触元件的限制装置(210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p),所述限制装置用于在将所述端子焊接到所述接触元件期间限制所述焊料材料,
其特征在于:所述载体包括在面对所述芯片表面的所述载体表面上的导热材料的一个或多个热消散元件(205s,205p;785s,785p;885s,885p),所述热消散元件从所述端子移位,所述热消散元件邻接所述限制装置,并包围所述接触元件周围的限制装置,不含任何焊接掩模。
2.根据权利要求1所述的电子装置(200,300;400;700;800),其中所述接触元件(140s,140p;740s,740p;840s,840p)和所述消散元件(205s,205p;785s,785p;885s,885p)是公共金属层(510)的部分。
3.根据权利要求1所述的电子装置(200,300;700;800),其中所述限制装置(210s,210p,310;410s1,410sd,410p;790s,790p;890s,890p)包括焊接掩模层(515)的一个或多个部分,所述焊接掩模层的一个或多个部分成形为限定一个或多个环(210s,210p;740s,740p;840s,840p),每个所述环围绕对应的所述接触元件(140s,140p;740s,740p;840s,840p)。
4.根据权利要求3所述的电子装置(300),其中所述限制装置(210s,210p,310)包括所述焊接掩模层(515)的一个或多个另外的部分,所述焊接掩模层的一个或多个另外的部分成形为定义一个或多个拉杆(310),每个所述拉杆在对应的一对相邻环(210s,210p)之间延伸。
5.根据权利要求1-4中任一项所述的电子装置(400),其中所述限制装置(410sl,410sd,410p)包括每个消散元件(250s,205p)的至少部分的一个或多个憎恶表面(410sd,410p),所述憎恶表面被处理以憎恶所述焊料材料(150)。
6.根据权利要求5所述的电子装置(400),其中每个接触元件(140s,140p)具有操作表面和侧向表面,所述操作表面面对对应的所述端子(125s,125p)且与所述载体表面(135)隔开,所述侧向表面在所述载体表面与所述操作表面之间延伸,所述限制装置(410sl,410sd,410p)包括每个接触元件的至少部分侧向表面的一个或多个另外的憎恶表面(410sl),所述另外的憎恶表面被处理以憎恶所述焊料材料(150)。
7.根据权利要求5所述的电子装置(400),其中每个憎恶表面(410s1,410sd)是氧化的表面和/或每个另外的憎恶表面(410sl)是另外的氧化的表面。
8.根据权利要求1-4中任一项所述的电子装置(200,300;400;700;800),还包括填充所述载体(110)和所述芯片(105)之间的空间的导热材料的填料(160;760)。
9.根据权利要求1-4中任一项所述的电子装置(700;800),其中每个芯片(105)具有与所述芯片表面(120)相反的附加的芯片表面(735),所述芯片包括在所述附加的芯片表面上的导电材料的一个或多个另外的接触元件(740s,740p),其中所述电子装置还包括具有另外的芯片表面(720)的至少一个另外的集成电路芯片(705),所述另外的芯片包括在所述另外的芯片表面上的导电材料的一个或多个另外的端子(725s,725p),每个另外的端子面对对应的所述另外的接触元件,将每个另外的端子焊接到对应的另外的接触元件的另外的焊料材料(750),以及另外的限制装置(790s,790p),所述另外的限制装置围绕所述另外的接触元件,用于在将所述另外的端子焊接到所述另外的接触元件期间限制所述另外的焊料材料,其中,所述芯片包括在所述附加的芯片表面上且从所述另外的端子移位的导热材料的一个或多个另外的热消散元件(785s,785p),所述附加的芯片表面面对所述另外的芯片表面,所述另外的消散元件不含任何焊接掩模,和/或
其中所述载体是又一个另外的集成电路芯片(805)。
10.一种用于制造倒装芯片类型的电子装置(200,300;400;700;800)的方法,所述方法包括:
在至少一个芯片载体(110;805)的载体表面(135;835)上形成导电材料的一个或多个接触元件(140s,140p;740s,740p;840s,840p),
围绕所述接触元件形成限制装置(210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p),
将焊料材料(150;750)沉积在所述接触元件上和/或至少一个集成电路芯片(105;705)的芯片表面上的导电材料的一个或多个端子上(125s,125p;725s,725p),
放置所述芯片,使每个端子面对对应的接触元件,以及
将每个端子通过焊料材料焊接到所述对应的接触元件,在将所述端子焊接到所述接触元件期间,由所述限制装置限制所述焊料材料,其特征在于,
在所述载体表面上形成从所述端子移位的导热材料的一个或多个热消散元件(205s,205p;785s,785p;885s,885p),所述载体表面面对所述芯片表面,所述热消散元件邻接所述限制装置,并包围所述接触元件周围的限制装置,不含任何焊接掩模。
11.根据权利要求10所述的方法,其中所述形成一个或多个接触元件(140s,140p;740s,740p;840s,840p)和所述形成一个或多个热消散元件(205s,205p;785s,785p;885s,885p)包括:
沉积公共金属层(510),并且
将所述公共金属层图案化成限定所述接触元件和所述消散元件的部分。
12.根据权利要求10所述的方法,其中所述形成限制装置(210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p)包括:
沉积焊接掩模层(515),并且
图案化所述焊接掩模层,以定义一个或多个环(210s,210p;790s,790p;890s,890p),每个所述环围绕对应的所述接触元件(140s,140p;740s,740p;840s,840p)。
13.根据权利要求12所述的方法,其中所述形成限制装置(210s,210p,310)包括:
图案化所述焊接掩模层(515)以限定一个或多个拉杆(310),每个所述拉杆在对应的一对相邻环(210s,210p)之间延伸。
14.根据权利要求10-13中任一项所述的方法,其中所述形成限制装置(410sl,410sd,410p)包括:
处理、特别是氧化每个消散元件(250s,205p)的至少部分,以获得憎恶所述焊料材料(150)的一个或多个憎恶表面(410sd,410p)。
15.根据权利要求14所述的方法,其中所述形成限制装置(410s1,410sd,410p)包括:
处理、特别是氧化每个接触元件(140s,140p)的侧向表面的至少部分,所述侧向表面在所述载体表面(135)和所述接触元件的操作表面之间延伸,所述操作表面面对对应的所述端子(125s,125p)且与所述载体表面隔开,以获得憎恶所述焊料材料(150)的一个或多个另外的憎恶表面(410sl)。
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2018
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CN105793982A (zh) | 2016-07-20 |
WO2015083043A1 (en) | 2015-06-11 |
GB2520952A (en) | 2015-06-10 |
US20160307874A1 (en) | 2016-10-20 |
US20190043838A1 (en) | 2019-02-07 |
JP2017504189A (ja) | 2017-02-02 |
US11251160B2 (en) | 2022-02-15 |
GB201610765D0 (en) | 2016-08-03 |
US10886254B2 (en) | 2021-01-05 |
GB2536383B (en) | 2017-02-01 |
JP6429877B2 (ja) | 2018-11-28 |
US10153250B2 (en) | 2018-12-11 |
GB2536383A (en) | 2016-09-14 |
GB201321370D0 (en) | 2014-01-15 |
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