CN101821842B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN101821842B CN101821842B CN2008801103741A CN200880110374A CN101821842B CN 101821842 B CN101821842 B CN 101821842B CN 2008801103741 A CN2008801103741 A CN 2008801103741A CN 200880110374 A CN200880110374 A CN 200880110374A CN 101821842 B CN101821842 B CN 101821842B
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- semiconductor device
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- solder resist
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Abstract
一种半导体装置,当在大型且扁平化的半导体装置的基板和半导体部件之间填充底部填充树脂时,能够均匀地渗透填充。半导体装置在基板(10)上安装有半导体部件(20),并且在基板和半导体部件之间填充有底部填充树脂(40),在基板上与底部填充树脂接触的区域的一部分具有亲液化处理部(30),亲液化处理部被处理为与亲液化处理部的周围的区域部分相比至少对液状的底部填充树脂具有亲液性。亲液化处理部被处理为接触角小于亲液化处理部的周围的区域部分的接触角。亲液化处理部的周围的区域部分被覆有阻焊剂。在亲液化处理部,在阻焊剂上形成有通过紫外光曝光被实施了亲液化处理的氧化钛膜。
Description
技术领域
(对相关申请的说明)
本发明以日本专利申请:特愿2007-264369号(2007年10月10日申请)为基础并主张其优先权,并且该申请的全部内容通过引用被包含于本说明书中。
本发明涉及一种通过焊锡凸块将半导体部件安装在基板上的半导体装置,尤其涉及在基板和半导体部件之间填充了底部填充树脂(Underfill resin)的半导体装置。
背景技术
携带以笔记本个人电脑为代表的手机和便携式信息终端、影像和音乐的重放设备、游戏机等电子设备的情况在增加。这些电子设备必须确保坠落撞击荷重和车辆等的振动等各种使用环境下的可靠性,需要高强度的部件安装技术。另一方面,由于功能强化,所安装的部件增加,针对高密度、薄型安装技术的开发要求比较强烈。为了解决高密度、薄型化和高强度这种矛盾的课题,已经有关于高密度、薄型化的各种报告。在这种状况下,用于实现半导体封装的安装构造薄型化的LGA(Land Grid Array:矩栅阵列)型封装得到普及。
并且,同时也要求窄间距化,在二次安装的领域中还需要同时实现基于LGA化的扁平化和窄间距化。另一方面,在SiP(System InPackage:系统级封装)、PoP(Package on Package:叠层封装)等新形式的封装中,存在封装大型化的趋势。
考虑到这些情况,而且为了确保与现状相同的可靠性,往往需要 使用底部填充树脂进行加强。作为应对上述大面积、窄间隙的技术,已经提出了以下所述的技术。例如,在专利文献1中,提出了不从侧面填充树脂并渗透,而预先向半导体封装安装部提供树脂的技术。另外,在专利文献2中提出了使用对加强用的填充材料即二氧化硅进行表面改性而成为球状的材料,提高流动性的技术。
专利文献1:日本特开2004-312051号公报
专利文献2:日本特开2004-292250号公报
非专利文献1:日本化学会編、藤嵨昭責任編集、「光触媒」丸善株式会社、2005年9月
发明内容
以上的专利文献1、2和非专利文献1的全部公开内容通过引用被记述在本说明书中。以下是对本发明的关联技术的分析。
向大型且扁平化的安装结构部涂敷底部填充树脂时,在使树脂从侧面渗透的情况下存在难以整体均匀涂敷的问题。
与此相对,专利文献1不是从侧面渗透的方式,所以比较有效,但是需要在安装部件之前供给树脂,并在填充树脂后进行基于无铅回流焊的锡焊。因此,需要采取在印刷焊锡时予以回避的形状,有可能导致树脂混入到锡焊连接部,存在操作困难的一面。
并且,在专利文献2中以加入填充材料为前提,但从可靠性方面讲往往是没有填充材料比较好,具有在重要的场合不能使用的问题。
本发明的主要课题是,当在大型且扁平化的半导体装置的基板和半导体部件之间填充底部填充树脂时,能够均匀地渗透填充。
在本发明的一个方面,半导体装置在基板上安装有半导体部件, 并且在所述基板和所述半导体部件之间填充有底部填充树脂,在所述基板和所述半导体部件一方或双方中与所述底部填充树脂接触的区域的一部分具有亲液化处理部,所述亲液化处理部被处理为与所述亲液化处理部的周围的区域部分相比至少对液状的底部填充树脂具有亲液性。
根据本发明,能够偏差较小且稳定地供给底部填充树脂。并且,一般在减小基板与半导体部件的连接高度时,可靠性降低,但本发明即使降低基板与半导体部件的连接高度,也能够稳定地填充底部填充树脂,所以能够减小连接高度。并且,能够消除半导体部件的中央部分的气泡,因此能够实现因加热及冷却造成的基板的应力降低。并且,由于能够消除半导体部件的中央部分的气泡,所以能够降低由于基板弯曲而对双面安装时的背面部件造成不良影响。另外,由于阻焊剂上的亲液化处理部的表面与底部填充树脂的亲和性提高,所以能够提高底部填充树脂的密着力。
附图说明
图1是示意表示本发明的实施例1的半导体装置的基板的亲液化处理部的俯视图。
图2是示意表示本发明的实施例1的半导体装置的结构的剖视图。
图3是示意表示本发明的实施例1的半导体装置的基板的结构的局部放大剖视图。
图4是将本发明的实施例1的半导体装置的底部填充树脂的渗透作用与比较例进行比较的图。
图5是用于说明亲液性的图。
图6是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的俯视图。
图7是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的变形例1的俯视图。
图8是示意表示本发明的实施例4的半导体装置的基板的亲液化 处理部的变形例2的俯视图。
图9是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的变形例3的俯视图。
图10是示意表示本发明的实施例5的半导体装置的结构的剖视图。
图11是示意表示本发明的实施例6的半导体装置的结构的剖视图。
标号说明
10基板
11焊盘
12布线
13通孔
14绝缘层
15阻焊剂
20半导体部件
21焊锡凸块
30亲液化处理部
31引导路径
40底部填充树脂
41气泡
具体实施方式
在本发明的一个实施方式中,半导体装置在基板(图2中的10)上安装有半导体部件(图2中的20),并且在所述基板(图2中的10)和所述半导体部件(图2中的20)之间填充有底部填充树脂(图2中的40),所述半导体装置在所述基板(图2中的10)和所述半导体部件(图2中的20)的一方或双方中与所述底部填充树脂(图2中的40)接触的区域的一部分具有亲液化处理部(图2、图10、图11中的30),所述亲液化处理部被处理为与所述亲液化处理部的周围的区域部分相比至少对液状的底部填充树脂具有亲液性(方式1)。
另外,所述半导体装置也可以是下述方式。
优选的是,所述亲液化处理部被处理为接触角小于所述亲液化处理部的周围的区域部分的接触角(方式2)。
优选的是,所述亲液化处理部的周围的区域部分与所述亲液化处理部相比,至少对液状的底部填充树脂是疏液性(方式3)。
优选的是,所述亲液化处理部的周围的区域部分被覆有阻焊剂,在所述亲液化处理部,在阻焊剂上形成有通过紫外光曝光被实施了亲液化处理的氧化钛膜(方式4)。
优选的是,所述亲液化处理部的周围的区域部分被覆有阻焊剂,在所述亲液化处理部,阻焊剂的表面通过离子照射被实施了表面改性(方式5)。
优选的是,所述亲液化处理部至少被配置在安装有所述半导体部件的区域的中央部分(方式6)。
优选的是,所述亲液化处理部具有从安装有所述半导体部件的区域的中央部分向外周延伸的一个或多个引导路径(方式7)。
实施例1
使用附图说明本发明的实施例1的半导体装置。图1是示意表示本发明的实施例1的半导体装置的基板的亲液化处理部的俯视图。图2是示意表示本发明的实施例1的半导体装置的结构的剖视图。图3是示意表示本发明的实施例1的半导体装置的基板的结构的局部放大剖视图。
实施例1的半导体装置是在基板10上经由焊锡凸块(Solder bump)21安装有半导体部件20,并在基板10和半导体部件20之间填充了底部填充树脂40的半导体装置。
基板10是交替层叠布线12和绝缘层14,并使布线之间、布线-焊盘之间经由通孔13相连接的多层布线基板。基板10在半导体部件20侧的一面形成有多个焊盘11,在焊盘11的周缘部和绝缘层14的表面被覆有阻焊剂15,用于防止与相邻的焊锡凸块21短路和实现与表层电路绝缘。在焊盘11表面的中央部分没有被覆阻焊剂15。
阻焊剂15采用环氧类等有机材料,与亲液化处理部30相比,至少与液状的底部填充树脂40具有疏液性。焊盘11经由焊锡凸块21与半导体部件20电连接。在阻焊剂15表面的预定区域形成有亲液化处理部30。基板10例如采用通常使用的半导体封装的转接板(Interposer),安装该基板10的安装基板采用树脂制的基板。
半导体部件20是由半导体芯片、半导体封装等构成的部件。在半导体部件20的基板10侧的一面形成有多个焊盘(未图示)。焊盘经由焊锡凸块21与基板10的焊盘11电连接。在半导体部件20的基板10侧的一面,除了焊盘表面之外被覆了阻焊剂(未图示),以防止与相邻的焊锡凸块21短路。
亲液化处理部30在阻焊剂15的表面中安装有半导体部件20的区域的中央形成为矩形状。亲液化处理部30通过对阻焊剂15选择性地进行亲液化处理而形成。通过亲液化处理部30能够在各个部分控制底部填充树脂40的渗透速度。
作为亲液化处理方法的一例,有涂敷氧化钛膜并照射紫外线的方法。阻焊剂15采用环氧类有机材料,所以表面是疏液性,但可以在该 阻焊剂15的表面通过喷射涂敷形成氧化钛膜,然后通过照射紫外线来发挥亲液性。虽然也依赖于照射量,但在照射之后经过一定时间后,再次恢复成为疏液性,所以需要在照射紫外线之后进行焊锡供给、部件安装、回流。
底部填充树脂40是填充于基板10和半导体部件20之间的树脂。底部填充树脂40是液状密封材料固化后形成的。液状密封材料根据树脂的类型和剂型,被分类为热固化/热塑、溶剂/无溶剂、一液/二液型等,可以使用把环氧树脂作为主成分的材料。
下面,说明本发明的实施例1的半导体装置的制造方法。
在基板10的制造工序中,在形成最终表面电路后形成阻焊剂15。一般利用层压装置粘贴膜抗蚀剂(Film resist),或者通过丝网印刷、喷射涂敷法、帘式涂敷(Curtain coat)法中的任一方法形成液状阻焊剂。
在形成阻焊剂后形成亲液化处理部30。在形成亲液化处理部30时,通过旋转涂敷(spin coat)、浸渍涂敷(dip coat)、喷射涂敷等形成氧化钛膜,然后使用在需要亲液化的部分开口的掩模进行紫外光照射,用碱性水溶液溶解不需要的部分。结果,只有掩模的开口部分成为亲液性。这样,能够在普通基板10的阻焊剂15上形成作为亲液化处理部30的氧化钛膜。通常,氧化钛膜是疏液性的,所以氧化钛膜能够直接充分发挥作为阻焊剂的性能。
然后,通过印刷焊锡、回流锡焊连接半导体部件20,然后冷却。
然后,形成底部填充树脂40。在形成底部填充树脂40时,若从半导体部件20的侧方供给底部填充树脂40,则底部填充树脂40通过毛细管现象渗透到半导体部件20与基板10的间隙中。
另外,此处是在印刷焊锡之前进行紫外光照射,但在印刷焊锡之后安装部件之前进行紫外光照射也有效。在这种情况下,虽然程度甚微,但也能缩短照射紫外光后到涂敷底部填充树脂的时间,所以能够确保更强的亲液性。另外,由于在印刷焊锡之后曝光,所以曝光时能够避开印刷焊锡。
下面,使用附图说明本发明的实施例1的半导体装置的底部填充树脂的渗透作用。图4是将本发明的实施例1的半导体装置的底部填充树脂的渗透作用与比较例进行比较的图。
如图4(A)所示,准备了具有亲液化处理部的实施例1和不具有亲液化处理部的比较例。并且,如图4(B)所示,实施例1和比较例都同样在半导体部件20的左右两边涂敷底部填充树脂40。然后,按照图4(C)、(D)、(E)依次进行。
在比较例中,由于不具有亲液化处理部,所以不优先在中央附近连接,并产生气泡41。由于底部填充树脂40填充不到气泡41中,成为可靠性降低的原因。并且,由于不能控制气泡41的大小、形状等,所以可能会产生突发性不良。虽然也有从一边进行底部填充树脂的涂敷并使其渗透的方法,但如果BGA部件大型化,则有可能导致渗透在中途停止。
而在实施例1中,由于在中央附近具有亲液化处理部30,所以在来自左右两边的底部填充树脂40到达亲液化处理部30时,向亲液化处理部30内的渗透速度变快,所以在亲液化处理部30中立即扩散,底部填充树脂40优先在中央附近连接,然后整体渗透,不会产生气泡。
下面,使用附图说明本发明的实施例1的半导体装置的亲液化处理部的亲液性。图5是说明亲液性的图。
亲液性、疏液性是根据固体表面上的液体的接触角来规定的,但一般没有明确把接触角为几度以下称为亲液性的规定。如图5所示,在把固体表面能设为γS、把液体表面能设为γL、把液体-固体间的界面能设为γSL、把接触角设为θ时,可以表示为式1。
(式1)
cosθ=(γS-γSL)/γL
接触角越小,渗透性越大,所以得知在认为液体表面能γL一定的情况下,在固体表面能γS较大而且界面能γSL较小时,成为亲液性。关于通过照射紫外线引起的氧化钛膜的亲液化,在非专利文献1中有详细记述,通过照射紫外线来保持固体表面能较高的状态。并且,通常氧化钛膜与水的接触角为30°左右,但在照射1小时后降低为5°,在照射2小时后基本降低为0°。然后,在较暗的场所保存,接触角又缓慢上升,在200小时后达到5°,在1500小时后达到30°。
根据实施例1,无论从一边或两边涂敷底部填充树脂40,其向安装有半导体部件20的区域的中心部渗透的渗透速度都变快,并且渗透性增大,所以即使是狭小的间隙也能够确实地渗透。并且,通过控制亲液化处理部30,或控制亲液性的程度,能够任意获取渗透路径,所以能够实现去除封装中央部的空气后向其周边部进行渗透的理想渗透。并且,能够偏差较小且稳定地供给底部填充树脂40。并且,一般在减小基板10与半导体部件20的间隔时,可靠性降低,但由于实施例1在减小基板10与半导体部件20的间隔时,也能够实现稳定的底部树脂填充,所以能够减小间隔。并且,由于能够消除半导体部件20中央部的气泡,所以能够实现因加热及冷却造成的基板10的应力降低。并且,由于能够消除半导体部件20中央部的气泡,所以能够降低由于基板10弯曲而对双面安装时的背面部件造成不良影响。另外,在亲液化处理部中,由于阻焊剂15的表面与底部填充树脂40的亲液性提高, 所以能够提高底部填充树脂40的密着力。
实施例2
说明本发明的实施例2的半导体装置。在实施例1中形成亲液化处理部(图1~3中的30)时,在阻焊剂上形成氧化钛膜,然后形成掩模,只对从掩模的开口部分露出的氧化钛膜照射紫外线来形成亲液化处理部30,但在实施例2中形成亲液化处理部(相当于图1~3中的30)时,在形成阻焊剂后,在不需要的部分不进行氧化钛膜的形成,所以预先使用掩模只在需要亲液化的部分形成氧化钛膜,然后在去除掩模后照射紫外线,把氧化钛膜整体作为亲液化处理部(相当于图1~3中的30)。这样,具有在亲液化处理时不使用掩模的优点。
实施例3
说明本发明的实施例3的半导体装置。在实施例3中,不像实施例1、2的亲液化处理部(相当于图1~3中的30)那样使用氧化钛膜,而是通过离子照射进行阻焊剂(相当于图3中的15)的表面改性来形成亲液化处理部,这种方法也有效。在这种情况下,在形成阻焊剂后,形成只在需要亲液化的部分开口的掩模,然后通过离子照射,只把从掩模的开口部分露出的阻焊剂(相当于图3中的15)的表面作为亲液化处理部(相当于图1~3中的30)。这样,具有在亲液化处理时不使用氧化钛膜的优点。
实施例4
使用附图说明本发明的实施例4的半导体装置。图6是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的俯视图。图7是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的变形例1的俯视图。图8是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的变形例2的俯视图。图9是示意表示本发明的实施例4的半导体装置的基板的亲液化处理部的变形例3的俯视图。
在实施例4中,如图6~9所示,形成有从亲液化处理部30向外周延伸的引导路径31,该亲液化处理部30形成于阻焊剂(相当于图3中的15)的表面中安装有半导体部件20的区域的中央。引导路径31与亲液化处理部30同样,通过对阻焊剂(相当于图3中的15)选择性地进行亲液化处理而形成。引导路径31与亲液化处理部30连接。
在图6所示的结构中,从引出有引导路径31的半导体部件20的边侧供给底部填充树脂(图2中的40),由此底部填充树脂(图2中的40)经过引导路径31优先填充到亲液化处理部30中,然后向其他部分渗透扩散,所以能够向安装有半导体部件20的区域整体填充底部填充树脂(图2中的40)。其中,在图1中用四边形示出亲液化处理部30,但如图6所示,如果在涂敷部附近设置朝向中央的引导路径31,则即使是一边涂敷也能够渗透。
并且,如图7、图8所示,也可以设置多个引导路径31。另外,如图9所示,也可以将中心部的亲液化处理部30设为圆形并设置引导路径31。
根据实施例4,能够发挥与实施例1相同的效果,并且通过考虑底部填充树脂(图2中的40)的渗透性、焊盘配置等来设置引导路径31,向安装有半导体部件20的区域的中心部渗透的渗透速度进一步加快。
实施例5
使用附图说明本发明的实施例5的半导体装置。图10是示意表示本发明的实施例5的半导体装置的结构的剖视图。
在实施例1~4中,在基板10上形成亲液化处理部(图2中的30),但在实施例5中,如图10所示,只在半导体部件20的背面(端子侧的一面)形成亲液化处理部30。半导体部件20的亲液化处理部30的 平面形状可以是与图1、图6~9所示的亲液化处理部30(引导路径31)相同的形状。另外,在半导体部件20的基板10侧的一面,除了焊盘表面之外被覆有阻焊剂(未图示),以防止与相邻的焊锡凸块21短路。在该半导体部件20的阻焊剂(未图示)的表面的预定部分形成有亲液化处理部30。关于亲液化处理方法,可以通过与实施例1~3相同的方法进行。根据实施例5,能够发挥与实施例1相同的效果。
实施例6
使用附图说明本发明的实施例6的半导体装置。图11是示意表示本发明的实施例6的半导体装置的结构的剖视图。
在实施例1~4中,在基板10上形成亲液化处理部(图2中的30),但在实施例6中,如图11所示,在半导体部件20和基板10上形成亲液化处理部30。亲液化处理部30形成于半导体部件20的背面(端子侧的一面)的预定区域、和基板10的阻焊剂15的表面的预定区域。优选半导体部件20的亲液化处理部30和基板10的亲液化处理部30彼此相对,而且平面形状相对应(面对称)。亲液化处理部30的平面形状可以是与图1、图6~9所示的亲液化处理部30(引导路径31)相同的形状。关于亲液化处理方法,可以通过与实施例1~3相同的方法进行。根据实施例6,能够发挥与实施例1相同的效果,并且向安装有半导体部件20的区域的中心部渗透的渗透速度进一步加快。
在本发明的全部公开(包括权利要求)的范围内,可以根据其基本技术思想进行实施方式及实施例的变更、调整。并且,在本发明的权利要求的范围内,可以进行各种公开要素的多种组合及选择。
Claims (6)
1.一种半导体装置,在基板上安装有半导体部件,并且在所述基板和所述半导体部件之间填充有底部填充树脂,所述半导体装置的特征在于,
在所述基板和所述半导体部件的一方或双方中与所述底部填充树脂接触的区域的一部分具有亲液化处理部,所述亲液化处理部被处理为与所述亲液化处理部的周围的区域部分相比至少对液状的底部填充树脂具有亲液性,
在该亲液化处理部与所述基板和所述半导体部件的一方或双方之间设置有阻焊剂,
所述亲液化处理部的周围的区域部分被覆有阻焊剂,
在所述亲液化处理部,阻焊剂的表面通过离子照射被实施了表面改性,
所述亲液化处理部不包括最外周的焊锡凸块,
在配置有所述亲液化处理部的区域的内侧的区域未被覆有阻焊剂,且在配置有所述亲液化处理部的区域的外侧的区域不存在与所述亲液化处理部分离的其它亲液化处理部。
2.根据权利要求1所述的半导体装置,其特征在于,
所述亲液化处理部被处理为接触角小于所述亲液化处理部的周围的区域部分的接触角。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述亲液化处理部的周围的区域部分与所述亲液化处理部相比,至少对液状的底部填充树脂是疏液性。
4.根据权利要求1或2所述的半导体装置,其特征在于,
所述亲液化处理部的周围的区域部分被覆有阻焊剂,
所述亲液化处理部是通过紫外光曝光被实施了亲液化处理的氧化钛膜。
5.根据权利要求1或2所述的半导体装置,其特征在于,
所述亲液化处理部至少被配置在安装有所述半导体部件的区域的中央部分。
6.根据权利要求5所述的半导体装置,其特征在于,
所述亲液化处理部具有从安装有所述半导体部件的区域的中央部分向外周延伸的一个或多个引导路径。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432751B1 (en) * | 1997-04-11 | 2002-08-13 | Matsushita Electric Industrial Co., Ltd. | Resin mold electric part and producing method therefor |
JP2004179578A (ja) * | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
CN1790653A (zh) * | 2004-11-16 | 2006-06-21 | 精工爱普生株式会社 | 电子元件的装配方法、电子装置的制造方法、电路基板及电子设备 |
CN1967829A (zh) * | 2005-11-16 | 2007-05-23 | 阿尔卑斯电气株式会社 | 电子部件的安装构造 |
CN1967830A (zh) * | 2005-11-16 | 2007-05-23 | 阿尔卑斯电气株式会社 | 电子部件的安装构造以及其安装方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834339A (en) * | 1996-03-07 | 1998-11-10 | Tessera, Inc. | Methods for providing void-free layers for semiconductor assemblies |
JP3712851B2 (ja) * | 1997-04-11 | 2005-11-02 | 松下電器産業株式会社 | 電子部品およびその製造方法 |
JP2004292250A (ja) | 2003-03-27 | 2004-10-21 | Mitsubishi Rayon Co Ltd | 表面改質球状シリカ及びその製造方法及び半導体封止用樹脂組成物 |
JP3854979B2 (ja) | 2004-08-05 | 2006-12-06 | 松下電器産業株式会社 | 電子部品の実装方法及び基板モジュール |
JP4536603B2 (ja) * | 2005-06-09 | 2010-09-01 | 新光電気工業株式会社 | 半導体装置の製造方法及び半導体装置用実装基板及び半導体装置 |
JP4203513B2 (ja) * | 2005-11-16 | 2009-01-07 | アルプス電気株式会社 | 電子部品の実装構造 |
JP4180622B2 (ja) * | 2005-11-16 | 2008-11-12 | アルプス電気株式会社 | 電子部品の実装構造、及びその実装方法 |
JP5331303B2 (ja) * | 2006-11-09 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7687890B2 (en) * | 2007-03-29 | 2010-03-30 | Intel Corporation | Controlling substrate surface properties via colloidal coatings |
-
2008
- 2008-10-09 WO PCT/JP2008/068354 patent/WO2009048097A1/ja active Application Filing
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432751B1 (en) * | 1997-04-11 | 2002-08-13 | Matsushita Electric Industrial Co., Ltd. | Resin mold electric part and producing method therefor |
JP2004179578A (ja) * | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
CN1790653A (zh) * | 2004-11-16 | 2006-06-21 | 精工爱普生株式会社 | 电子元件的装配方法、电子装置的制造方法、电路基板及电子设备 |
CN1967829A (zh) * | 2005-11-16 | 2007-05-23 | 阿尔卑斯电气株式会社 | 电子部件的安装构造 |
CN1967830A (zh) * | 2005-11-16 | 2007-05-23 | 阿尔卑斯电气株式会社 | 电子部件的安装构造以及其安装方法 |
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