JP5331303B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5331303B2 JP5331303B2 JP2006304244A JP2006304244A JP5331303B2 JP 5331303 B2 JP5331303 B2 JP 5331303B2 JP 2006304244 A JP2006304244 A JP 2006304244A JP 2006304244 A JP2006304244 A JP 2006304244A JP 5331303 B2 JP5331303 B2 JP 5331303B2
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- 239000004065 semiconductor Substances 0.000 title claims description 100
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 239000011347 resin Substances 0.000 claims description 77
- 229920005989 resin Polymers 0.000 claims description 77
- 238000000034 method Methods 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 230000001737 promoting effect Effects 0.000 description 24
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
(第1実施形態)
(第2実施形態)
(第3実施形態)
(第4実施形態)
10 実装配線基板
12 ソルダーレジスト
20 半導体チップ
30 アンダーフィル樹脂
40 流入促進部
42 開口部
44 ダム部
52 半田ボール
54 ニードル
P1 塗布開始地点
Claims (12)
- 第1辺を有する矩形の半導体素子を準備すると共に、第1面に形成された絶縁膜及び前記絶縁膜に形成された第1開口を有する配線基板を準備する工程と、
平面視において、前記半導体素子が前記第1開口と重ならず、かつ前記第1辺が前記第1開口に対向するように、前記半導体素子を前記第1面上に配置する工程と、
前記半導体素子と前記配線基板との間隙に樹脂を注入する工程と、
を備え、
前記樹脂を注入する工程において、前記第1面のうち前記第1開口と前記第1辺の間に位置する部分から、前記樹脂の注入を開始し、
前記第1開口は、前記樹脂の塗布が開始される地点を、前記半導体素子と反対の側から囲むように設けられている半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1開口は、平面視で矩形の3辺に沿った形状を有しており、かつ前記矩形の残りの一辺が前記第1辺に対向している半導体装置の製造方法。 - 請求項1又は2に記載の半導体装置の製造方法において、
前記第1開口と前記第1辺の間において、前記樹脂は、前記第1開口、及び前記第1辺の双方に達している半導体装置の製造方法。 - 請求項1〜3のいずれか一つに記載の半導体装置の製造方法において、
平面視において、前記第1開口は前記第1辺の一方の端部の近傍に位置しており、
前記樹脂を注入する工程において、前記樹脂を注入する箇所を、前記第1辺の一方の端部から他方の端部に向かう方向に移動させる半導体装置の製造方法。 - 請求項1〜4のいずれか一つに記載の半導体装置の製造方法において、
前記樹脂を注入する工程において、前記半導体素子の全周にわたってフィレットが形成される半導体装置の製造方法。 - 請求項1〜5のいずれか一つに記載の半導体装置の製造方法において、
前記半導体素子を前記第1面上に配置する工程において、前記半導体素子ははんだを介して前記配線基板に接続される半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記配線基板の前記絶縁膜は、平面視で前記半導体素子と重なる領域に第2開口を有しており、
前記はんだは前記第2開口内で前記配線基板と接続している半導体装置の製造方法。 - 請求項1〜7のいずれか一つに記載の半導体装置の製造方法において、
前記樹脂を注入する工程において、ニードルを用いて前記樹脂を注入する半導体装置の製造方法。 - 請求項1乃至8いずれかに記載の半導体装置の製造方法において、
前記第1開口は、平面視で、円の一部に相当する形状を有し、かつその開放部が前記半導体素子に向いている半導体装置の製造方法。 - 請求項1乃至9いずれかに記載の半導体装置の製造方法において、
前記第1開口は、平面視で、矩形の一部に相当する形状を有し、かつその開放部が前記半導体素子に向いている半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記矩形の前記一部は、当該矩形の2辺である半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記矩形の前記一部は、当該矩形の3辺である半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006304244A JP5331303B2 (ja) | 2006-11-09 | 2006-11-09 | 半導体装置の製造方法 |
US11/936,120 US7759802B2 (en) | 2006-11-09 | 2007-11-07 | Semiconductor device and method for manufacturing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006304244A JP5331303B2 (ja) | 2006-11-09 | 2006-11-09 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008124140A JP2008124140A (ja) | 2008-05-29 |
JP5331303B2 true JP5331303B2 (ja) | 2013-10-30 |
Family
ID=39368444
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006304244A Active JP5331303B2 (ja) | 2006-11-09 | 2006-11-09 | 半導体装置の製造方法 |
Country Status (2)
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US (1) | US7759802B2 (ja) |
JP (1) | JP5331303B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009048097A1 (ja) * | 2007-10-10 | 2009-04-16 | Nec Corporation | 半導体装置 |
JP5117371B2 (ja) * | 2008-12-24 | 2013-01-16 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
JP2011040512A (ja) * | 2009-08-10 | 2011-02-24 | Murata Mfg Co Ltd | 回路基板の製造方法 |
JP2011243612A (ja) | 2010-05-14 | 2011-12-01 | Sony Corp | 半導体装置及びその製造方法並びに電子機器 |
US8193036B2 (en) | 2010-09-14 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming mold underfill using dispensing needle having same width as semiconductor die |
US9054100B2 (en) | 2011-11-01 | 2015-06-09 | Stats Chippac, Ltd. | Semiconductor die and method of forming sloped surface in photoresist layer to enhance flow of underfill material between semiconductor die and substrate |
US10325783B2 (en) * | 2015-06-09 | 2019-06-18 | Infineon Technologies Ag | Semiconductor device including structure to control underfill material flow |
JP6591234B2 (ja) * | 2015-08-21 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11282717B2 (en) | 2018-03-30 | 2022-03-22 | Intel Corporation | Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap |
KR102471275B1 (ko) * | 2019-01-24 | 2022-11-28 | 삼성전자주식회사 | 칩 온 필름(cof) 및 이의 제조방법 |
US11521956B2 (en) | 2020-03-31 | 2022-12-06 | Nichia Corporation | Method of manufacturing light-emitting device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3367886B2 (ja) * | 1998-01-20 | 2003-01-20 | 株式会社村田製作所 | 電子回路装置 |
US6762509B2 (en) * | 2001-12-11 | 2004-07-13 | Celerity Research Pte. Ltd. | Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material |
JP2004349399A (ja) * | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP4536603B2 (ja) * | 2005-06-09 | 2010-09-01 | 新光電気工業株式会社 | 半導体装置の製造方法及び半導体装置用実装基板及び半導体装置 |
-
2006
- 2006-11-09 JP JP2006304244A patent/JP5331303B2/ja active Active
-
2007
- 2007-11-07 US US11/936,120 patent/US7759802B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20080111249A1 (en) | 2008-05-15 |
JP2008124140A (ja) | 2008-05-29 |
US7759802B2 (en) | 2010-07-20 |
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