JPWO2009048097A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JPWO2009048097A1 JPWO2009048097A1 JP2009537021A JP2009537021A JPWO2009048097A1 JP WO2009048097 A1 JPWO2009048097 A1 JP WO2009048097A1 JP 2009537021 A JP2009537021 A JP 2009537021A JP 2009537021 A JP2009537021 A JP 2009537021A JP WO2009048097 A1 JPWO2009048097 A1 JP WO2009048097A1
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- Prior art keywords
- lyophilic
- semiconductor device
- substrate
- underfill resin
- solder resist
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000011347 resin Substances 0.000 claims abstract description 57
- 229920005989 resin Polymers 0.000 claims abstract description 57
- 229910000679 solder Inorganic materials 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 19
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000007788 liquid Substances 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims description 4
- 230000035515 penetration Effects 0.000 description 7
- 238000009825 accumulation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 230000035699 permeability Effects 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 239000002552 dosage form Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000011941 photocatalyst Substances 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract
Description
本発明は、日本国特許出願:特願2007−264369号(2007年10月10日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、基板上にはんだバンプを介して半導体部品を実装した半導体装置に関し、特に、基板と半導体部品の間にアンダーフィル樹脂が充填された半導体装置に関する。
大型でかつ低背化した実装構造部へのアンダーフィル樹脂塗布は、側面から浸透させる場合には全体を均一に塗布することが難しいといった課題がある。
11 パッド
12 配線
13 ビア
14 絶縁層
15 ソルダレジスト
20 半導体部品
21 はんだバンプ
30 親液化処理部
31 誘導路
40 アンダーフィル樹脂
41 空気溜まり
さらに、以下の形態も可能である。
前記親液化処理部は、前記親液化処理部の周囲の領域部分よりも接触角が小さくなるように処理されていることが好ましい(形態2)。
前記親液化処理部の周囲の領域部分は、前記親液化処理部と比較して少なくとも液状のアンダーフィル樹脂と疎液性であることが好ましい(形態3)。
前記親液化処理部の周囲の領域部分は、ソルダーレジストで被覆されており、前記親液化処理部では、ソルダーレジスト上に、紫外光露光により親液化処理された酸化チタン膜が形成されていることが好ましい(形態4)。
前記親液化処理部の周囲の領域部分は、ソルダーレジストで被覆されており、前記親液化処理部では、ソルダーレジストの表面がイオン照射により表面改質されていることが好ましい(形態5)。
前記親液化処理部は、少なくとも前記半導体装置が搭載される領域の中央部分に配置されることが好ましい(形態6)。
前記親液化処理部は、前記半導体装置が搭載される領域の中央部分から外周に延在した一又は複数の誘導路を有することが好ましい(形態7)。
本発明の全開示(請求の範囲を含む)の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。
Claims (7)
- 基板上に半導体部品が搭載されるとともに前記基板と前記半導体部品の間にアンダーフィル樹脂が充填された半導体装置において、
前記基板及び前記半導体部品の一方又は両方において、前記アンダーフィル樹脂と接する領域の一部に、その周囲の領域部分と比較して少なくとも液状のアンダーフィル樹脂と親液性を有するように処理された親液化処理部を有することを特徴とする半導体装置。 - 前記親液化処理部は、前記親液化処理部の周囲の領域部分よりも接触角が小さくなるように処理されていることを特徴とする請求項1記載の半導体装置。
- 前記親液化処理部の周囲の領域部分は、前記親液化処理部と比較して少なくとも液状のアンダーフィル樹脂と疎液性であることを特徴とする請求項1又は2記載の半導体装置。
- 前記親液化処理部の周囲の領域部分は、ソルダーレジストで被覆されており、
前記親液化処理部では、ソルダーレジスト上に、紫外光露光により親液化処理された酸化チタン膜が形成されていることを特徴とする請求項1乃至3のいずれか一に記載の半導体装置。 - 前記親液化処理部の周囲の領域部分は、ソルダーレジストで被覆されており、
前記親液化処理部では、ソルダーレジストの表面がイオン照射により表面改質されていることを特徴とする請求項1乃至3のいずれか一に記載の半導体装置。 - 前記親液化処理部は、少なくとも前記半導体装置が搭載される領域の中央部分に配置されることを特徴とする請求項1乃至5のいずれか一に記載の半導体装置。
- 前記親液化処理部は、前記半導体装置が搭載される領域の中央部分から外周に延在した一又は複数の誘導路を有することを特徴とする請求項6記載の半導体装置。
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PCT/JP2008/068354 WO2009048097A1 (ja) | 2007-10-10 | 2008-10-09 | 半導体装置 |
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JP6225771B2 (ja) * | 2014-03-17 | 2017-11-08 | 株式会社デンソー | 半導体装置およびその製造方法 |
KR101596131B1 (ko) * | 2014-04-25 | 2016-02-22 | 한국과학기술원 | 소수성 표면을 이용한 칩 패키징 방법 및 칩 패키지 |
SG10201508196YA (en) * | 2015-10-02 | 2017-05-30 | Inspiraz Technology Pte Ltd | Processed substrate surface for epoxy deposition and method thereof |
TWI659507B (zh) * | 2018-05-18 | 2019-05-11 | 南茂科技股份有限公司 | 半導體封裝結構及其製造方法 |
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