201007894 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構（package )及用於該封 裝結構的軟質載板（tape carrier / film )，特別是指一種顯示 器（panel display )的驅動積體電路封裝結構（drive 1C package )及用於封裝該驅動積體電路的軟質載板。 【先前技術】 參閱圖1，目前用於平面顯示器（圖未示）的驅動積體 Φ 電路1是電連接於軟質載板2上後，以封裝膠脂4封裝而 成為驅動積體電路封裝結構3，之後’再組裝（assembly) 至平面顯示器的面板（panel，圖未示）上，用以提供電訊 號。 要特別說明的是，以下的說明與圖示均僅以覆晶式封 裝（COF，chip on flip )作說明。 驅動積體電路1具有一電路本體11，及複數主成分是 金且用於與該軟質載板2電連接的凸塊12。 該軟質載板2包含一具有線路圖案211的板本體21， 及複數與線路圖案電連接且可導電的接腳22,每一接腳22 具有一與該板本體21連接且與線路圖案211電連接的内接 部221，及一自該内接部221向外凸伸出的外引部222，該 内接ep 221、外引部222是以主成分是銅的基材223所構成 ，且該外引部222還包覆一層主成分是錫而用於後續銲黏 (bonding)用的鍍層224,該驅動積體電路1的每一凸塊 U是對應地與該軟質載板2的每一接腳22的外引部222相 201007894 兹:黏’並藉著鍍層224 (即業界所稱的銲錫）黏固成一體並 形成電連接。 該封裝膠脂4包覆該軟質載板2的接腳22與部份板本 鱧21 ’及該驅動積體電路丨，使得軟質載板2的接腳22與 部份板本體21 ’及驅動積體電路1與外界相隔絕，而避免 例如水氣的侵蚀。 由於平面顯示器作動時會產生電場，而上述的驅動積 體電路封裝結構3在電場的作用下，軟質載板3接腳22的 銅基材223會解離成鋼離子，而漸次地在封裝膠脂4中穿 過或上、下界面擴散（diffusi〇n)遷移（migrati〇n)獲得電 子析出原子態形成電橋，而讓金、銅形成通路直接擴散而 使兩相鄰的接腳相橋接導通，導致顯示器出現雜線、失效 〇 目前，銅離子遷移現象由於目前顯示器的接腳間距相 對較大（大於35"m)，同時作動時產生的電場強度也不強 、作用時間也不長，所以並不會造成技術上的困擾；但是 當顯示器欲往高階發展時，接腳的間距必然會縮減至35以 m以下，同時作動所產生的電場強度更是倍數增加此時 ，必然極容易、且會在短時間内就發生電遷移現象而導致 顯示器出現雜線、晝質表現降低。 此外，在接腳22外引部222銲黏於主成分是金的凸塊 12上時，難以避免的是金、銅直接接觸而讓少許的銅混入 金中，導致鍍層224 (即業界所稱的銲錫）性質劣化進而 導致連結失效（bonding fail)。 201007894 因此，如何預先防止高階顯示器作動時所產生的強大 的電場作用而導致的電遷移現象，並改善接腳銲黏的良率 與品質’是業界、學界致力改善的努力目標之一。 【發明内容】 因此，本發明之一目的，即在提供一種可以防止銅電 遷移現象發生的用於平面顯示器的驅動積體電路封裝結構 0 此外，本發明之另一目的，即在提供一種可以防止電 遷移現象發生且用於封裝操控平面顯示器之面板（panel) 的驅動積體電路的軟質載板。 於是，本發明一種用於平面顯示器的驅動積體電路封 裝結構，包含一軟質載板、一驅動積體電路，及一封裝膠 脂。 該軟質載板具有一設置有線路圖案的板本體，及複數 分別可導電並與該線路圖案電連接的接腳，每一接腳具有 一與該板本體連接的内接部，及一自該内接部向外凸伸出 該板本體邊緣的外引部，兩相鄰之接腳的外引部間距不大 於35/zm，且該外引部包括一主成分是銅的基材一包覆 該基材以阻擋銅離子向外擴散遷移的第一鍍層，及一設置 在該第一鍍層上的第二鍍層。 該驅動積體電路具有一電路本體，及複數分別與該電 路本體電連接的凸塊，每一接腳的外引部對應地崁黏於每 一凸塊。 該封裝膠脂包覆該載板的接腳與部份板本體，及該驅 201007894 動積體電路。 再者’本發明之一種用於封裝驅動積體電路的軟質載 板’該驅動積體電路用於平面顯示器，該軟質載板包含一 具有一線路圖案的板本體，及複數可導電的接腳，每一接 腳具有與該線路圖案電連接的内接部，及一自該内接部 向外凸伸出該板本體邊緣的外引部，兩相鄰之接腳的外引 部間距不大於35#m，且該外引部包括一主成分是銅的基 材、一包覆該基材以阻播該基材的銅形成銅離子後向外擴 散遷移的第一鍍層，及一設置在該第一鍍層上的第二鍍層 〇 本發明的功效在於：以第一鍍層包覆基材以阻擋基材 的銅形成銅離子後向外擴散，避免未來高階顯示器作動時 所產生的強大的電場作用而導致的電遷移現象。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 · 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中’類似的元件是以相同的編號來表示。 參閲圖2,本發明之用於平面顯示器的驅動積體電路封 裝結構5的一較佳實施例，適用於高階的平面顯示器（圖 未不）中，特別是作動時產生不小於1〇4v/cm強度之電場的 局階平面顯示器；該動積體電路封裝結構5 S將驅動積 體電路1電連接在軟質載板6上，再以封裝膠脂4封裝而 201007894 成’之後再組裝至平面顯示器上用以提供電訊號；要特別 說明的是，以下的說明與圖示均僅以覆晶式封裝（Cop， chip on flip )作說明。 該驅動積體電路1包含一電路本體11，及複數主成分 是金而用於與該軟質載板6電連接的凸塊12，且因應高階 顯示器的需要，凸塊12彼此的間距不大於35ym。 該軟質載板6包含一具有線路圖案611的板本體61， 及複數導電並與線路圖案611電連接的接腳62，每一接聊 ❿ 62具有一與該線路圖案611電連接的内接部621，及一自該 内接部621向外凸伸的外引部622，兩相鄰外引部622的間 距因應高階平面顯示器的設計（即驅動積體電路丨的凸塊 12間距）而不大於35 " m，該内接部621、外引部622主 要都是以主成分是銅的基材623所構成，且該外引部622 還包括一層包覆該基材623周面的第一鍍層624，及一層設 置在該第一鍍層624上而用於後續銲黏的第二鍍層625，該 第二鍍層625的主成分選自於錫、金、含錫的化合物或 籲 含金的化合物，該驅動積體電路1的每一凸塊12是對應地 與該軟質載板6的每一接腳62的外引部622相崁黏，並藉 著第二鍍層625黏固成一體並形成電連接。 該第一鍍層624的厚度需要能在不小於1〇4v/cm的電場 (鬲階平面顯示器運作時產生的電場強度）作用下，阻擋 基材623的銅形成銅離子而向外擴散遷移，在本例中，該 第一鍍層624的鎳含量不低於原子比例5〇% ，且厚度是 Am 5#m，而可在最符合產品結構製程良率與生產成本 201007894 的要求下，得到最佳的阻障效果（barriereffect);另外，該 第一鍍層624的形成方式可以化學鍍方式形成，及/或電鍍 方式形成，且根據發明人長期實驗研究，第一鍍層624除 了防止銅離子的擴散遷移之外，還可防止第二鍍層625 (主 成分疋錫、金、含錫的化合物，或含金的化合物）的劣化 ，且以化學鍍方式形成的第一鍍層624較以電鑛方式形成 的第一鍍層624,在此方面有更佳的表現。 該封裝膠脂4包覆軟質載板6的接腳62與部份板本體 61 ’及該驅動積體電路卜使得軟質載板6的接腳62與部❹ 份板本體61，及驅動積體電路i與外界相隔絕而避免例 如水氣的侵姓。 本發明的驅動積體電路封裝結構5在平面顯示器作動 產生電場時，特別是高階顯示器作動時產生的大電場（不 小於104v/Cm)下，雖然軟質載板6接腳62的銅基材623 會解離成銅離子’但是由於第—鑛層624中的錄對銅而言 有絕佳的阻障效果，所以可以防止銅離子在封裝膠脂4穿 過或上、下界面中擴散遷移’進而使得金、銅形成通路而© 讓兩相鄰的接腳62相橋接導通，導致顯示器出現雜線、畫 質表現降低的現象；此外，第—錢層624還可以避免金、 銅直接接觸而讓少許的銅混入金中，導致第二鐘層624 (即 業界所稱的銲錫）的劣化，改善接腳62銲黏的品質、良率 〇 由上述說明可知，本發明之用於封裳高階平面顯示器 之驅動積體電路的軟質載板6,以及用於平面顯示器的驅動 10 201007894 封裝結構5,主要是以主成分是鎳的第-鍵層624201007894 IX. Description of the Invention: [Technical Field] The present invention relates to a package and a tape carrier/film for the package structure, and more particularly to a panel display The driver 1C package and the soft carrier for packaging the driver integrated circuit. [Prior Art] Referring to Fig. 1, a driving integrated body Φ circuit 1 for a flat panel display (not shown) is electrically connected to a flexible carrier 2, and is packaged by a package adhesive 4 to form a driver integrated circuit package structure. 3, then 'reassemble' onto the panel of the flat panel display (not shown) to provide the electrical signal. In particular, the following description and illustration are only described in the form of a chip on flip (COF). The driving integrated circuit 1 has a circuit body 11 and a plurality of bumps 12 whose principal components are gold and are electrically connected to the flexible carrier 2. The flexible carrier board 2 includes a board body 21 having a line pattern 211, and a plurality of pins 22 electrically connected to the line pattern and electrically conductive. Each of the pins 22 has a connection with the board body 21 and is electrically connected to the line pattern 211. The connecting inner portion 221 and the outer lead portion 222 protruding outward from the inner connecting portion 221, the inner connecting portion 221 and the outer lead portion 222 are formed of a base material 223 whose main component is copper, and The outer lead portion 222 is further coated with a plating layer 224 whose main component is tin for subsequent bonding, and each bump U of the driving integrated circuit 1 is correspondingly associated with the soft carrier 2 The outer lead portion 222 of a pin 22 is 201007894: it is bonded and bonded by a plating layer 224 (known as solder in the industry) to form an electrical connection. The package adhesive 4 covers the pin 22 of the flexible carrier 2 and the partial board 21' and the driving integrated circuit 丨, so that the pin 22 of the flexible carrier 2 and the partial board body 21' and the driving The integrated circuit 1 is isolated from the outside to avoid, for example, moisture attack. Since the electric field is generated when the flat display is actuated, the above-mentioned driving integrated circuit package structure 3 is subjected to an electric field, and the copper substrate 223 of the pin 22 of the soft carrier 3 is dissociated into steel ions, and gradually encapsulated in the resin. 4 through the upper or lower interface diffusion (diffusi〇n) migration (migrati〇n) to obtain electron precipitation atomic state to form a bridge, and let the gold and copper formation channels directly diffuse and bridge the adjacent two adjacent pins The display leads to miscellaneous lines and failures. At present, the copper ion migration phenomenon is relatively large (more than 35 "m), and the electric field strength generated during the operation is not strong, and the action time is not long. It does not cause technical troubles; however, when the display is to be developed to a higher level, the pitch of the pins is inevitably reduced to less than 35 m, and the electric field strength generated by the actuation is multiplied at this time, which is inevitably extremely easy and Electromigration will occur in a short period of time, resulting in miscellaneous lines in the display and reduced performance of the enamel. In addition, when the lead portion 222 of the pin 22 is soldered to the bump 12 whose main component is gold, it is difficult to avoid direct contact between gold and copper to allow a small amount of copper to be mixed into the gold, resulting in the plating layer 224 (known in the industry). The soldering properties deteriorate and lead to bonding failure. 201007894 Therefore, how to prevent the electromigration caused by the strong electric field generated by the high-order display in advance and improve the yield and quality of the pin welding is one of the efforts of the industry and the academic community to improve. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a driver integrated circuit package structure for a flat panel display that can prevent the occurrence of copper electromigration. Furthermore, another object of the present invention is to provide a A soft carrier that prevents electromigration and that is used to package a driver integrated circuit that controls the panel of a flat panel display. Accordingly, the present invention provides a drive integrated circuit package structure for a flat panel display comprising a soft carrier, a driver integrated circuit, and a package adhesive. The flexible carrier board has a board body provided with a line pattern, and a plurality of pins respectively electrically conductive and electrically connected to the line pattern, each pin having an inner connecting portion connected to the board body, and The inner connecting portion protrudes outwardly from the outer lead portion of the edge of the board body, and the distance between the outer lead portions of the two adjacent pins is not more than 35/zm, and the outer lead portion includes a base material with a main component of copper. a first plating layer covering the substrate to block outward diffusion of copper ions, and a second plating layer disposed on the first plating layer. The driving integrated circuit has a circuit body and a plurality of bumps respectively electrically connected to the circuit body, and the outer lead portions of each pin are correspondingly bonded to each of the bumps. The package adhesive covers the pins of the carrier board and a portion of the board body, and the drive circuit of the 201007894. Furthermore, a soft carrier for packaging a driver integrated circuit of the present invention is used for a flat panel display, the flexible carrier includes a board body having a line pattern, and a plurality of conductive pins Each of the pins has an inner portion electrically connected to the line pattern, and an outer lead portion protruding outward from the inner portion of the board body, and the outer lead portions of the two adjacent pins are not spaced apart More than 35#m, and the outer lead portion includes a base material whose main component is copper, a first plating layer which is coated with the base material to block copper of the base material to form copper ions and then diffuse and migrate, and a setting The second plating layer on the first plating layer has the effect of covering the substrate with the first plating layer to block the copper of the substrate to form copper ions and then diffusing outward, so as to avoid the strong generated by the future high-order display actuation. Electromigration caused by the action of an electric field. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 2, a preferred embodiment of the driving integrated circuit package structure 5 for a flat panel display of the present invention is suitable for use in a high-order flat panel display (not shown), and particularly generates no less than 1〇4v when actuated. a local-level flat-panel display of an electric field of /cm intensity; the motor-integrated circuit package structure 5 S electrically connects the integrated integrated circuit 1 to the flexible carrier 6 and is packaged in a package of adhesive 4 and then assembled into 201007894 The flat panel display is used to provide an electrical signal; it should be particularly noted that the following description and illustration are only described by a Cop (chip on flip) package. The driving integrated circuit 1 includes a circuit body 11 and a plurality of bumps 12 whose main components are gold for electrical connection with the soft carrier 6. The spacing of the bumps 12 is not more than 35 μm according to the requirements of the high-order display. . The flexible carrier board 6 includes a board body 61 having a line pattern 611, and a plurality of pins 62 electrically conductive and electrically connected to the line pattern 611. Each of the contacts 62 has an inner portion electrically connected to the line pattern 611. 621, and an outer lead portion 622 protruding outward from the inner connecting portion 621, the spacing of the two adjacent outer lead portions 622 is not in accordance with the design of the high-order flat display (ie, the pitch of the bumps 12 driving the integrated circuit) More than 35 " m, the inner connecting portion 621 and the outer lead portion 622 are mainly composed of a base material 623 whose main component is copper, and the outer lead portion 622 further includes a layer covering the circumferential surface of the base material 623. a plating layer 624, and a second plating layer 625 disposed on the first plating layer 624 for subsequent soldering, the main composition of the second plating layer 625 is selected from tin, gold, tin-containing compounds or gold-containing Each of the bumps 12 of the driving integrated circuit 1 is correspondingly bonded to the outer lead portion 622 of each of the pins 62 of the flexible carrier 6, and is bonded and integrated by the second plating layer 625. Form an electrical connection. The thickness of the first plating layer 624 needs to be able to block the copper of the substrate 623 to form copper ions and diffuse and migrate under the action of an electric field of not less than 1 〇 4 v/cm (the electric field intensity generated when the 平面-plane display is operated). In this example, the nickel content of the first plating layer 624 is not lower than the atomic ratio of 5〇%, and the thickness is Am 5#m, and the best is obtained under the requirement of the product structure process yield and the production cost 201007894. In addition, the formation of the first plating layer 624 may be formed by electroless plating, and/or electroplating, and according to long-term experimental research by the inventors, the first plating layer 624 not only prevents diffusion of copper ions. In addition, deterioration of the second plating layer 625 (main component tin-tin, gold, tin-containing compound, or gold-containing compound) may be prevented, and the first plating layer 624 formed by electroless plating is formed by electro-mineralization. The first plating layer 624 has a better performance in this respect. The encapsulating adhesive 4 encloses the pin 62 of the flexible carrier 6 and the partial plate body 61' and the driving integrated circuit such that the pin 62 of the flexible carrier 6 and the portion of the plate body 61, and the driving assembly The circuit i is isolated from the outside to avoid, for example, the intrusion of moisture. The driving integrated circuit package structure 5 of the present invention generates a large electric field (not less than 104 v/cm) when the flat display is activated to generate an electric field, in particular, a copper substrate 623 of the soft carrier 6 pin 62. Will dissociate into copper ions' but because of the excellent barrier effect of the copper in the first-mine layer 624, it can prevent the copper ions from diffusing and migrating in the encapsulating resin 4 or in the upper and lower interfaces. The gold and copper are formed into a path and the two adjacent pins 62 are bridged and turned on, resulting in a miscellaneous line and a reduced image quality of the display. In addition, the first layer 624 can also avoid direct contact between gold and copper. A small amount of copper is mixed into the gold, resulting in deterioration of the second layer 624 (known as solder in the industry), improving the quality and yield of the soldering of the pin 62. From the above description, the high-order plane of the present invention is used for sealing. The soft carrier board 6 of the display integrated circuit of the display, and the driving structure for the flat panel display 10 201007894 package structure 5, mainly the first-key layer 624 whose main component is nickel
Si 的基材623，而確實可以防止銅離子擴散遷 、生’不但適用於目前的接腳間距相對較大，同時 動時產生的電場強度也不強的平面顯示器中同時 用於未來接腳間距不大☆ 35心、且作動時產生高電場的 高階顯示器中，解決高階顯示器發展的技術瓶頸，確實 到本發明的創作目的。The substrate 623 of Si can prevent the diffusion of copper ions, which is not only suitable for the current pin spacing, but also for the future pin spacing. In the high-order display that is not large ☆ 35 hearts and generates a high electric field when it is activated, the technical bottleneck for solving the development of high-order displays is indeed the purpose of the present invention.
惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一剖視示意圖，說明用於平面顯示器之驅動積 體電路封裝結構；及 圖2是一剖視示意圖，說明本發明用於平面顯示器的 驅動積體電路封裝結構的一較佳實施例。 201007894 【主要元件符號說明】 3 驅動積體電路封 62 接腳 裝結構 621 内接部 4 封裝膠脂 622 外引部 5 驅動積體電路封 623 基材 裝結構 624 第一鍍層 6 軟質載板 625 第二鍍層 61 板本體 611 線路圖案 12The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a package integrated circuit package structure for a flat panel display; and FIG. 2 is a cross-sectional view showing a drive integrated circuit package structure for a flat panel display of the present invention. A preferred embodiment of the invention. 201007894 [Explanation of main component symbols] 3 Driver integrated circuit package 62 Pin mounting structure 621 Inscribed part 4 Package adhesive 622 External lead part 5 Drive integrated circuit seal 623 Substrate mounting structure 624 First plating layer 6 Soft carrier board 625 Second plating layer 61 board body 611 line pattern 12