WO2020137025A1 - Electronic control device - Google Patents

Electronic control device Download PDF

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Publication number
WO2020137025A1
WO2020137025A1 PCT/JP2019/035789 JP2019035789W WO2020137025A1 WO 2020137025 A1 WO2020137025 A1 WO 2020137025A1 JP 2019035789 W JP2019035789 W JP 2019035789W WO 2020137025 A1 WO2020137025 A1 WO 2020137025A1
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WO
WIPO (PCT)
Prior art keywords
solder
porous metal
electronic control
control device
electronic
Prior art date
Application number
PCT/JP2019/035789
Other languages
French (fr)
Japanese (ja)
Inventor
心哉 河喜多
和 平岡
河合　義夫
Original Assignee
日立オートモティブシステムズ株式会社
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Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Publication of WO2020137025A1 publication Critical patent/WO2020137025A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present invention relates to an electronic control device.
  • the electronic control unit includes a semiconductor device having electronic components that generate a large amount of heat.
  • the electronic control device When the electronic control device is downsized, the amount of heat generated per unit area increases, so high heat dissipation and high heat resistance are required.
  • a bonding material for bonding an electronic component that requires heat dissipation to a substrate a porous metal body, and solder filled in the pores of the porous metal body and coated on the surface
  • a high-temperature solder bonding material composed of is known (for example, refer to Patent Document 1).
  • the high temperature solder joint material described in Patent Document 1 is apt to develop cracks in the solder coated on the surface of the porous metal body, and the joint reliability is not sufficient.
  • an electronic control device includes an electronic component, a substrate, and a joining portion that joins the electronic component and the substrate, and the joining portion is a porous metal having continuous pores.
  • a filling portion filled in the pores of the porous metal, at least a part of a region between the electronic component and the porous metal, and at least a part of the substrate and the porous metal.
  • a first solder having a surface joint portion provided in at least one of a region and the electronic component and the substrate, and so as to cover a lateral side of the surface joint portion of the first solder.
  • a second solder which is integrated with a first solder and is thicker than the one surface joint.
  • the progress of cracks that occur in solder can be suppressed and reliability can be improved.
  • FIG. 1 is a side view showing an embodiment of an electronic control device of the present invention.
  • FIG. 2 is an external perspective view of the first embodiment of the semiconductor device of the present invention.
  • 3 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along the line III-III.
  • 4 shows a junction structure which is a main part of the semiconductor device shown in FIG. 3
  • FIG. 4(a) is a plan view of the junction structure seen from above
  • FIG. 4(b) is FIG. 4(a).
  • IVb-IVb line sectional schematic view of FIG. 5 shows a junction structure which is a main part of the semiconductor device of Comparative Example 1.
  • FIG. 5(a) is a plan view of the junction structure seen from above, and FIG. 5(b) is Vb of FIG. 5(a).
  • FIG. 6 is a diagram showing a crack growth rate after a temperature cycle test in the semiconductor devices of Example 1 of the present invention and Comparative Example 1.
  • FIG. 7 is a schematic cross-sectional view of the second embodiment of the junction structure which is the main part of the semiconductor device of the present invention.
  • FIG. 8 is a figure which shows the crack growth rate after the temperature cycle test in the semiconductor device of Example 2 and Comparative Example 1 of this invention.
  • FIG. 9 is a diagram showing average compound thicknesses of semiconductor devices of Example 2 of the present invention and Comparative Example 1.
  • FIG. 10 shows a third embodiment of a junction structure which is a main part of a semiconductor device of the present invention, FIG.
  • FIG. 10(a) is a plan view of the junction structure seen from the upper surface
  • FIG. 10(b) is FIG.
  • FIG. 10A is a schematic sectional view taken along line Xb-Xb of FIG. 10A
  • FIG. 10C is a schematic sectional view taken along line Xc-Xc of FIG.
  • the semiconductor element 1 is transparent, and its outer shape is illustrated by a two-dot chain line.
  • FIG. 11 shows a fourth embodiment of a junction structure which is a main part of a semiconductor device of the present invention
  • FIG. 11(a) is a plan view of the junction structure seen from above
  • FIG. 11(b) is FIG.
  • FIG. 11A is a schematic sectional view taken along line XIb-XIb
  • FIG. 11C is a schematic sectional view taken along line XIc-XIc in FIG. 11A.
  • the semiconductor element 1 is transparent, and its outer shape is shown by a chain double-dashed line.
  • 12A to 12D are process diagrams showing a method for manufacturing a junction structure for a semiconductor device according to the fifth embodiment.
  • FIG. 13 is a diagram showing the void ratios of Example 5 of the present invention and Comparative Example 2.
  • the shapes of the surface joining portions on the upper side and the lower side are simplified to a uniform thickness, ignoring the wavy shape of unevenness and local voids. Is shown.
  • the same reference numerals may be given with different subscripts. However, when it is not necessary to distinguish these plural constituent elements, the subscripts may be omitted in the description.
  • FIG. 1 is a side view showing an embodiment of an electronic control device of the present invention. That is, FIG. 1 is a side view showing a state in which the wiring board 11 housed in the housing (not shown) of the electronic control unit 10 and the connector 12 are connected by soldering.
  • the electronic control unit 10 shown in FIG. 1 is used, for example, for engine control of a vehicle such as an automobile, motor control, automatic transmission control, and the like.
  • the electronic control unit 10 includes a wiring board 11, a semiconductor device 14 such as a microcomputer mounted on the wiring board 11 that generates a large amount of heat, a plurality of electronic components 13 such as a microcomputer and a passive element that generate a small amount of heat, and a connector 12. Is equipped with.
  • the semiconductor device 14 is a package of semiconductor elements such as a microcomputer, a power device, a memory, a system LSI (Large Scale Integration), and an ASIC (Application Specific Integrated Circuit).
  • As the package form for example, QFP (Quad Flat Package) BGA (Ball Grid Array), SOP (Small Outline Package), DIP (Dual Inline Package), LGA (Land Grid Array), QFN (Quad Flat No-Leaded), etc.
  • QFP Quad Flat Package
  • BGA Bit Grid Array
  • SOP Small Outline Package
  • DIP Dual Inline Package
  • LGA Land Grid Array
  • QFN Quad Flat No-Leaded
  • the connection lead 15 of the semiconductor device 14 is bent toward the wiring board 11 side, and further has a tip part bent parallel to the wiring board 11 on the bent tip side.
  • the connection lead 15 is joined to the connection terminal portion (not shown) of the wiring pattern provided on the one surface of the wiring substrate 11 by solder (not shown) at this tip portion
  • the electronic component 13 is soldered with solder 16 to connection terminal portions of a wiring pattern (not shown) provided on both front and back surfaces of the wiring board 11.
  • the wiring board 11 is made of, for example, a glass epoxy material, and may be a single-sided board, a double-sided board, or a multilayer board.
  • the connector 12 includes a plurality of connector pins 12b attached to the connector body 12a.
  • As a material for the connector body 12a PBT (Polybutyleneterephthalate), PPS (Polyphenylene sulfide), or the like is used.
  • a copper alloy such as phosphor bronze or brass is used for the connector pin 12b.
  • FIG. 2 is an external perspective view of the first embodiment of the semiconductor device of the present invention
  • FIG. 3 is a schematic sectional view taken along line III-III of the semiconductor device shown in FIG.
  • the semiconductor device 14 includes a semiconductor element (electronic component) 1, a lead frame 3, a bonding portion 2, a bonding wire 5, and a resin 4.
  • the semiconductor element 1 and the lead frame 3 are joined by the joining portion 2.
  • the connection terminals (not shown) of the semiconductor element 1 are connected to the lead frame 3 by the bonding wires 5.
  • the resin 4 seals the semiconductor element 1, the bonding wire 5, the bonding portion 2, and the lead frame 3.
  • the connecting lead 15 of the lead frame 3 is drawn out of the resin 4. 2 and 3, the external terminal portion exposed from the resin 4 of the lead frame 3 is shown as a flat shape.
  • FIG. 4 shows a junction structure which is a main part of the semiconductor device shown in FIG. 3,
  • FIG. 4A is a plan view of the junction structure seen from above
  • FIG. FIG. 4B is a schematic cross-sectional view taken along the line IVb-IVb of FIG.
  • the lead frame 3 is shown only in the vicinity of the region of the joint 2 to which the semiconductor element 1 is joined.
  • the semiconductor element 1 side will be described as the upper side and the lead frame 3 side as the lower side.
  • the joint structure 30 is composed of the semiconductor element 1, the joint portion 2, and the lead frame 3.
  • the bonding structure 30 is the structure of the semiconductor device 14 excluding the bonding wires 5 and the resin 4.
  • the semiconductor element 1 has a rectangular shape in a plan view.
  • the semiconductor element 1 is, for example, an integrated circuit such as an IGBT (Insulating Gate Bipolar Transistor) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the joint 2 is composed of a porous metal 21 and a solder 22 (see also FIG. 3).
  • the porous metal 21 is a porous metal member formed of copper or nickel and having continuous pores.
  • the porous metal 21 has a stepped prism shape having an upper step portion 21b having a small area facing the semiconductor element 1 and a lower step portion 21a facing the lead frame 3.
  • the upper step portion 21b has a rectangular shape that is smaller than the lower step portion 21a and is substantially the same size as or smaller than the semiconductor element 1 in a plan view.
  • the center of the porous metal 21 is arranged at substantially the same position as the center of the semiconductor element 1.
  • the continuous holes are used in the following meaning. That is, it means that innumerable openings are provided on the surface of the porous metal and communicate with the inside through the openings, and with each of the innumerable holes formed vertically and horizontally inside. Therefore, when the solder material applied to the porous metal is stretched with a squeegee in the solder printing step described later, the solder material is evenly and sufficiently filled from the surface of the porous metal into the pores.
  • the solder 22 is assumed to be composed of a first solder 23 and a second solder 24.
  • the first solder 23 includes solder that fills the pores of the porous metal 21 and solder that covers the surface of the porous metal 21.
  • the second solder 24 is integrated with the first solder 23 so as to cover the entire peripheral side surface of the porous metal 21.
  • the first solder 23 and the second solder 24 are formed by depositing a solder material on the porous metal 21 and its periphery by printing or the like, and putting the solder material in a reflow furnace or the like to heat it.
  • the pores of the porous metal 21 are filled with the solder material, and the solder material is also applied to the front surface and the entire circumference of the side surface of the porous metal 21. In this way, the solder material applied around the porous metal 21 is melted by reflow to form the solder 22.
  • the first solder 23 is provided between the solder (hereinafter referred to as a filling portion) 23 a filled in the pores of the porous metal 21 and the upper surface of the semiconductor element 1 and the upper step portion 21 b of the porous metal 21.
  • solder hereinafter referred to as the upper surface joint portion
  • the solder provided between the lead frame 3 and the lower surface of the lower step portion 21a of the porous metal 21 hereinafter referred to as the lower surface joint portion.
  • 23c the lower surface joint portion
  • the shapes of the upper-side and lower-side surface joining portions 23b and 23c are such that irregular wavy shapes and local voids are ignored.
  • the thickness is shown in a simplified manner.
  • the upper and lower surface joints 23b and 23c are respectively only in a part of the upper surface of the upper step portion 21b of the porous metal 21 or in a part of the lower surface of the lower step portion 21a of the porous metal 21. It may be formed only in the region. Further, only one of the upper surface joint portion 23b and the lower surface joint portion 23c may be formed.
  • the second solder 24 is provided so as to cover the entire peripheral side surface of the porous metal 21 between the semiconductor element 1 and the lead frame 3 in the thickness direction (vertical direction).
  • the peripheral side surface of the second solder 24 is an inclined surface that spreads from the semiconductor element 1 side toward the lead frame 3 side toward the outer peripheral side.
  • the second solder 24 has a shape like a truncated pyramid in which the horizontal cross-sectional area on the peripheral side of the lower step portion 21a of the porous metal 21 is larger than the horizontal cross-sectional area on the peripheral side of the upper step portion 21b. ..
  • the horizontal cross-sectional area is an area of a cross section of the solder 22 taken along a cutting line extending in a direction parallel to the front and back surfaces of the semiconductor device 14.
  • the second solder 24 is integrated with the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23.
  • the second solder 24 integrated with the upper surface joint portion 23b and the upper surface joint portion 23c has a large thickness filled in the entire space between the semiconductor element 1 and the lead frame 3 in the thickness direction.
  • a comparative example there is a structure in which a lead frame and a semiconductor element are joined by a joint portion having only a porous metal in which holes are filled with solder. That is, the structure is such that the solder material is applied only to the entire front surface of the porous metal, the solder material is filled in the pores, and the reflow is performed to perform solder joining.
  • the second solder 24 of the present embodiment is joined by the joining portion that does not have the second solder 24.
  • the solder filled in the pores of the porous metal oozes out on the surface at the time of joining, and between the porous metal and the semiconductor element and/or between the porous metal and the lead frame.
  • a surface joint is formed on the surface.
  • the surface formed between the porous metal and the semiconductor element and between the porous metal and the lead frame is very thin. Therefore, the crack growth rate caused by the strain caused by the load is large, and the life is shortened.
  • the surface joint portion 23b on the upper side and the surface joint portion 23c on the lower side of the first solder 23 having a small thickness are arranged in the thickness direction (vertical direction).
  • the semiconductor element 1 and the lead frame 3 are surrounded and integrated by the second solder 24 having a large thickness provided over the entire area. Therefore, the strain generated at the end portions of the upper surface joint portion 23b of the first solder 23 and the lower surface joint portion 23c of the first solder 23 is suppressed by the second solder 24, and the life is extended.
  • a semiconductor device 14 shown in FIGS. 3 and 4A and 4B was manufactured using the following members.
  • the semiconductor element 1 a 5 mm square Si-MOSFET was used.
  • the lead frame 3 a plate material having a material of C19400 and a thickness of 0.5 mm was used.
  • the bonding wire 5 an Al wire having a diameter of 200 ⁇ m was used.
  • the porous metal 21 a porous metal member made of copper and having continuous voids with a porosity of 80% was used.
  • Sn-10Sb was used as the first solder 23.
  • the porous metal 21 is formed into a stepped prism shape shown in FIGS. 4A and 4B, and the amount of the solder 22 including the amount of the first solder 23 and the amount of the second solder 24 is changed to the porous metal. 21 and the outer periphery thereof.
  • the solder is put into a reflow furnace (not shown) that can be evacuated during melting, and the solder is put into FIGS.
  • a joint structure 30 having the solder 22 having the structure shown was produced.
  • the upper step portion 21b of the porous metal 21 has a rectangular shape which is smaller than the lower step portion 21a in plan view. Therefore, when the solder 22 is put into a reflow furnace and heated to melt the solder 22, the solder 22 follows the shapes of the upper step portion 21b and the lower step portion 21a of the porous metal 21 from the semiconductor element 1 side to the lead frame 3 side. Spreads toward the outer circumference. As a result, the solder 22 is formed in a truncated pyramid shape in which the area on the lead frame 3 side is larger than the area on the semiconductor element 1 side, as shown in FIG. 4B. That is, the solder 22 is formed into the truncated pyramid shape shown in FIG.
  • solder 22 only by applying the solder 22 onto the porous metal 21 and the outer periphery thereof and placing the solder 22 in the reflow furnace.
  • the solder 22 spreads along the size of the outer circumference of the upper step portion 21b and the lower step portion 21a of the porous metal 21, and surrounds the upper step portion 21b of the porous metal 21 and the lower step portion 21a of the porous metal 21.
  • the peripheral side surface is covered and formed thick in the entire thickness direction.
  • the semiconductor element 1 and the lead frame 3 are connected by a bonding wire 5, and the semiconductor element 1, the bonding wire 5, the joint portion 2, and the lead frame 3 are connected to each other by a bonding lead 15 by a resin 4 made of epoxy resin or the like.
  • the semiconductor device 14 shown in FIG. 3 was obtained by sealing so as to expose only the semiconductor device.
  • Comparative Example 1 a semiconductor device (not shown) having the junction structure 30R shown in FIG. 5 was manufactured.
  • 5 shows a junction structure which is an essential part of the semiconductor device of Comparative Example 1
  • FIG. 5A is a plan view of the junction structure which is an essential part of the semiconductor device seen from above
  • FIG. FIG. 6 is a schematic sectional view taken along line Vb-Vb of FIG.
  • the joint structure 30R of Comparative Example 1 includes the semiconductor element 1, the joint portion 2r, and the lead frame 3.
  • the structures and materials of the semiconductor element 1 and the lead frame 3 of Comparative Example 1 are the same as those of the semiconductor element 1 and the lead frame 3 of Example 1, respectively.
  • the structure and material of the part of the semiconductor device shown as Comparative Example 1 excluding the junction structure 30R are the same as the structure and material of the part of the semiconductor device 14 of the present embodiment excluding the junction structure 30. That is, the semiconductor device of Comparative Example 1 is different from the semiconductor device 14 of the present embodiment having the junction 2 only in having the junction 2r.
  • the joint portion 2r of Comparative Example 1 has the porous metal 21r and the first solder 23.
  • the porous metal 21r has substantially the same plane size as the semiconductor element 1, and is formed in a prismatic shape having a rectangular cross section with the same area over the entire thickness direction (vertical direction).
  • the joint portion 2r has only the first solder 23 and does not have the second solder 24.
  • the first solder 23 is provided between the filling portion 23a filled in the pores of the porous metal 21r and the upper surface of the semiconductor element 1 and the upper surface of the porous metal 21 as in the bonding structure 30 of the above embodiment. It has an upper surface joint 23b and a lower surface joint 23c provided between the lead frame 3 and the lower surface of the porous metal 21.
  • the materials and other structures of the semiconductor device of Comparative Example 1 are all the same as in Example 1.
  • FIG. 6 is a diagram showing the crack growth rates after the temperature cycle test in the semiconductor devices of Example 1 of the present invention and Comparative Example 1.
  • the crack growth rate is in the cross section below the diagonal line of the semiconductor element 1.
  • the crack growth rate of the semiconductor device of Comparative Example 1 was 70%, and the crack growth rate of the semiconductor device 14 of Example 1 was 59%. This confirmed that the semiconductor device 14 of Example 1 had a smaller crack growth rate than the semiconductor device of Comparative Example 1.
  • the second solder 24 is illustrated as a structure provided over the entire circumference of the porous metal 21 between the semiconductor element 1 and the lead frame 3 in the thickness direction.
  • the second solder 24 may be provided over the entire area between the semiconductor element 1 and the lead frame 3 in the thickness direction in a partial region of the outer periphery of the porous metal 21.
  • the electronic control device 10 includes a semiconductor element (electronic component) 1, a lead frame (substrate) 3, and a joint portion 2.
  • the joint portion 2 has a porous metal 21, a first solder 23, and a second solder 24.
  • the first solder 23 includes a filling portion 23 a filled in the holes of the porous metal 21, at least a partial region between the semiconductor element 1 and the porous metal 21, the lead frame 3 and the porous metal 21.
  • a surface bonding portion 23b or 23c provided in at least one of at least a part of the area between and.
  • the second solder 24 is thicker than either the surface joint portion 23b or 23c of the first solder 23.
  • the second solder 24 having a large thickness is integrated with the surface joints 23b and 23c of the first solder 23 having a small thickness, the surface joints 23b and 23c of the first solder 23 are formed to be integrated.
  • the growth of cracks can be suppressed, the reliability of the semiconductor device 14 can be improved, and the life can be extended.
  • FIG. 7 is a schematic cross-sectional view of the second embodiment of the junction structure which is the main part of the semiconductor device of the present invention.
  • the bonding structure 30 of the second embodiment differs from that of the first embodiment in that a nickel (Ni) plating layer 7 is provided on the surface of the lead frame 3 facing the porous metal 21.
  • the lead frame 3 was a plate material having a material of C19400 and a thickness of 0.5 mm, and the nickel plating layer 7 was formed by electroless plating to a thickness of 3 ⁇ m.
  • the joint structure 30 of the second embodiment is the same as the joint structure 30 of the first embodiment in terms of materials and other configurations except that the nickel plating layer 7 is formed on one surface of the lead frame 3.
  • FIG. 8 is a diagram showing the crack growth rate after the temperature cycle test in the semiconductor devices of Example 2 of the present invention and Comparative Example 1.
  • the crack growth rate of the semiconductor device of Comparative Example 1 was 70%, and the crack growth rate of the semiconductor device 14 of Example 2 was 56%.
  • the semiconductor device 14 of Example 2 also had a smaller crack growth rate than the semiconductor device of Comparative Example 1.
  • the semiconductor device 14 of Example 2 has a smaller crack growth rate than the semiconductor device 14 of Example 1.
  • Example 2 When Sn or Sn alloy is bonded to the lead frame 3 made of Cu as in Example 1 and Comparative Example 1, Cu—Sn compound which is an intermetallic compound is formed at the interface between Cu and Sn or Sn alloy. ..
  • Example 2 in which the nickel plating layer 7 is formed on one surface of the lead frame 3, the formation of the Cu—Sn compound is prevented by the nickel plating layer 7, and the nickel plating layer 7 is formed at the interface between the nickel plating layer 7 and Sn or Sn alloy. A Ni-Sn compound is formed.
  • FIG. 9 is a diagram showing the average compound thickness of the semiconductor devices of Example 2 of the present invention and Comparative Example 1.
  • the average compound thicknesses of Example 2 and Comparative Example 1 are at the interface between the lead frame 3 and the end portion side of the joint portion 2.
  • the average compound thickness of Example 2 was 15 ⁇ m, which was smaller than the average compound thickness of 26 ⁇ m of Comparative Example 1. Since the intermetallic compound is harder and more brittle than solder, which is made of Sn or Sn alloy, the thicker the thickness thereof, the easier the cracks grow.
  • the example 2 in which the nickel plating layer 7 is formed between the lead frame 3 and the solder 22 is the first solder more than the comparative example 1 in which the nickel plating layer 7 is not formed between the lead frame 3 and the solder 22. It was confirmed that the crack growth rate of the surface bonding portions 23b and 23c of No. 23 was reduced and the life could be extended.
  • the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23 having a small thickness have the semiconductor element 1 and the lead frame 3 in the thickness direction. It is covered with the second solder 24 having a large thickness and filled in the entire space. Therefore, also in the second embodiment, the same effect as that of the first embodiment is obtained. Further, in the second embodiment, the nickel plating layer 7 formed on the one surface of the lead frame 3 prevents the formation of a hard and brittle Cu—Sn compound. Therefore, the crack growth rate is further reduced.
  • FIG. 10 shows a third embodiment of a junction structure which is a main part of a semiconductor device of the present invention
  • FIG. 10(a) is a plan view seen from the upper surface of the junction
  • FIG. 10(b) is 10A is a schematic sectional view taken along line Xb-Xb in FIG. 10A
  • FIG. 10C is a schematic sectional view taken along line Xc-Xc in FIG. 10A.
  • the semiconductor element 1 is transparent, and its outer shape is illustrated by a two-dot chain line.
  • the porous metal 21 has an octagonal shape in a plan view in which the triangular regions 24a of the four corner portions 44 of the rectangular body are removed. That is, the porous metal 21 has an octagonal shape having a pair of long sides 41, a pair of short sides 42, and four oblique sides 43. The porous metal 21 has substantially the same cross-sectional area over the entire thickness direction and has an octagonal prism shape.
  • Each of the long sides 41 of the porous metal 21 is arranged at a position substantially overlapping with each of the long sides of the semiconductor element 1, and each of the short sides 42 of the porous metal 21 is at a position substantially overlapping with each of the short sides of the semiconductor element 1. It is located in. Therefore, the second solder 24 that covers the entire circumference of the peripheral surface of the porous metal 21 is also formed in the triangular region 24 a at each corner portion 44 of the porous metal 21, and is filled up to the inner side in contact with the hypotenuse 43.
  • the third embodiment in a plan view surrounded by the long sides of the semiconductor element 1, the short sides of the semiconductor element 1, and the oblique sides of the porous metal 21 in the four corner portions 44, as compared with the first embodiment.
  • the area of the second solder 24 region is large only in the triangular region 24a.
  • the other configuration for joining the solder and the electronic component is the same as that of the first embodiment, and the first solder 23 is filled in the pores of the porous metal 21.
  • the second solder 24 is integrated with the upper surface joint portion 23 b of the first solder 23 and the lower surface joint portion 23 c of the first solder 23. Therefore, also in the third embodiment, the same effect as that of the first embodiment is obtained.
  • the area of the triangular region 24a in plan view has an area of bonding with the surface bonding portions 23b and 23c on the upper and lower sides of the first solder 23 more than that of the first embodiment. Since it is large, there is a possibility that crack propagation of the surface joint portions 23b and 23c of the first solder 23 can be suppressed more than in the first embodiment.
  • the corner portion 44 of the semiconductor element 1 is distorted more than other regions.
  • the triangular region 24a filled with the second solder 24 is provided in the corner portion 44 of the semiconductor element 1 where large strain occurs. Therefore, according to the third embodiment, even when a large load is applied to the corner portion 44 of the semiconductor element 1, the crack growth rate of the surface joint portions 23b and 23c of the first solder 23 can be reduced. ..
  • the porous metal 21 is illustrated as an octagonal prism shape having substantially the same cross-sectional area over the entire thickness direction, which is the vertical direction.
  • the porous metal 21 in the third embodiment may have a stepped prism shape in which the plane size of the lower step portion 21a is larger than the plane size of the upper step portion 21b, as in the first embodiment.
  • the porous metal 21 is illustrated as an octagonal shape in plan view in which the four corners of the rectangular body are removed in plan view.
  • the porous metal 21 may be a member having a pentagonal or more polygonal shape obtained by removing one or more corners of a rectangular body in a plan view, or may be a long side of the semiconductor element 1 and a short side of the semiconductor element 1 in a plan view. It may be a member having a circle or an elliptical shape that is substantially in contact with at least one side. Even in the case of this structure, the second solder 24 is filled in the region corresponding to the corner portion 44 of the rectangular semiconductor element 1.
  • FIG. 11 shows a fourth embodiment of the junction structure which is the main part of the semiconductor device of the present invention
  • FIG. 11(a) is a plan view of the junction structure seen from above
  • FIG. 11(b) is 11A is a schematic sectional view taken along line XIb-XIb of FIG. 11A
  • FIG. 11C is a schematic sectional view taken along line XIc-XIc of FIG. 11A.
  • the semiconductor element 1 is transparent, and its outer shape is shown by a chain double-dashed line.
  • the porous metal 21 is provided only in the regions corresponding to the four corners of the rectangular semiconductor element 1 in plan view. That is, the porous metal 21 has the first side along the long side of the semiconductor element 1, the second side along the short side of the semiconductor element 1, and the third side which is the oblique side connecting the first side and the second side. It has four porous metal members 26a-26d having a right triangle shape with and.
  • the porous metal members 26a to 26d are arranged apart from each other, and the second solder 24 is formed inside and outside each of the porous metal members 26a to 26d.
  • each of the porous metal members 26a to 26d has a filling portion 23a in which the first solder 23 is filled in the pores.
  • a surface joint portion 23b on the upper side of the first solder 23 is provided between the upper surface of each porous metal member 26a to 26d and the semiconductor element 1, and the lower surface of each porous metal member 26a to 26d and the lead.
  • a surface joint 23c on the lower side of the first solder 23 is provided between the frame 3 and the frame 3.
  • the second solder 24 is integrated with the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23.
  • the surface joint portions 23b and 23c of the first solder 23 are connected by the second solder 24 having a large thickness. Therefore, similarly to the first embodiment, the cracks in the surface joint portions 23b and 23c of the first solder 23 are suppressed from growing, and the reliability of the semiconductor device 14 can be improved.
  • the fourth embodiment may have a structure in which the nickel plating layer 7 is formed on one surface of the lead frame 3 as in the second embodiment. Since the formation of the Cu—Sn compound is prevented by the nickel plating layer 7, the crack growth rate of the surface joint portions 23b and 23c of the first solder 23 is further reduced, and the life can be extended.
  • the porous metal members 26a to 26d may be formed as one member integrated by the connecting portion, and may have a through hole penetrating in the thickness direction at the central portion.
  • Embodiment- 12A to 12D are process drawings showing the method for manufacturing the junction structure of the semiconductor device according to the fifth embodiment.
  • a method of manufacturing the junction structure 30 of the semiconductor device 14 will be described with reference to FIGS.
  • the first solder 23 and the second solder 24 are formed by using the same material.
  • a stepped prismatic porous metal 21 having an upper step portion 21 b and a lower step portion 21 a is formed in advance, and this porous metal 21 is mounted on the lead frame 3. ..
  • a mask 51 having an opening 52 of a plane size slightly larger than the lower step portion 21a of the porous metal 21 is arranged on the porous metal 21, and printing is performed using a squeegee 53. Then, the flux-containing solder 22A in which the flux is mixed with the first solder 23 (or the second solder 24) is applied to the upper surface and the outer periphery of the porous metal 21.
  • the mask 51 is removed and the semiconductor element 1 is mounted on the porous metal 21.
  • the opening 52 of the mask 51 is formed to have substantially the same size as the plane size of the semiconductor element 1, and is aligned so that the outer peripheral side surface of the semiconductor element 1 coincides with the outer peripheral side surface of the flux-containing solder 22A.
  • the flux-containing solder 22A is put into a reflow furnace in an N 2 atmosphere and heated to melt and solidify the flux-containing solder 22A, thereby producing the joint structure 30 shown in FIG.
  • the joint structure 30 of FIG. 12D is the same structure as the joint structure 30 of FIG. 4B.
  • the semiconductor element 1 and the lead frame 3 are connected by the bonding wire 5 and the semiconductor element 1, the bonding wire 5, the bonding portion 2 and the lead frame 3 are connected, although not shown.
  • the semiconductor device 14 is manufactured by encapsulating so that only the lead 15 for use is exposed.
  • Example 5 A semiconductor device 14 of Example 5 was manufactured by the method described in FIGS. 12(a) to 12(d) above.
  • the junction structure 30 of the semiconductor device 14 of Example 5 is the same as that of Example 1 except that the solder 22 of Example 1 is replaced with the flux-containing solder 22A, and the porous metal 21 has a porosity of 80%. It is made of copper.
  • Comparative Example 2 As Comparative Example 2, the semiconductor device of Comparative Example 2 was manufactured using the same manufacturing method as that of the semiconductor device of Example 5 except that the porous metal 21 was formed of copper having a porosity of 20%. (Not shown) was prepared.
  • FIG. 13 is a diagram showing the void ratios of Example 5 of the present invention and Comparative Example 2. Note that FIG. 13 also shows the void ratio when the porous metal 21 is not used. As shown in FIG. 13, the void ratio of the joint of the structure of Comparative Example 2 in which the porosity was 20% and the Cu network was dense was higher than the void ratio of the joint not containing the porous metal 21. On the other hand, the void ratio of the joint portion of the structure of Example 5 was equivalent to the void ratio of the joint portion not including the porous metal 21. From this result, it is confirmed that the void ratio tends to decrease as the porosity of the porous metal 21 increases.
  • the void rate of the porous metal 21 having a porosity of 30% or more is smaller than the void rate of 25% when the porosity of the porous metal 21 is 20%.
  • This void ratio has no problem in practical use. Therefore, in each of the embodiments, by using the porous metal 21 having a porosity of 30% or more, the effect of suppressing the growth of cracks in the surface joint portions 23b and 23c of the first solder 23 and the occurrence of void ratio are obtained. It is possible to achieve both the effect of suppressing
  • the skeleton of a porous metal having a porosity of 20% is thicker and has a larger heat capacity than the skeleton of a porous metal having a porosity of 80%.
  • the structure in which the metal lead frame 3 is used as the supporting member that supports the semiconductor element 1 is illustrated.
  • a circuit board provided with a wiring pattern or a connection pad, or a board such as an insulating board can be used.
  • the second solder 24 is illustrated as a structure having a large thickness filled in the entire space between the semiconductor element 1 and the lead frame 3 in the thickness direction which is the vertical direction.
  • the second solder 24 is connected to at least one of the upper and lower surface joints 23b and 23c, and may be formed thicker than the surface joints 23b and 23c. The entire space between the semiconductor element 1 and the lead frame 3 may not be filled.
  • the first solder 23 and the second solder 24 are exemplified as the solder made of the same material.
  • the first solder 23 and the second solder 24 may be solders made of different materials.
  • the second solder 24 is made porous by printing or the like. It may be applied on the outer surface of the high-quality metal 21 and put into reflow or the like to melt and solidify.

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Abstract

This electronic device is provided with: an electronic component; a substrate; and a joining part for joining the electronic component to the substrate. The joining part contains: a porous metal which has continuous pores; first solder which has filling parts filling the pores of the porous metal and a surface joining part provided to at least a portion of a region between the electronic component and the porous metal and/or at least a portion of a region between the substrate and the porous metal; and second solder that is thicker than the surface joining part, that is provided between the electronic component and the substrate, and that is integrated with the first solder so as to cover lateral sides of the surface joining part of the first solder.

Description

電子制御装置Electronic control unit
　本発明は、電子制御装置に関する。 The present invention relates to an electronic control device.
　電子制御装置は、発熱量が大きい電子部品を有する半導体デバイスを含んでいる。電子制御装置を小型化すると単位面積当たりの発熱量が増加するため、高放熱化および高耐熱化が求められる。この種の電子制御装置では、放熱が必要な電子部品を基板に接合する接合材として、多孔質金属体と、該多孔質金属体の空孔部分に充填され、かつ表面に被覆されたはんだとから構成される高温はんだ接合材が知られている（例えば、特許文献１参照）。 The electronic control unit includes a semiconductor device having electronic components that generate a large amount of heat. When the electronic control device is downsized, the amount of heat generated per unit area increases, so high heat dissipation and high heat resistance are required. In this type of electronic control device, as a bonding material for bonding an electronic component that requires heat dissipation to a substrate, a porous metal body, and solder filled in the pores of the porous metal body and coated on the surface A high-temperature solder bonding material composed of is known (for example, refer to Patent Document 1).
日本国特開２０１２－３５２９１号公報Japanese Patent Laid-Open No. 2012-35291
　特許文献１に記載された高温はんだ接合材は、多孔質金属体の表面に被覆されたはんだに亀裂が進展し易く、接合の信頼性が十分でない。 The high temperature solder joint material described in Patent Document 1 is apt to develop cracks in the solder coated on the surface of the porous metal body, and the joint reliability is not sufficient.
　本発明の一態様によると、電子制御装置は、電子部品と、基板と、前記電子部品と前記基板を接合する接合部とを備え、前記接合部は、連続する空孔を有する多孔質金属と、前記多孔質金属の前記空孔に充填された充填部、前記電子部品と前記多孔質金属との間の少なくとも一部の領域と、前記基板と前記多孔質金属との間の少なくとも一部の領域との少なくとも一方に設けられた表面接合部とを有する第１のはんだと、前記電子部品と前記基板間に設けられ、前記第１のはんだの前記表面接合部の側方側を覆うように第１のはんだと一体化された、前記一方の前記表面接合部より厚い第２のはんだと、を含む。 According to one aspect of the present invention, an electronic control device includes an electronic component, a substrate, and a joining portion that joins the electronic component and the substrate, and the joining portion is a porous metal having continuous pores. A filling portion filled in the pores of the porous metal, at least a part of a region between the electronic component and the porous metal, and at least a part of the substrate and the porous metal. A first solder having a surface joint portion provided in at least one of a region and the electronic component and the substrate, and so as to cover a lateral side of the surface joint portion of the first solder. A second solder which is integrated with a first solder and is thicker than the one surface joint.
　本発明によれば、はんだに生じるき裂の進展が抑制され、信頼性を向上することができる。 According to the present invention, the progress of cracks that occur in solder can be suppressed and reliability can be improved.
図１は、本発明の電子制御装置の一実施の形態を示す側面図。FIG. 1 is a side view showing an embodiment of an electronic control device of the present invention. 図２は、本発明の半導体デバイスの第１の実施形態の外観斜視図。FIG. 2 is an external perspective view of the first embodiment of the semiconductor device of the present invention. 図３は、図２に図示された半導体デバイスのＩＩＩ－ＩＩＩ線断面図。3 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along the line III-III. 図４は、図３に図示された半導体デバイスの要部である接合構造を示し、図４（ａ）は、接合構造を上方からみた平面図、図４（ｂ）は、図４（ａ）のＩＶｂ－ＩＶｂ線断面模式図。4 shows a junction structure which is a main part of the semiconductor device shown in FIG. 3, FIG. 4(a) is a plan view of the junction structure seen from above, and FIG. 4(b) is FIG. 4(a). IVb-IVb line sectional schematic view of FIG. 図５は、比較例１の半導体デバイスの要部である接合構造を示し、図５（ａ）は、接合構造を上方からみた平面図、図５（ｂ）は、図５（ａ）のＶｂ－Ｖｂ線断面模式図。5 shows a junction structure which is a main part of the semiconductor device of Comparative Example 1. FIG. 5(a) is a plan view of the junction structure seen from above, and FIG. 5(b) is Vb of FIG. 5(a). -Vb line sectional schematic diagram. 図６は、本発明の実施例１と比較例１の半導体デバイスにおける、温度サイクル試験後のき裂進展率を示す図。FIG. 6 is a diagram showing a crack growth rate after a temperature cycle test in the semiconductor devices of Example 1 of the present invention and Comparative Example 1. 図７は、本発明の半導体デバイスの要部である接合構造の第２の実施形態の断面模式図。FIG. 7 is a schematic cross-sectional view of the second embodiment of the junction structure which is the main part of the semiconductor device of the present invention. 図８は、本発明の実施例２と比較例１の半導体デバイスにおける、温度サイクル試験後のき裂進展率を示す図。FIG. 8: is a figure which shows the crack growth rate after the temperature cycle test in the semiconductor device of Example 2 and Comparative Example 1 of this invention. 図９は、本発明の実施例２と比較例１の半導体デバイスの平均化合物厚さを示す図。FIG. 9 is a diagram showing average compound thicknesses of semiconductor devices of Example 2 of the present invention and Comparative Example 1. 図１０は、本発明の半導体デバイスの要部である接合構造の第３の実施形態を示し、図１０（ａ）は、接合構造を上面からみた平面図、図１０（ｂ）は、図１０（ａ）のＸｂ－Ｘｂ線断面模式図、図１０（ｃ）は、図１０（ａ）のＸｃ－Ｘｃ線断面模式図。なお、図１０（ａ）では、半導体素子１を透明とし、その外形を二点鎖線により図示している。FIG. 10 shows a third embodiment of a junction structure which is a main part of a semiconductor device of the present invention, FIG. 10(a) is a plan view of the junction structure seen from the upper surface, and FIG. 10(b) is FIG. FIG. 10A is a schematic sectional view taken along line Xb-Xb of FIG. 10A, and FIG. 10C is a schematic sectional view taken along line Xc-Xc of FIG. In addition, in FIG. 10A, the semiconductor element 1 is transparent, and its outer shape is illustrated by a two-dot chain line. 図１１は、本発明の半導体デバイスの要部である接合構造の第４の実施形態を示し、図１１（ａ）は、接合構造を上面からみた平面図、図１１（ｂ）は、図１１（ａ）のＸＩｂ－ＸＩｂ線断面模式図、図１１（ｃ）は、図１１（ａ）のＸＩｃ－ＸＩｃ線断面模式図。なお、図１１（ａ）では、半導体素子１を透明とし、その外形を二点鎖線で示している。FIG. 11 shows a fourth embodiment of a junction structure which is a main part of a semiconductor device of the present invention, FIG. 11(a) is a plan view of the junction structure seen from above, and FIG. 11(b) is FIG. 11A is a schematic sectional view taken along line XIb-XIb, and FIG. 11C is a schematic sectional view taken along line XIc-XIc in FIG. 11A. Note that, in FIG. 11A, the semiconductor element 1 is transparent, and its outer shape is shown by a chain double-dashed line. 図１２（ａ）～（ｄ）は、第５の実施形態の半導体デバイスの接合構造の製造方法を示す工程図。12A to 12D are process diagrams showing a method for manufacturing a junction structure for a semiconductor device according to the fifth embodiment. 図１３は、本発明の実施例５と比較例２のボイド率を示す図である。FIG. 13 is a diagram showing the void ratios of Example 5 of the present invention and Comparative Example 2.
　以下、図面を参照して本発明の実施形態を説明する。以下の記載および図面は、本発明を説明するための例示であって、説明の明確化のため、適宜、省略および簡略化がなされている。本発明は、他の種々の形態でも実施する事が可能である。特に限定しない限り、各構成要素は単数でも複数でも構わない。
　図面において示す各構成要素の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面に開示された位置、大きさ、形状、範囲などに限定されない。特に、各実施形態における接合構造の断面模式図では、上部側および下部側の表面接合部の形状は、凹凸の波打ち形状や、局所的な空隙等を無視して、均一な厚さに簡素化して示している。
　同一あるいは同様な機能を有する構成要素が複数ある場合には、同一の符号に異なる添字を付して説明する場合がある。ただし、これらの複数の構成要素を区別する必要がない場合には、添字を省略して説明する場合がある。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description and the drawings are examples for explaining the present invention, and are appropriately omitted and simplified for the sake of clarity of the description. The present invention can be implemented in various other modes. Unless otherwise specified, each component may be singular or plural.
The position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc., for easy understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings. In particular, in the schematic cross-sectional views of the joining structure in each embodiment, the shapes of the surface joining portions on the upper side and the lower side are simplified to a uniform thickness, ignoring the wavy shape of unevenness and local voids. Is shown.
When there are a plurality of constituent elements having the same or similar functions, the same reference numerals may be given with different subscripts. However, when it is not necessary to distinguish these plural constituent elements, the subscripts may be omitted in the description.
－第１の実施形態－
　以下、図１～図６を参照して、本発明の第１の実施形態を説明する。
　図１は、本発明の電子制御装置の一実施の形態を示す側面図である。すなわち、図１は、電子制御装置１０の筐体（図示せず）内に収納された配線基板１１とコネクタ１２とをはんだ付けにより接続した状態を示す側面図である。
　図１に図示された電子制御装置１０は、例えば、自動車等の車両のエンジン制御、モータ制御、自動変速機制御等に用いられる。電子制御装置１０は、配線基板１１と、配線基板１１上に実装されたマイコン等の発熱量が大きい半導体デバイス１４、およびマイコンや受動素子などの発熱量が小さい複数の電子部品１３、およびコネクタ１２を備えている。 -First embodiment-
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a side view showing an embodiment of an electronic control device of the present invention. That is, FIG. 1 is a side view showing a state in which the wiring board 11 housed in the housing (not shown) of the electronic control unit 10 and the connector 12 are connected by soldering.
The electronic control unit 10 shown in FIG. 1 is used, for example, for engine control of a vehicle such as an automobile, motor control, automatic transmission control, and the like. The electronic control unit 10 includes a wiring board 11, a semiconductor device 14 such as a microcomputer mounted on the wiring board 11 that generates a large amount of heat, a plurality of electronic components 13 such as a microcomputer and a passive element that generate a small amount of heat, and a connector 12. Is equipped with.
　半導体デバイス１４は、マイコンやパワーデバイス、メモリ、システムＬＳＩ（Large Scale Integration）、ＡＳＩＣ（Application Specific Integrated Circuit）などの半導体素子をパッケージ形態としたものである。パッケージ形態としては、例えば、ＱＦＰ（Quad Flat Package）ＢＧＡ(Ball Grid Array)、ＳＯＰ(Small Outline Package)、ＤＩＰ(Dual Inline Package)、ＬＧＡ(Land Grid Array)、ＱＦＮ(Quad Flat No-Leaded)などがある。半導体デバイス１４の接続用リード１５は、配線基板１１側に向けて屈曲され、さらに屈曲された先端側に配線基板１１と平行に屈曲された先端部を有している。接続用リード１５は、この先端部において、配線基板１１の一面に設けられた配線パターンの接続端子部（図示せず）にはんだ（図示せず）により接合されている。 The semiconductor device 14 is a package of semiconductor elements such as a microcomputer, a power device, a memory, a system LSI (Large Scale Integration), and an ASIC (Application Specific Integrated Circuit). As the package form, for example, QFP (Quad Flat Package) BGA (Ball Grid Array), SOP (Small Outline Package), DIP (Dual Inline Package), LGA (Land Grid Array), QFN (Quad Flat No-Leaded), etc. There is. The connection lead 15 of the semiconductor device 14 is bent toward the wiring board 11 side, and further has a tip part bent parallel to the wiring board 11 on the bent tip side. The connection lead 15 is joined to the connection terminal portion (not shown) of the wiring pattern provided on the one surface of the wiring substrate 11 by solder (not shown) at this tip portion.
　電子部品１３は、はんだ１６により、配線基板１１の表裏両面に設けられた、図示しない配線パターンの接続端子部にはんだ付けされている。
　配線基板１１は、例えば、ガラスエポキシ材料等からなり、片面、両面、多層基板のいずれでもよい。
　コネクタ１２は、コネクタ本体１２ａに取り付けられた複数のコネクタピン１２ｂを備えている。コネクタ本体１２ａの材料としては、ＰＢＴ（Polybutyleneterephthalate）、ＰＰＳ（Polyphenylene sulfide）などが使用される。また、コネクタピン１２ｂには、りん青銅や黄銅などの銅合金を使用する。はんだの接合強度を高めるために、コネクタピン１２ｂ表面にはニッケル(Ｎｉ)めっき、錫（Ｓｎ）めっきなどを施すことが好ましい。 The electronic component 13 is soldered with solder 16 to connection terminal portions of a wiring pattern (not shown) provided on both front and back surfaces of the wiring board 11.
The wiring board 11 is made of, for example, a glass epoxy material, and may be a single-sided board, a double-sided board, or a multilayer board.
The connector 12 includes a plurality of connector pins 12b attached to the connector body 12a. As a material for the connector body 12a, PBT (Polybutyleneterephthalate), PPS (Polyphenylene sulfide), or the like is used. A copper alloy such as phosphor bronze or brass is used for the connector pin 12b. In order to increase the joint strength of the solder, it is preferable to apply nickel (Ni) plating, tin (Sn) plating or the like to the surface of the connector pin 12b.
　図２は、本発明の半導体デバイスの第１の実施形態の外観斜視図であり、図３は、図２に図示された半導体デバイスのＩＩＩ－ＩＩＩ線断面模式図である。
　半導体デバイス１４は、半導体素子（電子部品）１と、リードフレーム３と、接合部２と、ボンディングワイヤ５と、樹脂４とを備えている。
　半導体素子１とリードフレーム３とは接合部２により接合されている。半導体素子１の接続端子（図示せず）は、ボンディングワイヤ５によりリードフレーム３に接続されている。樹脂４は、半導体素子１と、ボンディングワイヤ５と、接合部２と、リードフレーム３を封止する。但し、リードフレーム３の接続用リード１５は、樹脂４の外部に引き出されている。なお、図２、図３において、リードフレーム３の樹脂４から露出した外部端子部は、平坦状として図示されている。 2 is an external perspective view of the first embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic sectional view taken along line III-III of the semiconductor device shown in FIG.
The semiconductor device 14 includes a semiconductor element (electronic component) 1, a lead frame 3, a bonding portion 2, a bonding wire 5, and a resin 4.
The semiconductor element 1 and the lead frame 3 are joined by the joining portion 2. The connection terminals (not shown) of the semiconductor element 1 are connected to the lead frame 3 by the bonding wires 5. The resin 4 seals the semiconductor element 1, the bonding wire 5, the bonding portion 2, and the lead frame 3. However, the connecting lead 15 of the lead frame 3 is drawn out of the resin 4. 2 and 3, the external terminal portion exposed from the resin 4 of the lead frame 3 is shown as a flat shape.
　図４は、図３に図示された半導体デバイスの要部である接合構造を示し、図４（ａ）は、接合構造を上方からみた平面図であり、図４（ｂ）は、図４（ａ）のＩＶｂ－ＩＶｂ線断面模式図である。図４（ａ）、図４（ｂ）では、リードフレーム３は、半導体素子１が接合された接合部２の領域付近のみが図示されている。
　以下では、半導体素子１側を上方側、リードフレーム３側を下方側として説明する。
　接合構造３０は、半導体素子１、接合部２、リードフレーム３により構成されている。換言すれば、接合構造３０は、半導体デバイス１４のうち、ボンディングワイヤ５および樹脂４を除いた部分の構造である。
　半導体素子１は、平面視で矩形形状を有する。半導体素子１は、例えば、ＩＧＢＴ(Insulating Gate Bipolar Transistor)、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等の集積回路である。
　接合部２は、多孔質金属２１とはんだ２２とから構成されている（図３も参照）。 4 shows a junction structure which is a main part of the semiconductor device shown in FIG. 3, FIG. 4A is a plan view of the junction structure seen from above, and FIG. FIG. 4B is a schematic cross-sectional view taken along the line IVb-IVb of FIG. In FIG. 4A and FIG. 4B, the lead frame 3 is shown only in the vicinity of the region of the joint 2 to which the semiconductor element 1 is joined.
Hereinafter, the semiconductor element 1 side will be described as the upper side and the lead frame 3 side as the lower side.
The joint structure 30 is composed of the semiconductor element 1, the joint portion 2, and the lead frame 3. In other words, the bonding structure 30 is the structure of the semiconductor device 14 excluding the bonding wires 5 and the resin 4.
The semiconductor element 1 has a rectangular shape in a plan view. The semiconductor element 1 is, for example, an integrated circuit such as an IGBT (Insulating Gate Bipolar Transistor) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
The joint 2 is composed of a porous metal 21 and a solder 22 (see also FIG. 3).
　多孔質金属２１は、銅やニッケルにより形成され、連続する空孔を有する多孔質金属部材である。多孔質金属２１は、半導体素子１に対向する小面積の上段部２１ｂと、リードフレーム３に対向する下段部２１ａとを有する段付き角柱形状を有する。上段部２１ｂは、平面視で、下段部２１ａより小さく、半導体素子１とほぼ同じサイズまたはそれより小さいサイズの矩形形状を有する。多孔質金属２１の中心は、半導体素子１の中心とほぼ同じ位置に配置されている。
　ここで、連続する空孔とは次の意味で使用する。すなわち、多孔質金属の表面には無数の開口が設けられ、その開口から内部に連通し、内部で縦横に形成された無数の空孔のそれぞれが連通していることである。そのため、後述するはんだ印刷工程において、多孔質金属に塗布したはんだ材をスキージで伸ばしたときに、多孔質金属の表面からはんだ材が空孔にまんべんなく、十分に充填される。 The porous metal 21 is a porous metal member formed of copper or nickel and having continuous pores. The porous metal 21 has a stepped prism shape having an upper step portion 21b having a small area facing the semiconductor element 1 and a lower step portion 21a facing the lead frame 3. The upper step portion 21b has a rectangular shape that is smaller than the lower step portion 21a and is substantially the same size as or smaller than the semiconductor element 1 in a plan view. The center of the porous metal 21 is arranged at substantially the same position as the center of the semiconductor element 1.
Here, the continuous holes are used in the following meaning. That is, it means that innumerable openings are provided on the surface of the porous metal and communicate with the inside through the openings, and with each of the innumerable holes formed vertically and horizontally inside. Therefore, when the solder material applied to the porous metal is stretched with a squeegee in the solder printing step described later, the solder material is evenly and sufficiently filled from the surface of the porous metal into the pores.
　はんだ２２は、第１のはんだ２３と第２のはんだ２４とで構成されているものとする。第１のはんだ２３は、多孔質金属２１の空孔に充填されたはんだと、多孔質金属２１の表面を覆うはんだを含む。第２のはんだ２４は、多孔質金属２１の周側面全面を覆うように第１のはんだ２３と一体化されている。
　第１のはんだ２３および第２のはんだ２４は、多孔質金属２１上およびその周囲にはんだ材を印刷などにより付着し、リフロー炉等に投入して加熱することにより形成される。はんだ印刷工程において、多孔質金属２１の空孔にはんだ材が充填されるとともに、多孔質金属２１の表の面と側面全周にもはんだ材が塗布される。このように多孔質金属２１の周囲に塗布されたはんだ材がリフローで溶融してはんだ２２が形成される。
　第１のはんだ２３は、多孔質金属２１の空孔内に充填されたはんだ（以下、充填部と呼ぶ）２３ａと、半導体素子１と多孔質金属２１の上段部２１ｂの上面との間に設けられたはんだ（以下、上部側の表面接合部と呼ぶ）２３ｂと、リードフレーム３と多孔質金属２１の下段部２１ａの下面との間に設けられたはんだ（以下、下部側の表面接合部と呼ぶ）２３ｃを有する。
　なお、図４（ｂ）に示す接合構造３０の断面模式図では、上部側および下部側の表面接合部２３ｂ、２３ｃの形状は、凹凸の波打ち形状や、局所的な空隙等を無視して、均一な厚さに簡素化して示している。また、上部側および下部側の表面接合部２３ｂ、２３ｃは、それぞれ、多孔質金属２１の上段部２１ｂの上面の一部の領域のみ、または多孔質金属２１の下段部２１ａの下面の一部の領域のみに形成されることもある。また、上部側の表面接合部２３ｂと下部側の表面接合部２３ｃの一方のみが形成されることもある。 The solder 22 is assumed to be composed of a first solder 23 and a second solder 24. The first solder 23 includes solder that fills the pores of the porous metal 21 and solder that covers the surface of the porous metal 21. The second solder 24 is integrated with the first solder 23 so as to cover the entire peripheral side surface of the porous metal 21.
The first solder 23 and the second solder 24 are formed by depositing a solder material on the porous metal 21 and its periphery by printing or the like, and putting the solder material in a reflow furnace or the like to heat it. In the solder printing process, the pores of the porous metal 21 are filled with the solder material, and the solder material is also applied to the front surface and the entire circumference of the side surface of the porous metal 21. In this way, the solder material applied around the porous metal 21 is melted by reflow to form the solder 22.
The first solder 23 is provided between the solder (hereinafter referred to as a filling portion) 23 a filled in the pores of the porous metal 21 and the upper surface of the semiconductor element 1 and the upper step portion 21 b of the porous metal 21. Solder (hereinafter referred to as the upper surface joint portion) 23b and the solder provided between the lead frame 3 and the lower surface of the lower step portion 21a of the porous metal 21 (hereinafter referred to as the lower surface joint portion). Call) 23c.
In the schematic cross-sectional view of the joining structure 30 shown in FIG. 4B, the shapes of the upper-side and lower-side surface joining portions 23b and 23c are such that irregular wavy shapes and local voids are ignored. The thickness is shown in a simplified manner. Further, the upper and lower surface joints 23b and 23c are respectively only in a part of the upper surface of the upper step portion 21b of the porous metal 21 or in a part of the lower surface of the lower step portion 21a of the porous metal 21. It may be formed only in the region. Further, only one of the upper surface joint portion 23b and the lower surface joint portion 23c may be formed.
　第２のはんだ２４は、厚さ方向（上下方向）における半導体素子１とリードフレーム３間において、多孔質金属２１の周側面全周を覆って設けられている。第２のはんだ２４の周側面は、半導体素子１側からリードフレーム３側に向けて外周側に拡がる傾斜面となっている。換言すれば、第２のはんだ２４は、多孔質金属２１の下段部２１ａの周囲側の水平断面積が、上段部２１ｂの周囲側の水平断面積よりも面積が大きい角錐台の如き形状を有する。ここで、水平断面積とは、半導体デバイス１４の表裏面と平行に延在する方向の切断線ではんだ２２を切った断面の面積である。第２のはんだ２４は、第１のはんだ２３の上部側の表面接合部２３ｂおよび下部側の表面接合部２３ｃと一体化されている。上部側の表面接合部２３ｂおよび上部側の表面接合部２３ｃと一体化された第２のはんだ２４は、厚さ方向における半導体素子１とリードフレーム３間全体に充填された大きい厚さを有する。 The second solder 24 is provided so as to cover the entire peripheral side surface of the porous metal 21 between the semiconductor element 1 and the lead frame 3 in the thickness direction (vertical direction). The peripheral side surface of the second solder 24 is an inclined surface that spreads from the semiconductor element 1 side toward the lead frame 3 side toward the outer peripheral side. In other words, the second solder 24 has a shape like a truncated pyramid in which the horizontal cross-sectional area on the peripheral side of the lower step portion 21a of the porous metal 21 is larger than the horizontal cross-sectional area on the peripheral side of the upper step portion 21b. .. Here, the horizontal cross-sectional area is an area of a cross section of the solder 22 taken along a cutting line extending in a direction parallel to the front and back surfaces of the semiconductor device 14. The second solder 24 is integrated with the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23. The second solder 24 integrated with the upper surface joint portion 23b and the upper surface joint portion 23c has a large thickness filled in the entire space between the semiconductor element 1 and the lead frame 3 in the thickness direction.
　比較例として、リードフレームと半導体素子とを、空孔内にはんだが充填された多孔質金属のみを有する接合部により接合する構造がある。すなわち、多孔質金属の表の面全域にのみはんだ材を塗布してはんだ材を空孔内に充填してリフローしてはんだ接合する構造である。換言すれば、本実施形態の第２のはんだ２４を有していない接合部により接合する構造がある。この比較例の構造でも、接合時に、多孔質金属の空孔内に充填されたはんだが表面に滲み出て、多孔質金属と半導体素子との間および／または多孔質金属とリードフレームとの間に表面接合部が形成される。しかし、このように、多孔質金属の空孔内にのみはんだを充填してリフローする比較例では、多孔質金属と半導体素子との間および多孔質金属とリードフレームとの間に形成される表面接合部の厚さは大変薄い。このため、負荷が掛かることにより生じるひずみにより生じるき裂進展率が大きく、寿命が低下する。 As a comparative example, there is a structure in which a lead frame and a semiconductor element are joined by a joint portion having only a porous metal in which holes are filled with solder. That is, the structure is such that the solder material is applied only to the entire front surface of the porous metal, the solder material is filled in the pores, and the reflow is performed to perform solder joining. In other words, there is a structure in which the second solder 24 of the present embodiment is joined by the joining portion that does not have the second solder 24. Also in the structure of this comparative example, the solder filled in the pores of the porous metal oozes out on the surface at the time of joining, and between the porous metal and the semiconductor element and/or between the porous metal and the lead frame. A surface joint is formed on the surface. However, in this way, in the comparative example in which the solder is filled only in the pores of the porous metal and the reflow is performed, the surface formed between the porous metal and the semiconductor element and between the porous metal and the lead frame. The thickness of the joint is very thin. Therefore, the crack growth rate caused by the strain caused by the load is large, and the life is shortened.
　これに対し、本実施形態の接合構造３０では、上述したように、厚さの小さい第１のはんだ２３の上部側の表面接合部２３ｂと下部側の表面接合部２３ｃは、厚さ方向（上下方向）における半導体素子１とリードフレーム３間全体に設けられた厚さの大きい第２のはんだ２４に囲まれて一体化されている。このため、第１のはんだ２３の上部側の表面接合部２３ｂおよび第１のはんだ２３の下部側の表面接合部２３ｃの端部に生じるひずみは、第２のはんだ２４により抑制され、長寿命化を図ることができる。
　以下、実施例と共に、このことを説明する。 On the other hand, in the joint structure 30 of the present embodiment, as described above, the surface joint portion 23b on the upper side and the surface joint portion 23c on the lower side of the first solder 23 having a small thickness are arranged in the thickness direction (vertical direction). Direction), the semiconductor element 1 and the lead frame 3 are surrounded and integrated by the second solder 24 having a large thickness provided over the entire area. Therefore, the strain generated at the end portions of the upper surface joint portion 23b of the first solder 23 and the lower surface joint portion 23c of the first solder 23 is suppressed by the second solder 24, and the life is extended. Can be planned.
Hereinafter, this will be described together with examples.
［実施例１］
　以下の部材を用いて、図３および図４（ａ）、（ｂ）に示す半導体デバイス１４を作製した。
　半導体素子１は、５ｍｍ角のＳｉ－ＭＯＳＦＥＴを用いた。リードフレーム３として、材質がＣ１９４００で、厚さ０．５ｍｍの板材を用いた。ボンディングワイヤ５として、直径２００μｍのＡｌワイヤを用いた。多孔質金属２１として、材質が銅で、空孔率が８０％の連続する空孔を有する多孔質金属部材を用いた。第１のはんだ２３として、Ｓｎ－１０Ｓｂを用いた。また、第２のはんだ２４も、第１のはんだ２３と同じ、Ｓｎ－１０Ｓｂを用いた。 [Example 1]
A semiconductor device 14 shown in FIGS. 3 and 4A and 4B was manufactured using the following members.
As the semiconductor element 1, a 5 mm square Si-MOSFET was used. As the lead frame 3, a plate material having a material of C19400 and a thickness of 0.5 mm was used. As the bonding wire 5, an Al wire having a diameter of 200 μm was used. As the porous metal 21, a porous metal member made of copper and having continuous voids with a porosity of 80% was used. Sn-10Sb was used as the first solder 23. As the second solder 24, Sn-10Sb, which is the same as the first solder 23, was used.
　多孔質金属２１を図４（ａ）、（ｂ）に示す段付き角柱形状に形成し、第１のはんだ２３の量および第２のはんだ２４の量を含む量のはんだ２２を、多孔質金属２１上およびその外周に塗布した。この状態で、例えば、Ｎ２等の不活性ガス雰囲気中で加熱するとともに、はんだが溶融中に真空にできるリフロー炉（図示せず）に投入して、図４（ａ）、（ｂ）に示す構造のはんだ２２を有する接合構造３０を作製した。 The porous metal 21 is formed into a stepped prism shape shown in FIGS. 4A and 4B, and the amount of the solder 22 including the amount of the first solder 23 and the amount of the second solder 24 is changed to the porous metal. 21 and the outer periphery thereof. In this state, for example, while heating in an inert gas atmosphere such as N 2 or the like, the solder is put into a reflow furnace (not shown) that can be evacuated during melting, and the solder is put into FIGS. A joint structure 30 having the solder 22 having the structure shown was produced.
　上述した通り、多孔質金属２１の上段部２１ｂは、平面視で、下段部２１ａより小さいサイズの矩形形状を有する。このため、リフロー炉に投入して加熱し、はんだ２２を溶融すると、はんだ２２は、多孔質金属２１の上段部２１ｂと下段部２１ａとの形状に倣って、半導体素子１側からリードフレーム３側に向けて外周側に拡がる。これにより、はんだ２２は、図４（ｂ）に示されるように、リードフレーム３側の面積が半導体素子１側の面積より大きい角錐台形状に形成される。すなわち、はんだ２２を多孔質金属２１上およびその外周に塗布してリフロー炉に投入するだけで、はんだ２２は、図４（ｂ）に示される角錐台形状に形成される。この構造では、はんだ２２は、多孔質金属２１の上段部２１ｂと下段部２１ａとの外周のサイズに沿って拡がり、多孔質金属２１の上段部２１ｂの周囲と多孔質金属２１の下段部２１ａの周側面を覆って、厚さ方向全体に厚く形成される。 As described above, the upper step portion 21b of the porous metal 21 has a rectangular shape which is smaller than the lower step portion 21a in plan view. Therefore, when the solder 22 is put into a reflow furnace and heated to melt the solder 22, the solder 22 follows the shapes of the upper step portion 21b and the lower step portion 21a of the porous metal 21 from the semiconductor element 1 side to the lead frame 3 side. Spreads toward the outer circumference. As a result, the solder 22 is formed in a truncated pyramid shape in which the area on the lead frame 3 side is larger than the area on the semiconductor element 1 side, as shown in FIG. 4B. That is, the solder 22 is formed into the truncated pyramid shape shown in FIG. 4B only by applying the solder 22 onto the porous metal 21 and the outer periphery thereof and placing the solder 22 in the reflow furnace. In this structure, the solder 22 spreads along the size of the outer circumference of the upper step portion 21b and the lower step portion 21a of the porous metal 21, and surrounds the upper step portion 21b of the porous metal 21 and the lower step portion 21a of the porous metal 21. The peripheral side surface is covered and formed thick in the entire thickness direction.
　この後、半導体素子１とリードフレーム３とを、ボンディングワイヤ５により接続し、エポキシ樹脂などからなる樹脂４により、半導体素子１、ボンディングワイヤ５、接合部２およびリードフレーム３を、接続用リード１５のみが露出されるように封止して図３に示す半導体デバイス１４を得た。 After that, the semiconductor element 1 and the lead frame 3 are connected by a bonding wire 5, and the semiconductor element 1, the bonding wire 5, the joint portion 2, and the lead frame 3 are connected to each other by a bonding lead 15 by a resin 4 made of epoxy resin or the like. The semiconductor device 14 shown in FIG. 3 was obtained by sealing so as to expose only the semiconductor device.
　また、比較例１として、図５に示す接合構造３０Ｒを有する半導体デバイス（図示せず）を作製した。
　図５は、比較例１の半導体デバイスの要部である接合構造を示し、図５（ａ）は、半導体デバイスの要部である接合構造を上方からみた平面図であり、図５（ｂ）は、図５（ａ）のＶｂ－Ｖｂ線断面模式図である。
　比較例１の接合構造３０Ｒは、半導体素子１と、接合部２ｒと、リードフレーム３から構成されている。比較例１の半導体素子１およびリードフレーム３の構造および材料は、それぞれ、実施例１の半導体素子１およびリードフレーム３と同一である。また、比較例１として示す半導体デバイスの接合構造３０Ｒを除いた部分の構造および材料は、本実施形態の半導体デバイス１４の接合構造３０を除いた部分の構造および材料と同一である。つまり、比較例１の半導体デバイスは接合部２ｒを有する点でのみ、接合部２を有する本実施形態の半導体デバイス１４と相違する。 As Comparative Example 1, a semiconductor device (not shown) having the junction structure 30R shown in FIG. 5 was manufactured.
5 shows a junction structure which is an essential part of the semiconductor device of Comparative Example 1, and FIG. 5A is a plan view of the junction structure which is an essential part of the semiconductor device seen from above, and FIG. FIG. 6 is a schematic sectional view taken along line Vb-Vb of FIG.
The joint structure 30R of Comparative Example 1 includes the semiconductor element 1, the joint portion 2r, and the lead frame 3. The structures and materials of the semiconductor element 1 and the lead frame 3 of Comparative Example 1 are the same as those of the semiconductor element 1 and the lead frame 3 of Example 1, respectively. Further, the structure and material of the part of the semiconductor device shown as Comparative Example 1 excluding the junction structure 30R are the same as the structure and material of the part of the semiconductor device 14 of the present embodiment excluding the junction structure 30. That is, the semiconductor device of Comparative Example 1 is different from the semiconductor device 14 of the present embodiment having the junction 2 only in having the junction 2r.
　比較例１については、主として実施例１との相違点について説明する。
　比較例１の接合部２ｒは、多孔質金属２１ｒと第１のはんだ２３とを有する。
　多孔質金属２１ｒは、半導体素子１とほぼ同じ平面サイズを有し、厚さ方向（上下方向）全体に亘り同一面積の矩形断面を有する角柱形状に形成されている。接合部２ｒは、第１のはんだ２３のみを有し、第２のはんだ２４を有していない。第１のはんだ２３は、上記実施形態の接合構造３０と同様、多孔質金属２１ｒの空孔に充填された充填部２３ａと、半導体素子１と多孔質金属２１の上面との間に設けられた上部側の表面接合部２３ｂと、リードフレーム３と多孔質金属２１の下面との間に設けられた下部側の表面接合部２３ｃを有する。
　比較例１の半導体デバイスの材料やその他の構造は、すべて、実施例１と同様である。 Regarding Comparative Example 1, differences from Example 1 will be mainly described.
The joint portion 2r of Comparative Example 1 has the porous metal 21r and the first solder 23.
The porous metal 21r has substantially the same plane size as the semiconductor element 1, and is formed in a prismatic shape having a rectangular cross section with the same area over the entire thickness direction (vertical direction). The joint portion 2r has only the first solder 23 and does not have the second solder 24. The first solder 23 is provided between the filling portion 23a filled in the pores of the porous metal 21r and the upper surface of the semiconductor element 1 and the upper surface of the porous metal 21 as in the bonding structure 30 of the above embodiment. It has an upper surface joint 23b and a lower surface joint 23c provided between the lead frame 3 and the lower surface of the porous metal 21.
The materials and other structures of the semiconductor device of Comparative Example 1 are all the same as in Example 1.
　実施例１の半導体デバイス１４および比較例１の半導体デバイスについて、温度サイクル試験を行った後、半導体デバイスそれぞれのき裂進展率を測定した。
　温度サイクル試験としては、－４０℃と２００℃とを繰り返し２０００サイクル行った。
　図６は、本発明の実施例１と比較例１の半導体デバイスにおける、温度サイクル試験後のき裂進展率を示す図である。
　き裂進展率は、半導体素子１の対角線下の断面におけるものである。
　図６に示すように、比較例１の半導体デバイスのき裂進展率は７０％であり、実施例１の半導体デバイス１４のき裂進展率は５９％であった。
　これにより、実施例１の半導体デバイス１４は、比較例１の半導体デバイスよりもき裂進展率が小さくなることを確認することができた。 After performing a temperature cycle test on the semiconductor device 14 of Example 1 and the semiconductor device of Comparative Example 1, the crack growth rate of each semiconductor device was measured.
As the temperature cycle test, -40° C. and 200° C. were repeated 2000 times.
FIG. 6 is a diagram showing the crack growth rates after the temperature cycle test in the semiconductor devices of Example 1 of the present invention and Comparative Example 1.
The crack growth rate is in the cross section below the diagonal line of the semiconductor element 1.
As shown in FIG. 6, the crack growth rate of the semiconductor device of Comparative Example 1 was 70%, and the crack growth rate of the semiconductor device 14 of Example 1 was 59%.
This confirmed that the semiconductor device 14 of Example 1 had a smaller crack growth rate than the semiconductor device of Comparative Example 1.
　なお、上記第１の実施形態では、第２のはんだ２４は、多孔質金属２１の外周全周において、厚さ方向における半導体素子１とリードフレーム３間全体に設けられる構造として例示した。しかし、第２のはんだ２４は、多孔質金属２１の外周の一部の領域において、厚さ方向における半導体素子１とリードフレーム３間全体に設けられる構造としてもよい。 In the first embodiment described above, the second solder 24 is illustrated as a structure provided over the entire circumference of the porous metal 21 between the semiconductor element 1 and the lead frame 3 in the thickness direction. However, the second solder 24 may be provided over the entire area between the semiconductor element 1 and the lead frame 3 in the thickness direction in a partial region of the outer periphery of the porous metal 21.
　本発明の第１の実施形態によれば、下記の効果を奏する。
（１）電子制御装置１０は、半導体素子（電子部品）１と、リードフレーム（基板）３と、接合部２とを備える。接合部２は、多孔質金属２１と、第１のはんだ２３および第２のはんだ２４を有する。第１のはんだ２３は、多孔質金属２１の空孔に充填された充填部２３ａと、半導体素子１と多孔質金属２１との間の少なくとも一部の領域と、リードフレーム３と多孔質金属２１との間の少なくとも一部の領域との少なくとも一方に設けられた表面接合部２３ｂまたは２３ｃを有する。第２のはんだ２４は、第１のはんだ２３の表面接合部２３ｂまたは２３ｃのいずれの厚さより厚い。このように、厚さの小さい第１のはんだ２３の表面接合部２３ｂ、２３ｃに、厚さの大きい第２のはんだ２４を一体化するため、第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂の進展が抑制され、半導体デバイス１４の信頼性を向上し、高寿命化を図ることができる。 According to the first embodiment of the present invention, the following effects are achieved.
(1) The electronic control device 10 includes a semiconductor element (electronic component) 1, a lead frame (substrate) 3, and a joint portion 2. The joint portion 2 has a porous metal 21, a first solder 23, and a second solder 24. The first solder 23 includes a filling portion 23 a filled in the holes of the porous metal 21, at least a partial region between the semiconductor element 1 and the porous metal 21, the lead frame 3 and the porous metal 21. And a surface bonding portion 23b or 23c provided in at least one of at least a part of the area between and. The second solder 24 is thicker than either the surface joint portion 23b or 23c of the first solder 23. In this way, since the second solder 24 having a large thickness is integrated with the surface joints 23b and 23c of the first solder 23 having a small thickness, the surface joints 23b and 23c of the first solder 23 are formed to be integrated. The growth of cracks can be suppressed, the reliability of the semiconductor device 14 can be improved, and the life can be extended.
－第２の実施形態－
　図７は、本発明の半導体デバイスの要部である接合構造の第２の実施形態の断面模式図である。
　第２の実施形態の接合構造３０は、リードフレーム３の多孔質金属２１と対向する面にニッケル（Ｎｉ）めっき層７を有する点で、第１の実施形態と相違する。
［実施例２］
　リードフレーム３は、実施例１と同様、材質がＣ１９４００、厚さ０．５ｍｍの板材を用い、ニッケルめっき層７は、無電解めっきにより厚さ３μｍに形成した。実施例２の接合構造３０は、リードフレーム３の一面にニッケルめっき層７を形成する以外は、材料およびその他の構成のすべてが、実施例１と同一の接合構造３０と同一である。 -Second Embodiment-
FIG. 7 is a schematic cross-sectional view of the second embodiment of the junction structure which is the main part of the semiconductor device of the present invention.
The bonding structure 30 of the second embodiment differs from that of the first embodiment in that a nickel (Ni) plating layer 7 is provided on the surface of the lead frame 3 facing the porous metal 21.
[Example 2]
As in the case of Example 1, the lead frame 3 was a plate material having a material of C19400 and a thickness of 0.5 mm, and the nickel plating layer 7 was formed by electroless plating to a thickness of 3 μm. The joint structure 30 of the second embodiment is the same as the joint structure 30 of the first embodiment in terms of materials and other configurations except that the nickel plating layer 7 is formed on one surface of the lead frame 3.
　図８は、本発明の実施例２と比較例１の半導体デバイスにおける、温度サイクル試験後のき裂進展率を示す図である。
　温度サイクル試験は、第１の実施形態と比較例１の場合と同様、－４０℃と２００℃とを繰り返し２０００サイクル行ったものである。
　図８に示すように、比較例１の半導体デバイスき裂進展率は７０％であり、実施例２の半導体デバイス１４のき裂進展率は５６％であった。
　これにより、実施例２の半導体デバイス１４も、比較例１の半導体デバイスよりもき裂進展率を小さくすることを確認することができた。しかも、実施例２の半導体デバイス１４の方が、実施例１の半導体デバイス１４よりもき裂進展率が小さい。 FIG. 8 is a diagram showing the crack growth rate after the temperature cycle test in the semiconductor devices of Example 2 of the present invention and Comparative Example 1.
In the temperature cycle test, as in the case of the first embodiment and Comparative Example 1, -40° C. and 200° C. were repeated 2000 cycles.
As shown in FIG. 8, the crack growth rate of the semiconductor device of Comparative Example 1 was 70%, and the crack growth rate of the semiconductor device 14 of Example 2 was 56%.
This confirmed that the semiconductor device 14 of Example 2 also had a smaller crack growth rate than the semiconductor device of Comparative Example 1. Moreover, the semiconductor device 14 of Example 2 has a smaller crack growth rate than the semiconductor device 14 of Example 1.
　実施例１および比較例１のように、Ｃｕからなるリードフレーム３にＳｎまたはＳｎ合金を接合すると、ＣｕとＳｎまたはＳｎ合金との界面に、金属間化合物であるＣｕ－Ｓｎ化合物が形成される。
　これに対し、リードフレーム３の一面にニッケルめっき層７を形成する実施例２では、ニッケルめっき層７によりＣｕ－Ｓｎ化合物の形成が阻止され、ニッケルめっき層７とＳｎまたはＳｎ合金との界面にＮｉ―Ｓｎ化合物が形成される。 When Sn or Sn alloy is bonded to the lead frame 3 made of Cu as in Example 1 and Comparative Example 1, Cu—Sn compound which is an intermetallic compound is formed at the interface between Cu and Sn or Sn alloy. ..
On the other hand, in Example 2 in which the nickel plating layer 7 is formed on one surface of the lead frame 3, the formation of the Cu—Sn compound is prevented by the nickel plating layer 7, and the nickel plating layer 7 is formed at the interface between the nickel plating layer 7 and Sn or Sn alloy. A Ni-Sn compound is formed.
　図９は、本発明の実施例２と比較例１の半導体デバイスの平均化合物厚さを示す図である。実施例２および比較例１の平均化合物厚さは、リードフレーム３と接合部２の端部側の界面におけるものである。
　図９に示されるように、実施例２の平均化合物厚さは１５μｍであり、比較例１の平均化合物厚さ２６μｍより薄かった。
　金属間化合物は、ＳｎまたはＳｎ合金からなる、はんだに比し、硬くて脆いため、その厚さが厚いほど、き裂が進展し易い。
　リードフレーム３とはんだ２２との間にニッケルめっき層７を形成した実施例２は、リードフレーム３とはんだ２２との間にニッケルめっき層７が形成されていない比較例１よりも第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂の進展率が小さくなり、長寿命化を図ることができることを確認することができた。 FIG. 9 is a diagram showing the average compound thickness of the semiconductor devices of Example 2 of the present invention and Comparative Example 1. The average compound thicknesses of Example 2 and Comparative Example 1 are at the interface between the lead frame 3 and the end portion side of the joint portion 2.
As shown in FIG. 9, the average compound thickness of Example 2 was 15 μm, which was smaller than the average compound thickness of 26 μm of Comparative Example 1.
Since the intermetallic compound is harder and more brittle than solder, which is made of Sn or Sn alloy, the thicker the thickness thereof, the easier the cracks grow.
The example 2 in which the nickel plating layer 7 is formed between the lead frame 3 and the solder 22 is the first solder more than the comparative example 1 in which the nickel plating layer 7 is not formed between the lead frame 3 and the solder 22. It was confirmed that the crack growth rate of the surface bonding portions 23b and 23c of No. 23 was reduced and the life could be extended.
　以上の通り、第２の実施形態においても、厚さの小さい第１のはんだ２３の上部側の表面接合部２３ｂと下部側の表面接合部２３ｃは、厚さ方向における半導体素子１とリードフレーム３間全体に充填された、厚さの大きい第２のはんだ２４で覆われている。
　従って、第２の実施形態においても、第１の実施形態と同様な効果を奏する。
　さらに、第２の実施形態では、リードフレーム３の一面に形成するニッケルめっき層７により硬くて脆いＣｕ－Ｓｎ化合物の形成が阻止される。このため、き裂進展率の低下に一層の効果を奏する。 As described above, also in the second embodiment, the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23 having a small thickness have the semiconductor element 1 and the lead frame 3 in the thickness direction. It is covered with the second solder 24 having a large thickness and filled in the entire space.
Therefore, also in the second embodiment, the same effect as that of the first embodiment is obtained.
Further, in the second embodiment, the nickel plating layer 7 formed on the one surface of the lead frame 3 prevents the formation of a hard and brittle Cu—Sn compound. Therefore, the crack growth rate is further reduced.
－第３の実施形態－
　図１０は、本発明の半導体デバイスの要部である接合構造の第３の実施形態を示し、図１０（ａ）は、接合部の上面からみた平面図であり、図１０（ｂ）は、図１０（ａ）のＸｂ－Ｘｂ線断面模式図であり、図１０（ｃ）は、図１０（ａ）のＸｃ－Ｘｃ線断面模式図である。なお、図１０（ａ）では、半導体素子１を透明とし、その外形を二点鎖線により図示している。
　第３の実施形態の接合構造３０では、多孔質金属２１は、矩形体の４つのコーナー部４４の三角形の領域２４ａを取り除いた、平面視で、八角形形状を有する。つまり、多孔質金属２１は、一対の長辺４１と、一対の短辺４２と、４つの斜辺４３を有する八角形形状を有する。多孔質金属２１は、厚さ方向全体に亘り断面積がほぼ同一であり、八角柱形状を有する。 -Third Embodiment-
FIG. 10 shows a third embodiment of a junction structure which is a main part of a semiconductor device of the present invention, FIG. 10(a) is a plan view seen from the upper surface of the junction, and FIG. 10(b) is 10A is a schematic sectional view taken along line Xb-Xb in FIG. 10A, and FIG. 10C is a schematic sectional view taken along line Xc-Xc in FIG. 10A. In addition, in FIG. 10A, the semiconductor element 1 is transparent, and its outer shape is illustrated by a two-dot chain line.
In the joining structure 30 of the third embodiment, the porous metal 21 has an octagonal shape in a plan view in which the triangular regions 24a of the four corner portions 44 of the rectangular body are removed. That is, the porous metal 21 has an octagonal shape having a pair of long sides 41, a pair of short sides 42, and four oblique sides 43. The porous metal 21 has substantially the same cross-sectional area over the entire thickness direction and has an octagonal prism shape.
　多孔質金属２１の長辺４１のそれぞれは、半導体素子１の各長辺とほぼ重なる位置に配置され、多孔質金属２１の短辺４２のそれぞれは、半導体素子１の各短辺とほぼ重なる位置に配置されている。従って、多孔質金属２１の周側面全周を覆う第２のはんだ２４は、多孔質金属２１の各コーナー部４４では、三角形の領域２４ａ内にも形成され、斜辺４３に接触する内側まで充填される。
　つまり、第３の実施形態では、第１の実施形態よりも、４つのコーナー部４４における、半導体素子１の長辺と半導体素子１の短辺と多孔質金属２１の斜辺で囲まれる平面視で三角形の領域２４ａの部分だけ、第２のはんだ２４の領域の面積が大きい。 Each of the long sides 41 of the porous metal 21 is arranged at a position substantially overlapping with each of the long sides of the semiconductor element 1, and each of the short sides 42 of the porous metal 21 is at a position substantially overlapping with each of the short sides of the semiconductor element 1. It is located in. Therefore, the second solder 24 that covers the entire circumference of the peripheral surface of the porous metal 21 is also formed in the triangular region 24 a at each corner portion 44 of the porous metal 21, and is filled up to the inner side in contact with the hypotenuse 43. It
That is, in the third embodiment, in a plan view surrounded by the long sides of the semiconductor element 1, the short sides of the semiconductor element 1, and the oblique sides of the porous metal 21 in the four corner portions 44, as compared with the first embodiment. The area of the second solder 24 region is large only in the triangular region 24a.
　第３の実施形態においても、はんだと電子部品の接合についての他の構成は第１の実施形態と同様であり、第１のはんだ２３は、多孔質金属２１の空孔内に充填された充填部２３ａと、半導体素子１と多孔質金属２１の上面との間に設けられた上部側の表面接合部２３ｂと、リードフレーム３と多孔質金属２１の下面との間に設けられた下部側の表面接合部２３ｃを有する。また、第２のはんだ２４は、第１のはんだ２３の上部側の表面接合部２３ｂと第１のはんだ２３の下部側の表面接合部２３ｃとに一体化されている。
　従って、第３の実施形態においても、第１の実施形態と同様な効果を奏する。また、第３の実施形態では、平面視で三角形の領域２４ａの部分だけ、第１のはんだ２３の上・下部側の表面接合部２３ｂ、２３ｃとの接合の面積が第１の実施形態よりも大きいので、第１の実施形態よりも第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂の進展を抑制できる可能性がある。 Also in the third embodiment, the other configuration for joining the solder and the electronic component is the same as that of the first embodiment, and the first solder 23 is filled in the pores of the porous metal 21. A portion 23a, an upper surface joint portion 23b provided between the semiconductor element 1 and the upper surface of the porous metal 21, and a lower portion provided between the lead frame 3 and the lower surface of the porous metal 21. It has a surface bonding portion 23c. Further, the second solder 24 is integrated with the upper surface joint portion 23 b of the first solder 23 and the lower surface joint portion 23 c of the first solder 23.
Therefore, also in the third embodiment, the same effect as that of the first embodiment is obtained. Further, in the third embodiment, only the area of the triangular region 24a in plan view has an area of bonding with the surface bonding portions 23b and 23c on the upper and lower sides of the first solder 23 more than that of the first embodiment. Since it is large, there is a possibility that crack propagation of the surface joint portions 23b and 23c of the first solder 23 can be suppressed more than in the first embodiment.
　また、温度等、周囲の環境に変化が生じると、半導体素子１のコーナー部４４には、他の領域よりも大きいひずみが発生する。第３の実施形態では、大きいひずみが発生する半導体素子１のコーナー部４４に、第２のはんだ２４が充填された三角形の領域２４ａが設けられている。このため、第３の実施形態によれば、半導体素子１のコーナー部４４に大きな負荷が掛かる場合でも、第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂進展率を小さくすることができる。 Further, when a change occurs in the surrounding environment such as temperature, the corner portion 44 of the semiconductor element 1 is distorted more than other regions. In the third embodiment, the triangular region 24a filled with the second solder 24 is provided in the corner portion 44 of the semiconductor element 1 where large strain occurs. Therefore, according to the third embodiment, even when a large load is applied to the corner portion 44 of the semiconductor element 1, the crack growth rate of the surface joint portions 23b and 23c of the first solder 23 can be reduced. ..
　なお、第３の実施形態において、多孔質金属２１を、上下方向である厚さ方向全体に亘り断面積がほぼ同一な八角柱形状として例示した。しかし、第３の実施形態における多孔質金属２１を、第１の実施形態と同様、下段部２１ａの平面サイズが上段部２１ｂの平面サイズより大きい段付き角柱形状としてもよい。
　また、上記実施形態では、多孔質金属２１を、平面視で矩形体の４つのコーナー部で取り除いた、平面視で八角形形状として例示した。しかし、多孔質金属２１を、平面視で矩形体の１以上のコーナー部で取り除いた五角形以上の多辺形形状を有する部材としたり、平面視で半導体素子１の長辺と半導体素子１の短辺との少なくとも一辺と略接する円や楕円形状を有する部材としたりすることができる。この構造の場合でも、矩形形状の半導体素子１のコーナー部４４に対応する領域には、第２のはんだ２４が充填される。 In addition, in the third embodiment, the porous metal 21 is illustrated as an octagonal prism shape having substantially the same cross-sectional area over the entire thickness direction, which is the vertical direction. However, the porous metal 21 in the third embodiment may have a stepped prism shape in which the plane size of the lower step portion 21a is larger than the plane size of the upper step portion 21b, as in the first embodiment.
In addition, in the above-described embodiment, the porous metal 21 is illustrated as an octagonal shape in plan view in which the four corners of the rectangular body are removed in plan view. However, the porous metal 21 may be a member having a pentagonal or more polygonal shape obtained by removing one or more corners of a rectangular body in a plan view, or may be a long side of the semiconductor element 1 and a short side of the semiconductor element 1 in a plan view. It may be a member having a circle or an elliptical shape that is substantially in contact with at least one side. Even in the case of this structure, the second solder 24 is filled in the region corresponding to the corner portion 44 of the rectangular semiconductor element 1.
－第４の実施形態－
　図１１は、本発明の半導体デバイスの要部である接合構造の第４の実施形態を示し、図１１（ａ）は、接合構造を上面からみた平面図であり、図１１（ｂ）は、図１１（ａ）のＸＩｂ－ＸＩｂ線断面模式図であり、図１１（ｃ）は、図１１（ａ）のＸＩｃ－ＸＩｃ線断面模式図である。なお、図１１（ａ）では、半導体素子１を透明とし、その外形を二点鎖線で示している。
　第４の実施形態の半導体デバイス１４の接合構造３０では、多孔質金属２１は、平面視で矩形形状の半導体素子１の４つのコーナー部に対応する領域のみに設けられている。つまり、多孔質金属２１は、半導体素子１の長辺に沿う第１辺と、半導体素子１の短辺に沿う第２辺と、第１辺と第２辺とを結ぶ斜辺である第３辺とを有する直角三角形形状を有する４つの多孔質金属部材２６ａ～２６ｄを有する。 -Fourth Embodiment-
FIG. 11 shows a fourth embodiment of the junction structure which is the main part of the semiconductor device of the present invention, FIG. 11(a) is a plan view of the junction structure seen from above, and FIG. 11(b) is 11A is a schematic sectional view taken along line XIb-XIb of FIG. 11A, and FIG. 11C is a schematic sectional view taken along line XIc-XIc of FIG. 11A. Note that, in FIG. 11A, the semiconductor element 1 is transparent, and its outer shape is shown by a chain double-dashed line.
In the junction structure 30 of the semiconductor device 14 of the fourth embodiment, the porous metal 21 is provided only in the regions corresponding to the four corners of the rectangular semiconductor element 1 in plan view. That is, the porous metal 21 has the first side along the long side of the semiconductor element 1, the second side along the short side of the semiconductor element 1, and the third side which is the oblique side connecting the first side and the second side. It has four porous metal members 26a-26d having a right triangle shape with and.
　多孔質金属部材２６ａ～２６ｄは、相互に離間して配置されており、各多孔質金属部材２６ａ～２６ｄの内側および外側には、第２のはんだ２４が形成されている。図１１（ｃ）に図示されるように、多孔質金属部材２６ａ～２６ｄは、それぞれ、空孔内に第１のはんだ２３が充填された充填部２３ａを有する。また、各多孔質金属部材２６ａ～２６ｄの上面と半導体素子１との間には第１のはんだ２３の上部側の表面接合部２３ｂが設けられ、各多孔質金属部材２６ａ～２６ｄの下面とリードフレーム３との間には第１のはんだ２３の下部側の表面接合部２３ｃが設けられている。そして、第２のはんだ２４は、第１のはんだ２３の上部側の表面接合部２３ｂと下部側の表面接合部２３ｃとに一体化されている。 The porous metal members 26a to 26d are arranged apart from each other, and the second solder 24 is formed inside and outside each of the porous metal members 26a to 26d. As shown in FIG. 11C, each of the porous metal members 26a to 26d has a filling portion 23a in which the first solder 23 is filled in the pores. Further, a surface joint portion 23b on the upper side of the first solder 23 is provided between the upper surface of each porous metal member 26a to 26d and the semiconductor element 1, and the lower surface of each porous metal member 26a to 26d and the lead. A surface joint 23c on the lower side of the first solder 23 is provided between the frame 3 and the frame 3. The second solder 24 is integrated with the upper surface joint portion 23b and the lower surface joint portion 23c of the first solder 23.
　このように、第４の実施形態においても、第１のはんだ２３の表面接合部２３ｂ、２３ｃが、厚さの大きい第２のはんだ２４により接続された構造を有する。このため、第１の実施形態と同様、第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂の進展が抑制され、半導体デバイス１４の信頼性を向上することができるという効果を奏する。 In this way, also in the fourth embodiment, the surface joint portions 23b and 23c of the first solder 23 are connected by the second solder 24 having a large thickness. Therefore, similarly to the first embodiment, the cracks in the surface joint portions 23b and 23c of the first solder 23 are suppressed from growing, and the reliability of the semiconductor device 14 can be improved.
　なお、第４の実施形態において、第２の実施形態と同様、リードフレーム３の一面にニッケルめっき層７を形成する構造としてもよい。ニッケルめっき層７によりＣｕ－Ｓｎ化合物の形成が阻止されるため、さらに第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂進展率が小さくなり、長寿命化を図ることができる。 Note that the fourth embodiment may have a structure in which the nickel plating layer 7 is formed on one surface of the lead frame 3 as in the second embodiment. Since the formation of the Cu—Sn compound is prevented by the nickel plating layer 7, the crack growth rate of the surface joint portions 23b and 23c of the first solder 23 is further reduced, and the life can be extended.
　また、第４の実施形態において、多孔質金属部材２６ａ～２６ｄが連結部により一体化された１つの部材として形成され、中央部に厚さ方向に貫通する貫通孔を有する部材としてもよい。 Further, in the fourth embodiment, the porous metal members 26a to 26d may be formed as one member integrated by the connecting portion, and may have a through hole penetrating in the thickness direction at the central portion.
－第５の実施形態－
　図１２（ａ）～（ｄ）は、第５の実施形態の半導体デバイスの接合構造の製造方法を示す工程図である。以下、図１２（ａ）～（ｄ）を参照して半導体デバイス１４の接合構造３０の製造方法を説明する。
　なお、以下の説明は、第１のはんだ２３と第２のはんだ２４とを同じ材料を用いて形成するものとする。
　図１２（ａ）に示されるように、予め、上段部２１ｂおよび下段部２１ａを有する段付き角柱形状の多孔質金属２１を形成しておき、この多孔質金属２１をリードフレーム３上に搭載する。 -Fifth Embodiment-
12A to 12D are process drawings showing the method for manufacturing the junction structure of the semiconductor device according to the fifth embodiment. Hereinafter, a method of manufacturing the junction structure 30 of the semiconductor device 14 will be described with reference to FIGS.
In the following description, the first solder 23 and the second solder 24 are formed by using the same material.
As shown in FIG. 12( a ), a stepped prismatic porous metal 21 having an upper step portion 21 b and a lower step portion 21 a is formed in advance, and this porous metal 21 is mounted on the lead frame 3. ..
　図１２（ｂ）に示されるように、多孔質金属２１の下段部２１ａよりも少し大きい平面サイズの開口部５２を有するマスク５１を多孔質金属２１上に配置し、スキージ５３を用いて印刷を行い、多孔質金属２１の上面および外周に、第１のはんだ２３（または第２のはんだ２４）にフラックスを混合したフラックス含有はんだ２２Ａを被着する。 As shown in FIG. 12B, a mask 51 having an opening 52 of a plane size slightly larger than the lower step portion 21a of the porous metal 21 is arranged on the porous metal 21, and printing is performed using a squeegee 53. Then, the flux-containing solder 22A in which the flux is mixed with the first solder 23 (or the second solder 24) is applied to the upper surface and the outer periphery of the porous metal 21.
　図１２（ｃ）に示されるように、マスク５１を取り除いて、多孔質金属２１上に半導体素子１を搭載する。マスク５１の開口５２は、半導体素子１の平面サイズとほぼ同一に形成されており、半導体素子１の外周側面がフラックス含有はんだ２２Ａの外周側面に一致するように位置を合わせる。
　そして、この状態でＮ２雰囲気のリフロー炉に投入して加熱し、フラックス含有はんだ２２Ａを溶融、凝固することにより図１２（ｄ）に示される接合構造３０を作製する。図１２（ｄ）の接合構造３０は、図４（ｂ）の接合構造３０と同一構造である。 As shown in FIG. 12C, the mask 51 is removed and the semiconductor element 1 is mounted on the porous metal 21. The opening 52 of the mask 51 is formed to have substantially the same size as the plane size of the semiconductor element 1, and is aligned so that the outer peripheral side surface of the semiconductor element 1 coincides with the outer peripheral side surface of the flux-containing solder 22A.
Then, in this state, the flux-containing solder 22A is put into a reflow furnace in an N 2 atmosphere and heated to melt and solidify the flux-containing solder 22A, thereby producing the joint structure 30 shown in FIG. The joint structure 30 of FIG. 12D is the same structure as the joint structure 30 of FIG. 4B.
　この後は、図示はしないが、実施例１と同様、半導体素子１とリードフレーム３とを、ボンディングワイヤ５により接続し、半導体素子１、ボンディングワイヤ５、接合部２およびリードフレーム３を、接続用リード１５のみが露出されるように封止して半導体デバイス１４を作製する。 After that, although not shown, the semiconductor element 1 and the lead frame 3 are connected by the bonding wire 5 and the semiconductor element 1, the bonding wire 5, the bonding portion 2 and the lead frame 3 are connected, although not shown. The semiconductor device 14 is manufactured by encapsulating so that only the lead 15 for use is exposed.
［実施例５］
　上記図１２（ａ）～（ｄ）に記載した方法により実施例５の半導体デバイス１４を作製した。
　実施例５の半導体デバイス１４の接合構造３０は、実施例１のはんだ２２をフラックス含有はんだ２２Ａに替えた以外はすべて実施例１と同一であり、多孔質金属２１は、空孔率８０％の銅により形成されている。 [Example 5]
A semiconductor device 14 of Example 5 was manufactured by the method described in FIGS. 12(a) to 12(d) above.
The junction structure 30 of the semiconductor device 14 of Example 5 is the same as that of Example 1 except that the solder 22 of Example 1 is replaced with the flux-containing solder 22A, and the porous metal 21 has a porosity of 80%. It is made of copper.
［比較例２］
　比較例２として、多孔質金属２１が、空孔率２０％の銅により形成されている以外は、すべて実施例５の半導体デバイスの製造方法と同じ製造方法を用いて比較例２の半導体デバイス（図示せず）を作製した。 [Comparative example 2]
As Comparative Example 2, the semiconductor device of Comparative Example 2 was manufactured using the same manufacturing method as that of the semiconductor device of Example 5 except that the porous metal 21 was formed of copper having a porosity of 20%. (Not shown) was prepared.
　図１３は、本発明の実施例５と比較例２のボイド率を示す図である。なお、図１３には、多孔質金属２１を用いない場合のボイド率も記載してある。
　図１３に示す通り、空孔率が２０％でＣｕの網目が密な比較例２の構造の接合部のボイド率は多孔質金属２１を含まない接合部のボイド率に比べて高かった。これに対し、実施例５の構造の接合部のボイド率は，多孔質金属２１を含まない接合部のボイド率と同等であった。この結果から、多孔質金属２１の空孔率が大きくなるとボイド率が小さくなる傾向が確認される。従って、空孔率が３０％以上の多孔質金属２１のボイド率は、多孔質金属２１の空孔率が２０％の場合のボイド率２５％より小さくなる。このボイド率は、実用に供して支障が無い。
　従って、各実施形態において、空孔率３０％以上の多孔質金属２１を用いることで、第１のはんだ２３の表面接合部２３ｂ、２３ｃのき裂の進展を抑制する効果と、ボイド率の発生を抑制する効果とを両立することができる。 FIG. 13 is a diagram showing the void ratios of Example 5 of the present invention and Comparative Example 2. Note that FIG. 13 also shows the void ratio when the porous metal 21 is not used.
As shown in FIG. 13, the void ratio of the joint of the structure of Comparative Example 2 in which the porosity was 20% and the Cu network was dense was higher than the void ratio of the joint not containing the porous metal 21. On the other hand, the void ratio of the joint portion of the structure of Example 5 was equivalent to the void ratio of the joint portion not including the porous metal 21. From this result, it is confirmed that the void ratio tends to decrease as the porosity of the porous metal 21 increases. Therefore, the void rate of the porous metal 21 having a porosity of 30% or more is smaller than the void rate of 25% when the porosity of the porous metal 21 is 20%. This void ratio has no problem in practical use.
Therefore, in each of the embodiments, by using the porous metal 21 having a porosity of 30% or more, the effect of suppressing the growth of cracks in the surface joint portions 23b and 23c of the first solder 23 and the occurrence of void ratio are obtained. It is possible to achieve both the effect of suppressing
　なお、空孔率が２０％の多孔質金属の骨格は、空孔率が８０％の多孔質金属の骨格より太く熱容量が大きい。本発明のごとく、フラックス成分を含有するペースト状のはんだを多孔質金属に印刷し、リフローすることで接合部を形成する場合，熱容量が大きいと気化したフラックス成分が未溶融のはんだに吸着することで、リフロー工程中に多孔質金属の網目から離脱せずボイドとして接合部に残存することでボイド率が高くなったと予測される。 Note that the skeleton of a porous metal having a porosity of 20% is thicker and has a larger heat capacity than the skeleton of a porous metal having a porosity of 80%. As in the present invention, when a paste-like solder containing a flux component is printed on a porous metal and a joint is formed by reflowing, when the heat capacity is large, the vaporized flux component is adsorbed by the unmelted solder. Therefore, it is estimated that the void rate increased because the voids did not separate from the mesh of the porous metal during the reflow process and remained as voids in the joint.
　なお、上記各実施形態では、半導体素子１を支持する支持部材として金属製のリードフレーム３を用いる構造として例示した。しかし、リードフレーム３に替えて、配線パターンや接続パッドが設けられた回路基板や、絶縁板等の基板を用いることができる。 In each of the above embodiments, the structure in which the metal lead frame 3 is used as the supporting member that supports the semiconductor element 1 is illustrated. However, instead of the lead frame 3, a circuit board provided with a wiring pattern or a connection pad, or a board such as an insulating board can be used.
　上記各実施形態では、第２のはんだ２４は、上下方向である厚さ方向の半導体素子１とリードフレーム３間全体に充填された大きい厚さを有する構造として例示した。しかし、第２のはんだ２４は、上・下部側の表面接合部２３ｂ、２３ｃの少なくとも一方に接続され、この表面接合部２３ｂ、２３ｃよりも厚く形成されていればよく、必ずしも、厚さ方向の半導体素子１とリードフレーム３間全体に充填されていなくてもよい。 In each of the above-described embodiments, the second solder 24 is illustrated as a structure having a large thickness filled in the entire space between the semiconductor element 1 and the lead frame 3 in the thickness direction which is the vertical direction. However, the second solder 24 is connected to at least one of the upper and lower surface joints 23b and 23c, and may be formed thicker than the surface joints 23b and 23c. The entire space between the semiconductor element 1 and the lead frame 3 may not be filled.
　上記実施形態では、第１のはんだ２３と第２のはんだ２４とを、同一の材料からなる、はんだとして例示した。しかし、第１のはんだ２３と第２のはんだ２４とを、異なる材料からなる、はんだとしてもよい。第１のはんだ２３と第２のはんだ２４とを異なる材料のはんだとするには、第１のはんだ２３を多孔質金属２１の空孔に充填した後、第２のはんだ２４を印刷等により多孔質金属２１の外表面に塗布し、リフロー等に投入して、溶融・凝固すればよい。 In the above embodiment, the first solder 23 and the second solder 24 are exemplified as the solder made of the same material. However, the first solder 23 and the second solder 24 may be solders made of different materials. In order to use different materials for the first solder 23 and the second solder 24, after filling the holes of the porous metal 21 with the first solder 23, the second solder 24 is made porous by printing or the like. It may be applied on the outer surface of the high-quality metal 21 and put into reflow or the like to melt and solidify.
　上記各実施形態や変形例を組み合わせてもよい。さらに、上記では、種々の実施の形態および変形例を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。 -The above embodiments and modifications may be combined. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other modes that can be considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.
　次の優先権基礎出願の開示内容は引用文としてここに組み込まれる。
　日本国特許出願２０１８－２４１１８６（２０１８年１２月２５日出願） The disclosure content of the following priority basic application is incorporated herein by reference.
Japanese patent application 2018-241186 (filed on December 25, 2018)
　　１　　　半導体素子（電子部品）
　　２　　　接合部
　　３　　　リードフレーム（基板）
　　４　　　樹脂
　　７　　　ニッケルめっき層
　１０　　　電子制御装置
　２１　　　多孔質金属
　２１ａ　　下段部
　２１ｂ　　上段部
　２２、２２Ａ　　　はんだ
　２３　　　第１のはんだ
　２３ａ　　充填部
　２３ｂ　　上部側の表面接合部
　２３ｃ　　下部側の表面接合部
　２４　　　第２のはんだ
　２４ａ　　領域
　２６ａ～２６ｄ　　　多孔質金属部材
　３０　　　接合構造
　４４　　　コーナー部 1 Semiconductor element (electronic component)
2 Joint 3 Lead frame (board)
4 Resin 7 Nickel Plating Layer 10 Electronic Control Device 21 Porous Metal 21a Lower Step 21b Upper Step 22, 22A Solder 23 First Solder 23a Filling Part 23b Upper Side Surface Joint 23c Lower Side Surface Joint 24 24 Second Solder 24a Area 26a-26d Porous metal member 30 Joining structure 44 Corner

Claims (13)

  1. 　電子部品と、
    　基板と、
    　前記電子部品と前記基板を接合する接合部とを備え、
    　前記接合部は、
    　連続する空孔を有する多孔質金属と、
    　前記多孔質金属の前記空孔に充填された充填部、前記電子部品と前記多孔質金属との間の少なくとも一部の領域と、前記基板と前記多孔質金属との間の少なくとも一部の領域との少なくとも一方に設けられた表面接合部とを有する第１のはんだと、
    　前記電子部品と前記基板間に設けられ、前記第１のはんだの前記表面接合部の側方側を覆うように第１のはんだと一体化された、前記一方の前記表面接合部より厚い第２のはんだと、を含む電子制御装置。     Electronic components,
    Board,
    Comprises a joint portion for joining the electronic component and the substrate,
    The joint is
    A porous metal having continuous pores,
    Filling part filled in the pores of the porous metal, at least a partial region between the electronic component and the porous metal, and at least a partial region between the substrate and the porous metal A first solder having a surface joint provided on at least one of
    A second thicker than the one surface joint portion provided between the electronic component and the substrate and integrated with the first solder so as to cover a lateral side of the surface joint portion of the first solder; And an electronic control device including the solder.
  2. 　請求項１に記載の電子制御装置において、
    　前記基板はリードフレームである電子制御装置。     The electronic control device according to claim 1,
    An electronic control unit in which the substrate is a lead frame.
  3. 　請求項１に記載の電子制御装置において、
    　前記基板の前記多孔質金属と対向する面に、ニッケルめっき層が形成されている電子制御装置。     The electronic control device according to claim 1,
    An electronic control device in which a nickel plating layer is formed on a surface of the substrate facing the porous metal.
  4. 　請求項１に記載の電子制御装置において、
    　前記第１のはんだと前記第２のはんだとは、同じ材料で形成されている電子制御装置。     The electronic control device according to claim 1,
    The electronic control device in which the first solder and the second solder are formed of the same material.
  5. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属の平面視での面積は、前記基板対向側と前記電子部品対向側で異なる電子制御装置。     The electronic control device according to claim 1,
    An electronic control device in which the area of the porous metal in plan view differs between the substrate facing side and the electronic component facing side.
  6. 　請求項５に記載の電子制御装置において、
    　前記多孔質金属の平面視での面積は、前記基板対向側の方が前記電子部品対向側よりも大きい電子制御装置。     The electronic control unit according to claim 5,
    The area of the porous metal in plan view is larger on the substrate facing side than on the electronic component facing side.
  7. 　請求項１に記載の電子制御装置において、
    　前記第２のはんだは、前記多孔質金属の周側面を覆って形成されている電子制御装置。     The electronic control device according to claim 1,
    An electronic control unit in which the second solder is formed to cover a peripheral side surface of the porous metal.
  8. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属は、少なくとも１つのコーナー部を有する五角形以上の多辺形形状を有し、
    　前記第２のはんだは、前記多孔質金属の前記コーナー部に充填されている電子制御装置。     The electronic control device according to claim 1,
    The porous metal has a pentagonal or more polygonal shape having at least one corner portion,
    The electronic control unit in which the second solder is filled in the corner portion of the porous metal.
  9. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属は、円または楕円形状を有し、
    　前記第２のはんだは、矩形形状の前記電子部品の各コーナー部に対応する領域に充填されている電子制御装置。     The electronic control device according to claim 1,
    The porous metal has a circular or elliptical shape,
    An electronic control unit in which the second solder is filled in regions corresponding to the respective corners of the rectangular electronic component.
  10. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属は、厚さ方向に貫通する中空部を有し、
    　前記第２のはんだは、前記多孔質金属の前記中空部内に充填されている電子制御装置。     The electronic control device according to claim 1,
    The porous metal has a hollow portion that penetrates in the thickness direction,
    An electronic control unit in which the second solder is filled in the hollow portion of the porous metal.
  11. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属は、銅、ニッケルの少なくとも１つを含む金属または合金からなる電子制御装置。     The electronic control device according to claim 1,
    The said porous metal is an electronic controller which consists of a metal or alloy containing at least 1 of copper and nickel.
  12. 　請求項１に記載の電子制御装置において、
    　前記多孔質金属の空孔率は、３０％以上である電子制御装置。     The electronic control device according to claim 1,
    An electronic control unit in which the porosity of the porous metal is 30% or more.
  13. 　請求項１に記載の電子制御装置において、
    　前記電子部品と、前記接合部と、前記接合部により前記電子部品に接合された少なくとも前記基板の領域とを封止する樹脂をさらに備える電子制御装置。     The electronic control device according to claim 1,
    An electronic control device further comprising: a resin that seals the electronic component, the bonding portion, and at least a region of the substrate bonded to the electronic component by the bonding portion.
PCT/JP2019/035789 2018-12-25 2019-09-11 Electronic control device WO2020137025A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003203932A (en) * 2002-01-07 2003-07-18 Sanken Electric Co Ltd Semiconductor device and manufacturing method thereof
WO2012081167A1 (en) * 2010-12-15 2012-06-21 日立オートモティブシステムズ株式会社 Semiconductor device and method for manufacturing same
JP2014003339A (en) * 2013-10-07 2014-01-09 Hitachi Ltd Semiconductor device and connection structure, and manufacturing methods thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003203932A (en) * 2002-01-07 2003-07-18 Sanken Electric Co Ltd Semiconductor device and manufacturing method thereof
WO2012081167A1 (en) * 2010-12-15 2012-06-21 日立オートモティブシステムズ株式会社 Semiconductor device and method for manufacturing same
JP2014003339A (en) * 2013-10-07 2014-01-09 Hitachi Ltd Semiconductor device and connection structure, and manufacturing methods thereof

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