JPH09153519A - Structure for mounting semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure for mounting a semiconductor with excellent reliability and productivity. SOLUTION: In a semiconductor device 14 with which solder bumps 8 arranged on an IC chip 5 are connected by face-down bonding to the IC connecting electrodes 2 of a circuit board 1, the shapes of the solder bump connecting parts are without the shape of lands but long and narrow with fixed width. The surface of it is electroless plated with Au and formed with porous flash Au plating layer 7a. By applying no cleansing type flux 13 with the chlorine content of 0.05% or less on the side of the solder bump 8 partially and reflowing the solder bump 8 in the atmosphere, the solder is held inside the solder bump connecting part and the distance between the IC chip 5 and the surface of the circuit board 1 is kept constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting structure, and more particularly to a flip chip bonding semiconductor mounting structure for mounting an IC chip directly on a circuit board face down.

[0002]

2. Description of the Related Art In recent years, with the high-density mounting of IC chips,
A resin-sealed semiconductor device having a large number of electrodes has been developed. As a typical example thereof, there is a PGA (pin grid array). Although the PGA has an advantage that it can be attached to and detached from a mother board, it has a problem that it has a large size because it has a pin and it is difficult to miniaturize it.

Therefore, a BGA (ball grid array) which is smaller and has a higher density has been developed in place of the PGA. Furthermore, in the BGA, as a technique for improving reliability and productivity of conventional wire bonding, IC
A flip chip bonding technique for mounting a chip directly on a circuit board is disclosed in JP-A-6-349983. The outline will be described below with reference to the drawings.

3 and 4 show a mounting structure of a conventional face-down bonding (hereinafter abbreviated as FDB) BGA, FIG. 3 is a cross-sectional view of a main portion, and FIG. 4 is a partial plan view thereof. In FIGS. 3 and 4, the circuit board 1 is a substantially rectangular resin board made of glass epoxy resin or the like with copper foils on both upper and lower surfaces, and a plurality of through holes are formed in the resin board by means such as a cutting drill. After cleaning the substrate surface including the wall surface of the through hole, a copper plating layer is formed on the entire surface of the resin substrate by electroless plating and electrolytic plating, and the copper plating layer is applied to the inside of the through hole.

Further, a plating resist is laminated, exposed and developed to form a pattern mask, and then pattern etching is performed using an etching solution to form the IC connection electrodes 2 on the upper surface side and the matrix on the lower surface side. The external connection electrode 3 is formed in a shape. A circular land portion 2a is formed at the solder bump connecting portion at the tip of the lead electrode that becomes the IC connecting electrode 2. Next, a solder resist process is performed to form a resist film 4 on a predetermined portion, thereby forming an opening on the upper surface side of the resin substrate, which is slightly larger than the portion on which the IC chip 5 is mounted, and the lead electrode. The resist film 4 is formed so that the vicinity of the tip is exposed, and the exposed lead electrode has a surface of Ni of about 2 to 5 μm.
The plating layer 6 is applied, and the Ni plating layer 6 is coated with 0.
A Ni-Au plated layer having an Au plated layer 7 of about 5 μm is formed. The circuit board 1 is completed by forming a large number of resist film openings which are solderable surfaces of the same shape in a matrix so as to expose the external connection electrodes 3 on the lower surface side.

Solder bumps 8 are formed on the IC chip 5 in advance, and the solder bumps 8 are used for the IC connecting electrodes 2.
Is positioned on the land portion 2a of the lead electrode via flux, the solder bump 8 is melted by reflow, and the IC chip 5 is fixed to the land portion 2a of the lead electrode.

Since the solder bump 8 has the constricted portion 2c formed in the shape of the land portion 2a of the lead electrode, the flow of the melted solder bump 8 is suppressed by the shape effect and does not flow out of the land portion 2a. The solder bump 8 rises to a certain height on the land 2a,
The distance between the surface of the circuit board 1 and the surface of the circuit board 1 can be kept constant.

As shown in FIG. 3, with the upper surface side of the IC chip 5 exposed, the gap between the IC chip 5 and the circuit board 1 is filled with a sealing resin 9 to cover the opening of the resist film 4. By side potting as described above, the side wall of the opening of the resist film 4 prevents the sealing resin 9 from flowing.
The IC chip 5 is integrally fixed to the circuit board 1.

At the position of the external connection electrode 4 formed on the lower surface side of the circuit board 1, a solder ball 10 having a solder composition whose melting point is lower than that of the flip chip solder bump 8 on the IC chip 5 side. To place. The solder composition is
For example, the solder bump 8 of the flip chip has Pb: 90.
%, Sn: 10%, so-called 9/1 solder having a melting point of 301 ° C., and the solder ball forming the solder ball electrode 10 is S
n: 60%, Pb: 40%, melting point 183 ° C, so-called 6 /
It is general that four solders each having a different melting point are used. The solder ball electrode 10 is formed by
For example, reflow may be performed again at a low temperature of 210 to 230 ° C. Therefore, the solder bumps 8 on the IC chip 5 side are higher than the melting point of the solder ball electrodes 10 and do not melt. The semiconductor device 11 which is FDB by the above
Is completed.

In the semiconductor device 11 described above, the constriction 2c is formed in the shape of the land 2a of the lead electrode to limit the wetting and spreading of the solder, and thereby the height of the solder bump 8 can be controlled. However, with the miniaturization and high-density mounting of the IC chip 5, it is required to increase the number of lead electrodes corresponding to the IC chip 5 having a large number of pins with a narrow pitch between the solder bumps 8. However, it was difficult to simply increase the number of lead electrodes because the land 2a had a circular shape. That is, the land portion 2a must be formed in a circular shape having a diameter larger than the width of the lead-out portion of the lead electrode in order to limit the spread of the solder. Even if the number of lead electrodes is increased by narrowing the width of the lead-out portions, the number of lead electrodes in a unit length is limited by the size of the land portion 2a. Chip F is simply F
It was difficult to make a DB.

Therefore, a conventional FD that solves the above problems
A semiconductor device presented as a B structure is shown in FIG. FIG.
Is a sectional view of a main part, and FIG. 6 is a plan view thereof. 5 and 6, the solder bump connecting portion at the tip of the lead electrode which becomes the IC connecting electrode 2 is formed with the same width as the lead portion. The first resist film 4a is formed by performing a solder resist process so that only the solder bump connecting portions 2b of the lead electrodes are exposed on the upper surface of the circuit board 1 to limit the solder flow of the solder bumps 8 described later. Further, on the first resist film 4a having a solder flow preventing function, there is an opening slightly larger than the portion where the IC chip 5 is mounted, so that the flow of the sealing resin 9 is prevented and the pattern is protected. A second resist film 4 is formed. On the surface of the exposed lead electrode, a Ni-plated layer 6 and an Au-plated layer 7 are formed.
The formation of the Au plating layer is the same as in the above-mentioned conventional technique.

Next, similarly to the above, the solder bumps 8 are formed on the IC chip 5 in advance, the solder bumps 8 are positioned on the solder bump connecting portions 2b of the lead electrodes through the flux, and the solder bumps 8 are reflowed. Is melted and the IC chip 5 is fixed to the solder bump connecting portion 2b. The solder bump 8 does not flow out of the tip portion of the lead electrode due to the first resist film 4a, but rises to a certain height at the tip portion and keeps a constant distance between the IC chip 5 and the surface of the circuit board 1. You can Further, the IC chip 5 is sealed with resin and the solder ball electrode 10 is formed on the lower surface of the circuit board 1 to complete the semiconductor device 12 having the FDB structure.

[0013]

However, the above-mentioned semiconductor device has the following problems. That is, IC
The IC chip 5 with a narrow pitch can be FDB within a range where the distance between the lead electrodes of the connection electrode 2 can be narrowed, and the demand for miniaturization and high density of the IC chip can be met. Since the step of forming the first resist film 4a for preventing the flow of the solder bumps 8 is increased, the steps are complicated and the cost is increased.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a semiconductor mounting structure which is excellent in reliability and productivity of the semiconductor mounting structure.

[0015]

To achieve the above object, in a semiconductor device according to the present invention, a solder bump provided on an IC chip is face-down bonded to an IC connecting electrode formed on an upper surface of a circuit board. In the semiconductor device described above, the shape of the solder bump connecting portion of the IC connecting electrode is an elongated shape having a substantially constant width without a land shape, and electroless displacement Au plating is performed on the IC connecting electrode. In addition to forming a porous Au plating layer, the solder bumps are heated and melted in the atmosphere and connected by using a non-cleaning type flux.

The non-cleaning type flux is characterized in that the chlorine content is 0.05 wt% or less.

The flux is partially adhered to the solder bump side.

Therefore, in the semiconductor mounting structure obtained by the present invention, as described above, the shape of the solder bump connecting portion of the IC connecting electrode does not have a land shape but is an elongated shape having a substantially constant width, The pitch between the bumps can be narrowed to correspond to an IC chip having a large number of pins, so that the pitch between the lead electrodes of the IC connection electrodes can be narrowed to a limit that can be narrowed. Further, the electroless substitution gold plating treatment is performed on the IC connection electrode to form a porous gold plating layer, so that the wetting and spreading of the solder can be suppressed. At the same time, the chlorine content of the flux is small by partially adhering the non-cleaning type flux having a chlorine content of 0.05% or less to the solder bump side and reflowing the solder bump in the atmosphere. The flow of the molten solder can be suppressed and the distance between the IC chip and the surface of the circuit board can be maintained at a constant interval.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor mounting structure according to the present invention will be described below with reference to the drawings. FIG. 1 is a preferred embodiment of the present invention, and FIG. 1 and FIG.
FIG. 2B is a sectional view of a main part of the GA and a plan view thereof, and FIG. 2B is a sectional view of the IC chip. The same members as those in the prior art are denoted by the same reference numerals.

First, in FIG. 1, the shape of the solder bump connecting portion of the IC connecting electrode 2 on the upper surface of the circuit board 1 is not a land shape but an elongated shape having a substantially constant width.
The pitch between the solder bumps is narrowed to correspond to the IC chip 5 having a large number of pins, and the pitch between the lead electrodes of the IC connection electrode 2 is narrowed to the limit that can be narrowed, as in the above case. . Next, a solder resist process is performed to form a resist film 4 on a predetermined portion. That is, an opening slightly larger than the portion where the IC chip 5 is mounted is formed on the upper surface side of the resin substrate, and the resist film 4 is formed so that the vicinity of the tip of the lead electrode is exposed. Ni is formed on the surface of the exposed solder bump connecting portion 2b of the lead electrode.
The flash Au plating layer 7a having a thickness of about 0.05 μm is formed by applying the plating layer 6a, and further by electroless displacement Au plating in order to improve conductivity on the Ni plating layer 6a.
To form Here, the electroless displacement Au plating means Au.
The metallic Ni in the ionic solution exchanges electrons with each other due to the difference in the ionization tendency between Au and Ni, Au particles are deposited on the surface of Ni, and Ni becomes ions and is eluted in the solution.
Therefore, the deposited Au surface is essentially porous and Ni is exposed. The locations where the Au particles are deposited on the Ni surface are completely random, and there is always a porous surface into which Ni is eluted.

Next, referring to FIG. 2B, the IC chip 5
In this case, a plurality of solder bumps 8 are formed in advance, and the IC chip 5 is handled to partially apply an appropriate amount of the non-cleaning type flux 13 to the plurality of solder bumps 8 at the same time. It goes without saying that applying the flux to the solder bump 8 side of the IC chip 5 is much easier than applying it to the IC connecting electrode 2 side of the circuit board 1 and can apply a fixed amount. The non-cleaning type flux 13 has a chlorine content of 0.05% or less.

The solder bumps 8 of the IC chip 5 are positioned on the solder bump connecting portions 2b of the IC connecting electrodes 2 of the circuit board 1 through the non-cleaning type flux 13 and reflowed in the atmosphere, so that the solder bumps 8 are formed. Is melted and the IC chip 5 is fixed to the solder bump connecting portion 2b. On this occasion,
By reflowing in the atmosphere instead of in the atmosphere of an inert gas, the flow of solder is suppressed, and at the same time, the chlorine content is reduced to 0.05% or less in the non-cleaning type flux 13 to reduce the flow of solder. When the solder bumps 8 are heated and melted, the Au particles described above can be suppressed to Ni.
It is possible to keep the distance between the IC chip 5 and the surface of the circuit board 1 at a constant distance without flowing out of the solder bump connecting portion 2b having a porous surface deposited on the surface.
Furthermore, since the chlorine content is low, a cleaning process is not required after the IC chip 5 is fixed to the circuit board 1. It should be noted that when the chlorine content of the flux is 0.05% or more, the flow of the solder is improved, and the molten solder flows out even if the surface of the solder bump connection portion 2b is porous. Cannot be kept at regular intervals.

Further, similarly to the above, the FDB structure semiconductor device 14 is completed by sealing the IC chip 5 with resin and forming the solder ball electrode 10 on the lower surface of the circuit board 1.

As described above, the feature of this embodiment is that the pitch between solder bumps is narrowed and the number of pins is large.
Corresponding to the C chip 5, the IC connection electrode 2 of the circuit board 1
The lead electrode surface exposed by the resist film 4 is made into a porous Au plate by electroless displacement Au plating with a narrow pitch within a range where the space between the lead electrode members can be narrowed.
The plating layer 7a is formed, the non-cleaning type flux 13 is applied to the solder bump 8 side, and the reflow is performed in the atmosphere for connection. In this embodiment, the BGA in which the IC chip is mounted on the circuit board by the FDB has been described, but it goes without saying that it can be applied to the PGA.

[0025]

As described above, according to the present invention,
In order to meet the demand for miniaturization and high density, the pitch of the IC connecting electrodes of the circuit board is set to a narrow pitch to the limit so that the number of lead electrodes per unit length is increased, An electrode for IC connection is formed by applying a flux having a minimum chlorine content to the solder bump side on the porous surface formed in the solder bump connection portion to make the solder flow condition such as reflow in the atmosphere suppressed. The molten solder does not flow out from the solder bump connection portion of. Therefore, the solder rises to a constant height, and the IC chip and the surface of the circuit board can be connected while maintaining a constant distance. Further, since the chlorine content of the flux is small, a cleaning process is not required after fixing the IC chip to the circuit board. Further, the step of forming the first resist film for preventing the flow of the melted solder bumps as described in the prior art becomes unnecessary.
Also, the application of the flux should be on the solder bump side,
Also, since the atmosphere for reflow is in the atmosphere, both work efficiency is good. As described above, it is possible to provide a semiconductor mounting structure that is compatible with downsizing and speeding up of an IC and has excellent reliability and productivity.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of essential parts showing a mounting structure of a face-down bonding BGA according to an embodiment of the present invention.

FIG. 2A is a plan view showing a mounting structure of a face-down bonding BGA according to the embodiment of the present invention, and FIG. 2B is a sectional view of an IC chip.

FIG. 3 is a cross-sectional view of essential parts showing a mounting structure of a face-down bonding BGA of a conventional example.

FIG. 4 is a plan view showing a mounting structure of a conventional face-down bonding BGA.

FIG. 5: Prior art face down bonding BGA
FIG. 3 is a cross-sectional view of an essential part showing the mounting structure of FIG.

FIG. 6 is a conventional face-down bonding BGA.
3 is a plan view showing the mounting structure of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit board 2 IC connection electrode 2b Solder bump connection part 2c Constriction part 3 External connection electrode 4 Resist film 5 IC chip 6a Ni plating layer 7a Flash Au plating layer 8 Solder bump 9 Encapsulating resin 13 Non-cleaning type flux 14 Face Down bonding BGA

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Ishida 6-12 Hommachi Honmachi, Tanashi City, Tokyo Citizen Watch Co., Ltd. Tanashi Factory

Claims (3)

[Claims] 1. A semiconductor device in which a solder bump provided on an IC chip is face-down bonded to an IC connecting electrode formed on an upper surface of a circuit board, wherein the IC
The solder bump connection portion of the connection electrode has an elongated shape having a substantially constant width without a land shape, and a porous Au plating layer is obtained by subjecting the IC connection electrode to electroless displacement Au plating. And the solder bumps are heated and melted in the air and connected by using a non-cleaning type flux. 2. The semiconductor mounting structure according to claim 1, wherein the non-cleaning type flux has a chlorine content of 0.05 wt% or less. 3. The semiconductor mounting structure according to claim 2, wherein the flux partially adheres to the solder bump side.