JP6416291B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6416291B2 JP6416291B2 JP2016570414A JP2016570414A JP6416291B2 JP 6416291 B2 JP6416291 B2 JP 6416291B2 JP 2016570414 A JP2016570414 A JP 2016570414A JP 2016570414 A JP2016570414 A JP 2016570414A JP 6416291 B2 JP6416291 B2 JP 6416291B2
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- 239000004065 semiconductor Substances 0.000 title claims description 813
- 238000004519 manufacturing process Methods 0.000 title claims description 107
- 229920005989 resin Polymers 0.000 claims description 156
- 239000011347 resin Substances 0.000 claims description 156
- 239000000463 material Substances 0.000 claims description 153
- 238000007789 sealing Methods 0.000 claims description 131
- 238000000034 method Methods 0.000 claims description 116
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 230000008054 signal transmission Effects 0.000 claims description 25
- 238000003860 storage Methods 0.000 claims description 20
- 238000005520 cutting process Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 description 39
- 239000010410 layer Substances 0.000 description 30
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 18
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 18
- 230000006870 function Effects 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 17
- 238000000465 moulding Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 10
- 239000000523 sample Substances 0.000 description 9
- 239000000725 suspension Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 230000002265 prevention Effects 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011162 core material Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000004305 biphenyl Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
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- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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Description
<半導体装置(半導体パッケージ)の全体構造について>
図1は、本発明の一実施の形態である半導体装置PKGの上面図であり、図2〜図4は、半導体装置PKGの平面透視図であり、図5は、半導体装置PKGの断面図である。図2には、封止部MRを透視したときの半導体装置PKGの上面側の平面透視図が示されている。また、図3は、図2において、更にワイヤBWを透視(省略)したときの半導体装置PKGの上面側の平面透視図が示され、図4は、図3において、更に半導体チップCPを透視(省略)したときの半導体装置PKGの上面側の平面透視図が示されている。なお、図2〜図4では、封止部MRの外周の位置を点線で示してある。また、図1〜図4のA−A線の位置での半導体装置PKGの断面が、図5にほぼ対応している。
次に、上記図1〜図5に示される半導体装置PKGの製造工程について説明する。図6は、上記図1〜図5に示される半導体装置PKGの製造工程を示すプロセスフロー図である。図7は、図6のプロセスフローのうち、ステップS4の組み立て工程の詳細を示すプロセスフロー図である。また、図8〜図19は、半導体装置PKGの製造工程を説明するための平面図または断面図である。
次に、本発明者が行った検討の背景について説明する。
図25は、半導体チップCPの回路構成を示す回路ブロック図である。
図26〜図28は、図25の半導体チップCPを用いて半導体パッケージ(PKG)を製造した場合の回路構成を示す回路ブロック図である。このうち、図26は、224ピンの半導体パッケージ(PKG)を製造した場合に対応し、図27および図28は、100ピン、144ピンまたは176ピンの半導体パッケージ(PKG)を製造した場合に対応している。なお、図27の場合は、本実施の形態の技術思想を適用しておらず、一方、図28の場合は、本実施の形態の技術思想を適用している。
次に、上述した本実施の形態の技術思想に伴う半導体装置(PKG)の主要な特徴について、図31を参照して説明する。図31は、本実施の形態の半導体装置PKGを概念的に示す説明図である。
図32は、上記ステップS4dの樹脂封止工程を示す平面図であり、上記図12と同じ平面領域が示されている。図32において、矢印で示されているのは、樹脂封止工程で金型KG1,KG2のキャビティCAV内に上記樹脂材料MR1を注入したときの、キャビティCAV内を進行する樹脂材料MR1の進行方向に対応している。この進行方向が、上述した樹脂進行方向YG1,YG2,YG3,YG4,YG5,YG6に対応している。樹脂封止工程においては、金型(KG1,KG2)に設けられたゲート(樹脂注入口)GTから、金型(KG1,KG2)のキャビティ(CAV)内に、封止部MR形成用の樹脂材料MR1を注入する。ゲートGTからキャビティ(CAV)内に注入された樹脂材料MR1は、図32の矢印の方向に進行して、キャビティ(CAV)内を充填し、その後、加熱などにより樹脂材料MR1を硬化させることで、封止部MRが形成される。
上記実施の形態1では、リードフレームを用いて半導体装置PKGを製造していたが、本実施の形態2では、配線基板を用いて半導体装置PKGを製造している。
また、図34では、上記図33と同様に、半導体チップCPが有する複数のパッド電極PDのうち、有効パッドとなっているパッド電極PDを、白抜きの四角(□)で示し、無効パッド(未使用パッド)となっているパッド電極PDを、黒塗りの四角(■)で示してある。
2 制御回路部
2a,2b,2c,2d 選択回路
2e 論理回路部
3 デコーダ回路部
4 記憶回路部
5 内部回路部
5a,5b,5c,5d 内部回路
BD 接合材
BW,BW1,BW1a,BW1b,BW1c,BW2,BW3,BW3a,BW3b,BW3c,BW4,BW5,BW5a,BW5b,BW5c ワイヤ
CAV キャビティ
CP 半導体チップ
DP ダイパッド
GT ゲート
GTK 樹脂注入痕
KG1,KG2 金型
LD,LD1,LD1a,LD1b,LD1c,LD2,LD3,LD3a,LD3b,LD3c,LD4 リード
MR 封止部
MR1 樹脂材料
PD,PD1,PD1a,PD1b,PD1c,PD2,PD2a,PD2b,PD2c,PD3,PD3a,PD3b,PD3c,PD4 パッド電極
PKG,PKG1 半導体装置(半導体パッケージ)
SW,SW1,SW2,SW3,SW4 スイッチ回路部
TL 吊りリード
Claims (13)
- 第1内部回路と第2内部回路とスイッチ回路部とを含み、第1電極と第2電極とが形成された主面を有する半導体チップと、
前記半導体チップの周囲に配置された第1外部端子と、
前記第1電極と前記第1外部端子とを電気的に接続する第1ワイヤと、
前記第2電極と前記第1外部端子とを電気的に接続する第2ワイヤと、
前記半導体チップと、前記第1ワイヤと、前記第2ワイヤと、を樹脂で封止する封止体と、
を有する半導体装置であって、
前記第2電極は、前記第2内部回路と電気的に接続され、前記第2内部回路と前記第2電極との間で信号の伝送が可能であり、
前記スイッチ回路部は、前記第1内部回路と前記第1電極との間で信号の伝送が可能な第1状態と、前記第1内部回路と前記第1電極との間で信号の伝送が不可能な第2状態と、を設定可能な回路であり、
前記半導体装置の動作中は、前記スイッチ回路部は、前記第2状態に固定されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1外部端子と前記半導体チップとの間で、前記第2電極および前記第2ワイヤを介して信号が伝送されるが、前記第1電極および前記第1ワイヤを介しては、信号は伝送されない、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体チップは、記憶回路部を含み、
前記記憶回路部は、前記スイッチ回路部と電気的に接続され、
前記記憶回路部に記憶された情報に基づいて、前記スイッチ回路部は前記第2状態に固定されている、半導体装置。 - 請求項3記載の半導体装置において、
前記スイッチ回路部は、制御回路部と、前記第1電極に接続された第1入出力回路部とを含み、
前記記憶回路部に記憶された前記情報に基づいて、前記制御回路部によって前記第1入出力回路部を制御することにより、前記スイッチ回路部が前記第2状態に固定されている、半導体装置。 - 請求項4記載の半導体装置において、
前記半導体チップは、デコーダ回路部を更に含み、
前記記憶回路部に記憶された前記情報が、前記デコーダ回路部で信号に変換され、前記デコーダ回路部で変換された前記信号が、前記制御回路部に入力され、前記制御回路部に入力された前記信号に基づいて前記制御回路部が前記第1入出力回路部を制御することにより、前記スイッチ回路部が前記第2状態に固定されている、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体チップの前記主面に形成された第3電極と、
前記半導体チップの周囲に配置された第2外部端子と、
前記第3電極と前記第2外部端子とを電気的に接続する第3ワイヤと、
を更に有し、
前記第3電極は、前記半導体チップの第3内部回路と電気的に接続され、前記第3内部回路と前記第3電極との間で信号の伝送が可能であり、
平面視において、前記第1電極と前記第2電極と前記3電極とは、前記半導体チップの前記主面の第1辺に沿って配置され、
前記第1電極は、前記第2電極と前記第3電極との間に配置されている、半導体装置。 - 請求項6記載の半導体装置において、
前記半導体チップの前記主面に形成された第4電極と、
前記半導体チップの周囲に配置された第3外部端子と、
前記第4電極と前記第3外部端子とを電気的に接続する第4ワイヤと、
を更に有し、
前記第4電極は、前記半導体チップの第4内部回路と電気的に接続され、前記第4内部回路と前記第4電極との間で信号の伝送が可能であり、
平面視において、前記第4電極は、前記半導体チップの前記主面の前記第1辺に沿って配置され、
前記第2電極は、前記第4電極と前記第1電極との間に配置されている、半導体装置。 - 請求項7記載の半導体装置において、
前記半導体チップの主面に形成された複数の第5電極、
を更に有し、
平面視において、前記複数の第5電極は、前記半導体チップの前記主面の前記第1辺に沿って配置され、
前記複数の第5電極は、前記第1電極と前記第2電極との間、および、前記第1電極と前記第3電極との間に配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記封止体は、樹脂注入痕を有し、
前記第2ワイヤよりも前記第1ワイヤが、前記樹脂注入痕に近い位置にある、半導体装置。 - 半導体装置の製造方法であって、
(a)第1内部回路と第2内部回路と記憶回路部とスイッチ回路部とを含み、第1電極と第2電極とが形成された主面を有する半導体チップを用意する工程、
(b)前記半導体チップをチップ搭載部上に搭載する工程、
(c)前記半導体チップの前記第1電極と前記チップ搭載部の周囲に配置された第1外部端子とを第1ワイヤを介して電気的に接続し、前記半導体チップの前記第2電極と前記第1外部端子とを第2ワイヤを介して電気的に接続する工程、
(d)前記半導体チップと、前記第1ワイヤと、前記第2ワイヤと、を樹脂で封止し、樹脂封止部を形成する工程、
(e)前記半導体チップの前記記憶回路部に第1情報を記憶させる工程、
を有し、
前記第2電極は、前記第2内部回路と電気的に接続され、前記第2内部回路と前記第2電極との間で信号の伝送が可能であり、
前記スイッチ回路部は、前記第1内部回路と前記第1電極との間で信号の伝送が可能な第1状態と、前記第1内部回路と前記第1電極との間で信号の伝送が不可能な第2状態と、を設定可能な回路であり、
前記(e)工程後、前記記憶回路部に記憶された前記第1情報に基づいて、前記半導体装置の動作中は、前記スイッチ回路部は前記第2状態に固定されている、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(e)工程は、前記(d)工程の後に行われる、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(a)工程は、
(a1)複数のチップ領域を有する半導体ウエハを用意する工程、
(a2)前記半導体ウエハを切断して前記半導体チップを取得する工程、
を有し、
前記(a1)工程で用意された前記半導体ウエハの前記複数のチップ領域のそれぞれは、前記スイッチ回路部と、前記第1内部回路と、前記第2内部回路と、前記記憶回路部と、前記第1電極と、前記第2電極と、を有し、
前記(e)工程は、前記(a1)工程後で、前記(a2)工程前に行われる、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(d)工程は、
(d1)前記半導体チップと、前記第1ワイヤと、前記第2ワイヤと、前記チップ搭載部と、前記第1外部端子の少なくも一部とを、金型のキャビティ内に配置する工程、
(d2)前記(d1)工程後、前記金型の前記キャビティ内に、前記樹脂封止部用の樹脂材料を注入する工程、
を有し、
前記(d2)工程では、前記金型の前記キャビティ内に注入された前記樹脂材料は、前記第1ワイヤに接した後に前記第2ワイヤに接する、半導体装置の製造方法。
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