JP6340200B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP6340200B2
JP6340200B2 JP2014012301A JP2014012301A JP6340200B2 JP 6340200 B2 JP6340200 B2 JP 6340200B2 JP 2014012301 A JP2014012301 A JP 2014012301A JP 2014012301 A JP2014012301 A JP 2014012301A JP 6340200 B2 JP6340200 B2 JP 6340200B2
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region
main surface
type
semiconductor substrate
semiconductor device
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JP2014012301A
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Japanese (ja)
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JP2015141925A (ja
JP2015141925A5 (https=
Inventor
浩介 吉田
浩介 吉田
新田　哲也
哲也 新田
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2014012301A priority Critical patent/JP6340200B2/ja
Priority to US14/605,027 priority patent/US9356135B2/en
Priority to CN201510039267.6A priority patent/CN104810365B/zh
Publication of JP2015141925A publication Critical patent/JP2015141925A/ja
Publication of JP2015141925A5 publication Critical patent/JP2015141925A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/663—Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

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  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2014012301A 2014-01-27 2014-01-27 半導体装置およびその製造方法 Active JP6340200B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014012301A JP6340200B2 (ja) 2014-01-27 2014-01-27 半導体装置およびその製造方法
US14/605,027 US9356135B2 (en) 2014-01-27 2015-01-26 Semiconductor device and method of manufacturing the same
CN201510039267.6A CN104810365B (zh) 2014-01-27 2015-01-27 半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014012301A JP6340200B2 (ja) 2014-01-27 2014-01-27 半導体装置およびその製造方法

Publications (3)

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JP2015141925A JP2015141925A (ja) 2015-08-03
JP2015141925A5 JP2015141925A5 (https=) 2016-12-28
JP6340200B2 true JP6340200B2 (ja) 2018-06-06

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JP2014012301A Active JP6340200B2 (ja) 2014-01-27 2014-01-27 半導体装置およびその製造方法

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US (1) US9356135B2 (https=)
JP (1) JP6340200B2 (https=)
CN (1) CN104810365B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6920137B2 (ja) * 2017-08-31 2021-08-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
EP3627559B1 (en) * 2018-09-19 2022-06-22 Imec Vzw A iii-v semiconductor device and a method for forming a iii-v semiconductor device comprising an edge termination structure
CN109244140A (zh) * 2018-09-29 2019-01-18 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法
CN110120423B (zh) * 2019-05-05 2022-03-22 南京邮电大学 一种ldmos器件及其制备方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
JP3641547B2 (ja) 1998-03-25 2005-04-20 株式会社豊田中央研究所 横型ｍｏｓ素子を含む半導体装置
JP3987251B2 (ja) * 1999-05-21 2007-10-03 関西電力株式会社 半導体装置
US6593619B1 (en) * 1999-06-03 2003-07-15 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6835993B2 (en) * 2002-08-27 2004-12-28 International Rectifier Corporation Bidirectional shallow trench superjunction device with resurf region
US7023050B2 (en) * 2003-07-11 2006-04-04 Salama C Andre T Super junction / resurf LDMOST (SJR-LDMOST)
US7126166B2 (en) * 2004-03-11 2006-10-24 Semiconductor Components Industries, L.L.C. High voltage lateral FET structure with improved on resistance performance
JP4334395B2 (ja) * 2004-03-31 2009-09-30 株式会社東芝 半導体装置
JP5259920B2 (ja) * 2004-08-04 2013-08-07 ローム株式会社 半導体装置およびその製造方法
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
JP5017926B2 (ja) * 2005-09-28 2012-09-05 株式会社デンソー 半導体装置およびその製造方法
US7804150B2 (en) * 2006-06-29 2010-09-28 Fairchild Semiconductor Corporation Lateral trench gate FET with direct source-drain current path
JP2009060064A (ja) * 2007-09-04 2009-03-19 New Japan Radio Co Ltd 半導体装置及びその製造方法
JP2009088186A (ja) * 2007-09-28 2009-04-23 Sanyo Electric Co Ltd トレンチゲート型トランジスタ及びその製造方法
JP5223291B2 (ja) * 2007-10-24 2013-06-26 富士電機株式会社 半導体装置の製造方法
US20090206397A1 (en) * 2008-02-15 2009-08-20 Advanced Analogic Technologies, Inc. Lateral Trench MOSFET with Conformal Depletion-Assist Layer
US7847351B2 (en) * 2008-04-11 2010-12-07 Texas Instruments Incorporated Lateral metal oxide semiconductor drain extension design
WO2010014283A1 (en) * 2008-07-30 2010-02-04 Max Power Semiconductor Inc. Lateral devices containing permanent charge
WO2011107141A1 (en) * 2010-03-01 2011-09-09 X-Fab Semiconductor Foundries Ag High voltage mos transistor
JP5510404B2 (ja) * 2011-07-11 2014-06-04 トヨタ自動車株式会社 半導体装置、及び、半導体装置の製造方法
WO2013023094A2 (en) * 2011-08-11 2013-02-14 Volterra Semiconductor Corporation Vertical gate ldmos device
JP5772987B2 (ja) * 2012-01-12 2015-09-02 トヨタ自動車株式会社 半導体装置とその製造方法
JP2014236120A (ja) * 2013-06-03 2014-12-15 トヨタ自動車株式会社 半導体装置及びその製造方法
CN103426932A (zh) * 2013-08-29 2013-12-04 上海宏力半导体制造有限公司 双resurf ldmos器件

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Publication number Publication date
CN104810365A (zh) 2015-07-29
CN104810365B (zh) 2019-07-19
JP2015141925A (ja) 2015-08-03
US20150214356A1 (en) 2015-07-30
US9356135B2 (en) 2016-05-31

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