CN110120423B - 一种ldmos器件及其制备方法 - Google Patents
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Abstract
本发明提出了一种LDMOS器件，包括半导体衬底、埋层、外延层、源极金属、漏极金属和场氧化层，所述外延层上设置有PN变掺杂降场层、P型半导体体区和N型半导体漏区，所述PN变掺杂降场层的左半部分为P型变掺杂区，右半部分为N型变掺杂区，所述P型变掺杂区中的P型杂质浓度从左到右逐渐减小到0 cm‑3，所述N型变掺杂区中的N型杂质浓度从右至左逐渐减小到0 cm‑3。通过在外延层内制备PN变掺杂降场层，在漂移区中部产生一个均匀的电场分布，同时消除了主结处的高的电场峰值，优化了漂移区的表面电场分布，从而能够提高器件的反向击穿电压；此外，PN变掺杂降场层能够提高常规器件的漂移区浓度，有效的提高了器件的电流能力并降低器件的导通电阻。
Description
技术领域
本发明涉及一种LDMOS器件及其制备方法，属于集成电路技术领域。
背景技术
随着功率电子技术的发展，功率集成电路对半导体功率器件的性能也提出了更高的要求，作为功率集成电路的核心器件，横向半导体功率器件需要提供高的耐压，和低的导通电阻。LDMOS(横向扩散金属氧化物半导体晶体管)由于其具有良好的工艺兼容性，并且易于通过内部连线将分布在表面的源极、栅极和漏极与低压逻辑电路单片集成而被广泛应用。但是LDMOS击穿电压提高的同时往往使得导通电阻同时增加。这一矛盾关系限制了该类器件在高压和大电流领域的应用。为了克服这个矛盾关系，J.A.APPLES 等人提出了RESURF(Reduced Surface Field) 降低表面场技术，图1给出了一个典型的常规SOI RESURFLDMOS器件结构示意图，它由半导体衬底A1、埋层A2、外延层A3、P型半导体体区A4、N型半导体漏区A5，其中P型半导体体区A4中具有半导体源区A6和半导体体接触区A7，栅极A8、源极金属A9和漏极金属A10，栅极和外延层之间的是栅氧化层A11，以及场氧化层A12组成。但是此技术只能在一定程度上降低导通电阻，仍然满足不了高速发展的功率集成电路对高压LDMOS器件的技术要求。
为了改善RESURF结构的导通特性，文献：Zingg R P, Weijland I, Zwol H V, etal. 850V DMOS-switch in silicon-on-insulator with specific Ron of 13Ω ·mm2.Proceeding of International SOI Conference, 2000, pp.62-63，提出了一种新的高压低导通电阻设计技术——D-RESURF技术。图2给出了现有的具有PN变掺杂降场层的高压LDMOS器件结构示意图。其P型PN变掺杂降场层B13位于N型外延层B3中，该P型PN变掺杂降场层B13能够在一定程度上降低LDMOS器件的导通电阻，但由其表面电场的分布可知，其在正偏的PN结处将出现一个电场低谷,从而影响器件表面电场分布。此外，为了优化表面电场分布，PN变掺杂降场层B13要尽量接近P型半导体体区B4两者之间的电流通道随着两者之间的距离的减小而减小，因此会导致增大导通电阻，这些缺点严重影响了器件工作电压的进一步提高。
发明内容
为了解决上述问题，本发明提供了一种LDMOS器件，其能够优化漂移区的表面电场分布，从而能够提高器件的击穿电压，有效提高器件的电流能力并降低器件的导通电阻，还能够消除了传统D-RESURF LDMOS器件中正向PN结产生的电场峰值。
本发明提供一种LDMOS器件，包括半导体衬底、埋层、外延层、源极金属、漏极金属和场氧化层，所述埋层设置于所述半导体衬底上，所述外延层设置于所述埋层上，所述外延层上设置有PN变掺杂降场层、P型半导体体区和N型半导体漏区，所述P型半导体体区中设置有半导体源区和半导体体接触区，所述半导体源区和半导体体接触区均与所述源极金属接触；所述漏极金属与所述N型半导体漏区接触；所述外延层上方设置有场氧化层；所述PN变掺杂降场层的左半部分为P型变掺杂区，所述PN变掺杂降场层的右半部分为N型变掺杂区，所述P型变掺杂区中的P型杂质浓度从左到右逐渐减小到0cm-3，所述N型变掺杂区中的N型杂质浓度从右至左逐渐减小到0cm-3。
作为本发明的进一步技术方案，所述P型变掺杂区中的P型杂质浓度为从左到右降低的线性分布，所述N型变掺杂区中的N型杂质浓度为从右到左降低的线性分布。
进一步地，所述PN变掺杂降场层中的P型变掺杂区中的P型杂质浓度为从左到右降低的高斯分布，所述N型变掺杂区中的N型杂质浓度为从右到左降低的高斯分布。
进一步地，还包括有栅极，所述栅极设置于外延层侧面靠近所述半导体区的一侧，所述外延层、P型半导体体区以及半导体体接触区均与所述栅极接触，所述栅极中设置有金属槽栅。
进一步地，所述PN变掺杂降场层的一端与所述P型半导体体区相连，另一端与所述N型半导体漏区相连。
进一步地，所述栅极的材料为SiO2、Si3N4、Al2O3、TiO2、Y2O3、La2O3、Ta2O5、HfO2或PZT中的任意一种。
进一步地，所述外延层的材料为硅、碳化硅、砷化镓、氮化镓、氧化镓或锗硅中的任意一种。
本发明还提供了一种制备上述LDMOS器件的方法，包括以下步骤：
刻蚀外延层形成沟槽；
在沟槽内淀积介质材料；
形成PN变掺杂降场层，具体包括：步骤一、利用窗口离子注入法在整个外延层顶部注入III族元素，掺杂浓度从左至右逐渐降低；步骤二、利用窗口离子注入法在整个外延层顶部注入V族元素，掺杂浓度从左至右逐渐升高；
形成P型半导体体区和半导体源区；
形成N型半导体漏区和半导体接触区；
制作金属槽栅；
制作源极和漏极。
本发明采用以上技术方案与现有技术相比，具有以下技术效果：通过在外延层内制备PN变掺杂降场层，在漂移区中部产生一个完全均匀的电场分布，同时消除了主结处的高的电场峰值，优化了漂移区的表面电场分布，从而能够提高器件的反向击穿电压；此外，PN变掺杂降场层能够提高常规器件的漂移区浓度，有效的提高了器件的电流能力并降低器件的导通电阻。
此外，由于栅极处于器件侧边，能够使得P型半导体体区和PN变掺杂降场层相连，消除了D-RESURF器件中正向PN结产生的电场峰值。
附图说明
图1为现有技术中常规的LDMOS结构示意图；
图2为现有技术中D-RESURF LDMOS结构示意图；
图3为本发明实施例1提供的LDMOS器件截面示意图；
图4为本发明实施例2提供的LDMOS器件截面示意图；
图5为本发明提供的LDMOS器件制备方法的流程示意图；
图6为本发明的LDMOS器件制备方法中利用刻蚀形成沟槽后的截面示意图；
图7为本发明的LDMOS器件制备方法中在沟槽中淀积介质材料后的截面示意图；
图8为本发明的LDMOS器件制备方法中使用窗口离子注入法形成变掺杂的P型区域后的截面示意图；
图9为本发明的LDMOS器件制备方法中使用第二次窗口离子注入法形成PN变掺杂降场层后的截面示意图；
图10为本发明的LDMOS器件制备方法中P型半导体体区和半导体源区形成后的截面示意图；
图11为本发明的LDMOS器件制备方法中N型半导体漏区和半导体接触区形成后的截面示意图；
图12为本发明的LDMOS器件制备方法中制作金属槽栅后的截面示意图；
图13为本发明的LDMOS器件制备方法中制作源极，漏极的金属电极后的截面示意图；
图14是相同结构参数的常规LDMOS器件结构与本发明提供的LDMOS器件结构的电场分布示意图。
图15是常规LDMOS器件结构与本发明提供的LDMOS器件结构的IV特性示意图。
其中：A1、半导体衬底；A2、埋层；A3外延层；A4、P型半导体体区；A5、N型半导体漏区；A4、P型半导体体区；A6、半导体源区；A7、半导体体接触区；A8、栅极；A9、源极金属；A10、漏极金属；A11、栅氧化层；A12、场氧化层；B13、P型PN变掺杂降场层；B3、N型外延层；B4、P型半导体体区；1、半导体衬底；2、埋层；3、外延层；4、P型半导体体区；5、N型半导体漏区；6、半导体体接触区；7、半导体源区；9、源极金属；10、漏极金属；12、场氧化层；14、栅极；15、金属槽栅；16、PN变掺杂降场层；16-1、P型变掺杂区；16-2、N型变掺杂区；17、沟槽；18、P型变掺杂PN变掺杂降场层。
具体实施方式
下面结合附图对本发明的技术方案做进一步的详细说明。
实施例1：
本实施例提出了一种具有变掺杂PN变掺杂降场层的LDMOS，图3为本发明实施例1提供的LDMOS器件截面示意图，如图3所示，包括位于最下方的半导体衬底1；p型衬底上的埋层2；位于埋层上方的外延层3；所述外延层3包括一个变掺杂的PN变掺杂降场层16，PN变掺杂降场层的左半部分16-1为P型变掺杂区，浓度从左至右线性减小到0cm-3，PN变掺杂降场层的右半部分16-2为N型掺杂区，浓度从右至左线性减小到0cm-3。
PN变掺杂降场层16与P型半导体体区4和N型半导体漏区5相连；所述P型半导体体区4中具有半导体源区7和半导体体接触区6；外延层3中除去P型半导体体区4、N型半导体漏区5、半导体体接触区6和半导体源区7的部分称为漂移区，PN变掺杂降场层16设置于漂移区的上部。
半导体源区7和半导体体接触区6接触的是源极金属9；与N型半导体漏区5接触的是漏极金属10；外延层3左侧和P型半导体体区4以及半导体体接触区6接触的是栅极14，介质层中的是金属槽栅15；外延层上方的是场氧化层12。从图中可以看出，本发明提供的具有PN变掺杂降场层的LDMOS器件结，其PN变掺杂降场层16与位于顶部一侧的N型半导体漏区5和位于另一侧的P型半导体体区4相连，PN变掺杂降场层16的左半部分为P型变掺杂区16-1，浓度从左至右逐渐减小到0cm-3，PN变掺杂降场层16的右半部分为N型变掺杂区16-2，浓度从左至右从0cm-3开始逐渐升高。能够在漂移区中形成一个均匀的电场分布，从而能够提高器件的击穿电压；并能够提高常规器件的漂移区浓度，有效的提高了器件的电流能力并降低器件的导通电阻。
实施例2：
其他均同实施例1，不同之处在于PN变掺杂降场层16中P型变掺杂区16-1的P型杂质浓度为从左至右降低的高斯分布，所述N型变掺杂区16-2的N型杂质浓度分布为从右至左降低的高斯分布，如图4所示。
此外，本发明还在传统的LDMOS器件的制备工艺基础上做了一些改进，以优化器件的击穿电压和导通电阻。主要的工艺流程如图5所示。主要的改进包括在外延层3内通过两次窗口离子注入形成PN变掺杂降场层16，并将栅极14制作在侧向沟槽17内，使得PN变掺杂降场层16与位于顶部一侧的N型半导体漏区5和位于另一侧的P型半导体体区4相连。下面主要阐述该器件的主要制备步骤：
首先采用干法刻蚀工艺在外延层3中刻蚀出所需的沟槽17，如图6所示；
其次在沟槽17中淀积介质材料形成栅极14，该介质材料可以是常用的SiO2，也可以是SI3N4、Al2O3、TiO2、Y2O3、La2O3、Ta2O5、HfO2或PZT等介质材料，如图7所示。
然后利用窗口离子注入法在漂移区中注入III族元素形成P型变掺杂PN变掺杂降场层18，掺杂浓度从左至右逐渐降低，如图8所示；
接着利用窗口离子注入法在P型变掺杂PN变掺杂降场层18中注入V族元素，掺杂剂量从左至右逐渐升高。使P型PN变掺杂降场层18的浓度在中部降为0，然后在右部变成N型并且浓度逐渐升高，形成PN变掺杂降场层16，如图9所示；
之后利用离子注入形成P型半导体体区4和半导体源区7，如图10所示；
再利用离子注入及退火形成N型半导体漏区5和半导体接触区6，如图11所示；
然后通过刻蚀和淀积工艺形成金属槽栅15，如图12所示；
最后制作源极金属9、漏极金属10，如图13所示。
下面以SOI LDMOS器件为例，对本发明的工作机理进行说明。
图14是相同结构参数的常规LDMOS器件结构与本发明提供的LDMOS器件结构的电场分布示意图。图14比较了常规的LDMOS器件结构与本发明提供的LDMOS器件结构的表面电场分布。两种结构具有相同的几何尺寸，而漂移区浓度分布则进行了优化。其中虚线为常规LDMOS器件表面电场分布曲线，实线为本发明提供的LDMOS器件表面电场分布曲线。由图可知，对于常规的LDMOS器件结构，电场在漂移区中部较低，其在漂移区的两侧产生两个高的电场峰值。而对于本发明提供的高压LDMOS器件结构，PN变掺杂降场层能够在漂移区的中形成一个均匀的电场分布，而且由于该PN变掺杂降场层与体区和漏区相连，消除了两端的电场峰值，因此优化了漂移区的表面电场分布，从而能够在一定程度上提高器件的击穿电压。
图15是常规的LDMOS器件结构与本发明提供的LDMOS器件结构的IV特性。图15比较了常规的LDMOS器件结构与本发明提供的LDMOS器件结构在漏断电压为8V时的输出特性曲线。其中虚线为常规的LDMOS器件漏源电流与漏源电压关系曲线，实线为本发明提供的LDMOS器件漏源电流与漏源电压关系曲线。由图可知，本发明提供的LDMOS器件的饱和电流高于常规LDMOS器件的饱和电流，说明本发明提供的LDMOS器件具有较好的电流能力。通过输出特性曲线可得常规的LDMOS器件的导通电阻为46.8ohm·cm2；本发明提供的LDMOS器件导通电阻为25.1ohm·cm2，导通电阻降低了46.4%。
综上所述，本发明通过在漂移区引入PN变掺杂降场层16。一方面PN变掺杂降场层16能够在漂移区中部产生一个均匀的电场分布，同时由于PN变掺杂降场层16与N型半导体漏区5和P型半导体体区4相连，消除了主结处的高的电场峰值，优化了漂移区的表面电场分布，从而能够提高器件的击穿电压；另一方面，PN变掺杂降场层16能够提高常规器件的漂移区浓度，有效的提高了器件的电流能力并降低器件的导通电阻。
以上所述，仅为本发明中的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人在本发明所揭露的技术范围内，可理解想到的变换或替换，都应涵盖在本发明的包含范围之内，因此，本发明的保护范围应该以权利要求书的保护范围为准。
Claims (6)
1.一种LDMOS器件，包括半导体衬底、埋层、外延层、源极金属、漏极金属和场氧化层，所述外延层上设置有PN变掺杂降场层、P型半导体体区和N型半导体漏区，所述P型半导体体区中设置有半导体源区和半导体体接触区，所述半导体源区和半导体体接触区均与所述源极金属接触；所述漏极金属与所述N型半导体漏区接触；其特征在于：所述PN变掺杂降场层的左半部分为P型变掺杂区，所述PN变掺杂降场层的右半部分为N型变掺杂区，所述P型变掺杂区中的P型杂质浓度从左到右逐渐减小到0cm-3，所述N型变掺杂区中的N型杂质浓度从右至左逐渐减小到0cm-3；
所述LDMOS器件还包括栅极，所述栅极设置于外延层侧面靠近所述P型半导体体区的一侧，所述外延层、P型半导体体区以及半导体体接触区均与所述栅极接触，所述栅极中设置有金属槽栅；
所述PN变掺杂降场层的一端与所述P型半导体体区相连，另一端与所述N型半导体漏区相连。
2.根据权利要求1所述的一种LDMOS器件，其特征在于：所述P型变掺杂区中的P型杂质浓度为从左到右降低的线性分布，所述N型变掺杂区中的N型杂质浓度为从右到左降低的线性分布。
3.根据权利要求1所述的一种LDMOS器件，其特征在于：所述P型变掺杂降场层中的P型杂质浓度为从左到右降低的高斯分布，所述的N型变掺杂区中的N型杂质浓度分布为从右到左降低的高斯分布。
4.根据权利要求1所述的一种LDMOS器件，其特征在于：所述栅极的材料为SiO2、Si3N4、Al2O3、TiO2、Y2O3、La2O3、Ta2O5、HfO2或PZT中的任意一种。
5.根据权利要求1所述的一种LDMOS器件，其特征在于：所述外延层的材料为硅、碳化硅、砷化镓、氮化镓、氧化镓或锗硅中的任意一种。
6.一种制备权利要求1-5中任意一项所述LDMOS器件的方法，其特征在于：包括以下步骤：
刻蚀外延层形成沟槽；
在沟槽内淀积介质材料；
形成PN变掺杂降场层，具体包括：步骤一、利用窗口离子注入法在整个外延层顶部注入III族元素，掺杂浓度从左至右逐渐降低；步骤二、利用窗口离子注入法在整个外延层顶部注入V族元素，掺杂浓度从左至右逐渐升高；
形成P型半导体体区和半导体源区；
形成N型半导体漏区和半导体接触区；
制作金属槽栅；
制作源极和漏极。
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