CN106024905A - 一种低导通电阻横向双扩散金属氧化物半导体器件 - Google Patents
一种低导通电阻横向双扩散金属氧化物半导体器件 Download PDFInfo
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Abstract
一种低导通电阻横向双扩散金属氧化物半导体器件,包括:P型衬底,在P型衬底的上方设有高压N型区,在高压N型区的上方设有N型漂移区和P型体区,在N型漂移区内设有N型漏区、浅槽隔离区,在P型体区内设有N型源区和P型区,在高压N型区的上方设有栅氧化层且所述栅氧化层的两端分别延伸至P型体区和第一浅槽隔离区的上方,在栅氧化层上方设有多晶硅栅场板,在N型漏区、N型源区和P型区的上设有金属接触。其特征在于,所述浅槽隔离区包括间隔、对称排列的第一浅槽隔离区和第二浅槽隔离区,所述第二浅槽隔离区两端内缩且短于所述第一浅槽隔离区。本发明可以在击穿电压几乎不变的基础上,获得极低的导通电阻。
Description
技术领域
本发明涉及功率半导体器件领域,是关于一种低导通电阻横向双扩散金属氧化物半导体器件。
背景技术
随着半导体技术及其应用领域的迅速发展,功率半导体器件制造工艺和结构不断进步,促使功率器件向着高性能方向发展。
功率器件中横向双扩散金属氧化物半导体场效应管(Lateral Double-DiffusedMOSFET,简称LDMOS)具有高耐压、高输入阻抗及易于集成等优势,所以被广泛应用在半导体集成电路制造中。与传统MOSFET相比,LDMOS器件具有一个低掺杂的漂移区。当在漏源之间加很高的电压时,由于漂移区具有很高的电阻,大部分的电压都施加在此漂移区上,可有效提高器件的耐压水平。
现今,许多研究者通过改进器件结构或改善工艺来提高LDMOS器件的性能,其主要性能指标是击穿电压和导通电阻。降低导通电阻有利于提高器件的工作效率,而提高击穿电压对增大器件的输出功率和提升器件的输出阻抗有突出贡献。在LDMOS器件的结构设计中,常采用在漂移区使用浅沟槽隔离技术(ShallowTrench Isolation,STI)的工艺方法来提高击穿电压,该工艺是一种完全平坦、无“鸟嘴”现象的新型隔离技术。与传统的本征氧化隔离技术相比,采用STI技术的LDMOS可以承受更大的击穿电压。但研究表明,在使用常规STI作为LDMOS漂移区场板介质时,LDMOS导电通路上的线性区电流受STI的影响很大,由于STI结构大小的限制,LDMOS的耐压和导通电阻无法做到最优化,所以难以实现低导通电阻的LDMOS。
发明内容
围绕LDMOS的导通电阻和击穿电压之间的矛盾关系,本发明提供一种低导通电阻横向双扩散金属氧化物半导体器件,在同样的尺寸下与传统的LDMOS器件相比,可在击穿电压几乎不变的基础上,获得极低的导通电阻。
本发明采用如下技术方案:
一种低导通电阻横向双扩散金属氧化物半导体器件,包括:P型衬底,在P型衬底的上方设有高压N型区,在高压N型区的上方设有N型漂移区和P型体区,在N型漂移区内设有N型漏区、浅槽隔离区,在P型体区内设有N型源区和P型区,在高压N型区的上方还设有栅氧化层且所述栅氧化层的两端分别延伸至P型体区的上方和第一浅槽隔离区的上方,在栅氧化层上方设有多晶硅栅场板,在N型漏区、N型源区和P型区的上表面分别设有漏极金属接触、源极金属接触和体区金属接触。其特征在于,所述浅槽隔离区包括间隔、对称排列的第一浅槽隔离区和第二浅槽隔离区,所述第二浅槽隔离区两端内缩且短于所述第一浅槽隔离区,所述的第一浅槽隔离区的左边界距离型漏区距离大于0.2μm。所述的多晶硅栅场板及栅氧化层呈U形,且U形头部与浅槽隔离区中的第一浅槽隔离区搭接。多晶硅栅场板及栅氧化层U形底部距离第一浅槽隔离区的相邻边界0.2μm-0.3μm,覆盖在第一浅槽隔离区上的多晶硅栅场板及栅氧化层一端距离第一浅槽隔离区的相邻边界0.1μm-0.2μm。第二浅槽隔离区(14)两端边界比第一浅槽隔离区(13)两端边界均短0.2μm-0.3μm。
与现有技术相比,本发明具有如下优点:
(1)本发明结构与图1所示的传统的LDMOS结构的器件相比,在保持击穿电压基本不变的情况下能降低器件的导通电阻。与传统结构中全部是第一浅槽隔离区13相比,本发明的器件结构浅槽隔离区纵向呈第一浅槽隔离区13、第二浅槽隔离区14和第一浅槽隔离区13间隔、对称排列。LDMOS在工作时,电流流通路径从漏端硅绕过浅槽隔离区再到源端,相对于体内,器件表面浓度高,故为低阻区域,而本发明结构中从第二浅槽隔离区流通的电流路径(如图6所示)所经过的低阻区域比传统结构中从第一浅槽隔离区流通的电流路径(如图5所示)所经过的低阻区域大。因此电流路径中,低阻区域所占的比例大,从而使导通电阻降低。所以本发明结构的浅槽隔离区纵向呈第一浅槽隔离区13、第二浅槽隔离区14和第一浅槽隔离区13间隔、对称排列具有更低的导通电阻。如图7所示,在相同电压下,本发明结构与传统结构相比,在线性区和饱和区的电流更大,因而导通电阻更低。
(2)本发明结构与图1所示的传统的LDMOS结构的器件相比,第二浅槽隔离区14内缩使器件具有更低的导通电阻的同时,击穿电压却基本不变。这是由于第二浅槽隔离区14的内缩位置经过特定的设计。此种内缩方法可以使得第一浅槽隔离区13和第二浅槽隔离区14从三个方向上有效的对处于第二浅槽隔离区14的内缩区域的N型漂移区进行辅助耗尽,从而使器件的击穿电压几乎保持不变。若改变浅槽隔离区的内缩位置(如图9所示),包括全部内缩结构、两边内缩结构、内缩靠前结构和内缩靠后结构,器件的导通电阻均小于传统结构(如图10所示)但器件的击穿电压明显下降。如图11所示,其余内缩结构的击穿电压远小于传统结构的击穿电压。此外,本发明结构还采用U形场板进一步保证器件的击穿电压不变。因此,和原传统结构相比,本发明结构的击穿电压基本不变。如图8所示,本发明结构与传统结构相比,击穿电压基本不变。
(3)本发明器件结构的制造工艺可以与常规CMOS制造工艺相兼容,且不需要额外的工艺流程,因而可以节约设计和制备成本。
附图说明
图1是三维立体剖面图,图示了传统的LDMOS结构的立体剖面结构。
图2是三维立体剖面图,图示了本发明中低导通电阻的LDMOS结构器件的立体剖面结构。
图3是剖面图,图示了传统的LDMOS结构器件的立体剖面图1中AA’剖面的器件剖面结构。
图4是剖面图,图示了本发明中低导通电阻的LDMOS结构器件的立体剖面图2中BB’剖面的器件剖面结构。
图5是剖面电流路径图,图示了传统的LDMOS结构器件在只有第一浅槽隔离区的电流流通路径。
图6是剖面电流路径图,图示了本发明中低导通电阻的LDMOS结构器件在第二浅槽隔离区的电流流通路径。
图7所示为本发明中低导通电阻的LDMOS结构的器件和传统的LDMOS结构的器件的I-V测试结果的比较图。
图8所示为本发明中低导通电阻的LDMOS结构的器件和传统的LDMOS结构的器件关态击穿特性测试结果的比较图。
图9所示为LDMOS的浅槽隔离区在不同内缩位置时的器件结构俯视图,包括全部内缩结构、两边内缩结构、内缩靠前结构和内缩靠后结构的俯视图。
图10所示为LDMOS的浅槽隔离区在不同内缩位置的结构和传统LDMOS结构的器件的I-V测试结果的比较图。
图11所示为LDMOS的浅槽隔离区在不同内缩位置的结构和传统LDMOS结构的器件的关态击穿特性测试结果的比较图。
具体实施方式
一种低导通电阻横向双扩散金属氧化物半导体器件,包括:P型衬底1,在P型衬底1的上方设有高压N型区2,在高压N型区2的上方设有N型漂移区3和P型体区,在N型漂移区3内设有N型漏区6、浅槽隔离区,在P型体区4内设有N型源区5和P型区7,在高压N型区2的上方还设有栅氧化层8且所述栅氧化层8的两端分别延伸至P型体区4的上方和第一浅槽隔离区13的上方,在栅氧化层8上方设有多晶硅栅场板9,在N型漏区6、N型源区5和P型区7的上表面分别设有漏极金属接触10、源极金属接触11和体区金属接触12,其特征在于,所述浅槽隔离区包括间隔、对称排列的第一浅槽隔离区13和第二浅槽隔离区14,所述第二浅槽隔离区14两端内缩且短于所述第一浅槽隔离区13,所述的第一浅槽隔离区13的左边界距离N型漏区6距离大于0.2μm。
所述的多晶硅栅场板9及栅氧化层8呈U形,且U形头部与浅槽隔离区中的第一浅槽隔离区13搭接。
所述的多晶硅栅场板9及栅氧化层8U形底部距离第一浅槽隔离区13的相邻边界0.2μm-0.3μm,覆盖在第一浅槽隔离区13上的多晶硅栅场板9及栅氧化层8一端距离第一浅槽隔离区13的相邻边界0.1μm-0.2μm。
所述的第二浅槽隔离区(14)两端边界比第一浅槽隔离区(13)两端边界均短0.2μm-0.3μm。
本发明采用如下方法来制备:
第一步,取P型衬底硅圆片,对其进行预清洗,然后通过N型离子注入高温退火后形成高压N型区2。
第二步,光刻,利用离子刻蚀形成浅的沟槽,淀积二氧化硅填充沟槽,最后利用化学机械抛光使硅片表面平整形成浅槽隔离区13和浅槽隔离区14。
第三步,通过N型离子注入高温退火后形成N型漂移区3。
第四步,生长栅氧化层8,并淀积刻蚀多晶硅形成多晶硅栅场板9。
第五步,通过高剂量的硼离子和磷离子注入,形成N型漏区6、N型源区5和P型区7。
第六步,生长二氧化硅,光刻出沟道区,进行阈值电压调整注入。
第七步,光刻出金属电极引出孔,淀积金属层,刻蚀掉多余金属,形成漏极金属接触10、源极金属接触11和体区金属接触12。
Claims (4)
1.一种低导通电阻横向双扩散金属氧化物半导体器件,包括:P型衬底(1),在P型衬底(1)的上方设有高压N型区(2),在高压N型区(2)的上方设有N型漂移区(3)和P型体区(4),在N型漂移区(3)内设有N型漏区(6)、浅槽隔离区,在P型体区(4)内设有N型源区(5)和P型区(7),在高压N型区(2)上还设有栅氧化层(8)且所述栅氧化层(8)的两端分别延伸至P型体区(4)的上方和第一浅槽隔离区(13)的上方,在栅氧化层(8)上方设有多晶硅栅场板(9),在N型漏区(6)、N型源区(5)和P型区(7)的上表面分别设有漏极金属接触(10)、源极金属接触(11)和体区金属接触(12),其特征在于,所述浅槽隔离区包括间隔、对称排列的第一浅槽隔离区(13)和第二浅槽隔离区(14),所述第二浅槽隔离区(14)两端内缩且短于所述第一浅槽隔离区(13),所述的第一浅槽隔离区(13)的左边界距离N型漏区(6)距离大于0.2μm。
2.根据权利要求1所述的一种低导通电阻横向双扩散金属氧化物半导体器件,其特征在于,所述的多晶硅栅场板(9)及栅氧化层(8)呈U形,且U形头部与浅槽隔离区中的第一浅槽隔离区(13)搭接。
3.根据权利要求2所述的一种低导通电阻横向双扩散金属氧化物半导体器件,其特征在于,多晶硅栅场板(9)及栅氧化层(8)U形底部距离第一浅槽隔离区(13)的相邻边界0.2μm-0.3μm,覆盖在第一浅槽隔离区(13)上的多晶硅栅场板(9)及栅氧化层(8)一端距离第一浅槽隔离区(13)的相邻边界0.1μm-0.2μm。
4.根据权利要求1所述的一种低导通电阻横向双扩散金属氧化物半导体器件,其特征在于,第二浅槽隔离区(14)两端边界比第一浅槽隔离区(13)两端边界均短0.2μm-0.3μm。
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