CN108807541B - 一种具有交错叉指式排列的浅槽隔离结构横向半导体器件 - Google Patents

一种具有交错叉指式排列的浅槽隔离结构横向半导体器件 Download PDF

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CN108807541B
CN108807541B CN201810537122.2A CN201810537122A CN108807541B CN 108807541 B CN108807541 B CN 108807541B CN 201810537122 A CN201810537122 A CN 201810537122A CN 108807541 B CN108807541 B CN 108807541B
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trench isolation
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刘斯扬
陈虹廷
叶然
吴海波
孙伟锋
陆生礼
时龙兴
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Southeast University
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Abstract

一种具有交错叉指式浅槽隔离结构的横向半导体器件，包括：P型衬底，在P型衬底的上方设有高压N型区，在高压N型区的上方设有N型漂移区和P型体区，在N型漂移区内设有N型漏区和三个浅槽隔离区，在P型体区内设有N型源区和P型区，在高压N型区上还设有U形栅氧化层且所述栅氧化层的U形开口朝向漏端并且两端分别延伸至P型体区的上方和浅槽隔离区的上方，在栅氧化层的上方设有多晶硅栅场板，在N型漏区、N型源区和P型区的上表面分别设有漏极金属接触、源极金属接触和体区金属接触，其特征在于，所述的浅槽隔离区在漂移区内呈交错叉指式排列。本发明结构能够在击穿电压不变的基础上，获得较低的导通电阻。

Description

一种具有交错叉指式排列的浅槽隔离结构横向半导体器件
技术领域
本发明涉及功率半导体器件领域，是关于一种具有交错叉指式浅槽隔离结构的横向半导体器件。
背景技术
横向双扩散金属氧化物半导体场效应管(Lateral Double-Diffused MOSFET，简称LDMOS)具有高击穿电压、高输入阻抗及易于与其他器件集成等优点，被广泛应用在高压集成电路和功率集成电路中。与传统MOSFET器件相比，LDMOS器件具有一个低掺杂的漂移区，当漏源之间加高压时，由于漂移区全部耗尽，所以能承受更高的电压。
在LDMOS器件结构的设计中，常在漂移区使用浅槽隔离技术(Shallow TrenchIsolation，STI)来提高器件的耐压能力。采用STI结构的LDMOS器件，STI可以在漂移区内承担大部分电场，有助于漂移区更好的耗尽，因此其具有更高的击穿电压。虽然该工艺可以提高器件的耐压能力，但是STI结构会使电流从源端流向漏端的流动路径增大，导致器件的导通电阻增大。因此，在LDMOS的漂移区采用STI结构时，击穿电压和导通电阻无法取得更好的折中。
发明内容
针对LDMOS的导通电阻和击穿电压之间的矛盾关系，本发明提供一种具有交错叉指式浅槽隔离结构的横向半导体器件，与传统的LDMOS器件相比，在同样的尺寸下可实现在击穿电压几乎不变的基础上，获得较低的导通电阻。
本发明采用如下技术方案：
一种具有交错叉指式浅槽隔离结构的横向半导体器件，包括：P型衬底，在P型衬底的上方设有高压N型区，在高压N型区的上方设有N型漂移区和P型体区，在N型漂移区内设有N型漏区、第一浅槽隔离区、第二浅槽隔离区和第三浅槽隔离区，在P型体区内设有N型源区和P型区，在高压N型区上还设有U形栅氧化层且所述栅氧化层的U形开口朝向漏端并且两端分别延伸至P型体区的上方和第一浅槽隔离区、第三浅槽隔离区的上方，在栅氧化层的上方设有多晶硅栅场板，在N型漏区、N型源区和P型区的上表面分别设有漏极金属接触、源极金属接触和体区金属接触，所述的第一浅槽隔离区、第二浅槽隔离区和第三浅槽隔离区在漂移区内呈交错叉指式排列，并且所述的第二浅槽隔离区在第一浅槽隔离区和第三浅槽隔离区的中间，所述的第一浅槽隔离区和第三浅槽隔离区距N型漏区有一定距离且向源端延伸，所述的第二浅槽隔离区的一个边界紧靠N型漏区且向源端延伸，另一个边界延伸进入第一浅槽隔离区和第三浅槽隔离区之间的区域。
进一步的，所述的第一浅槽隔离区和第三浅槽隔离区距离漏端的距离为0.2μm-0.4μm，第二浅槽隔离区和第一浅槽隔离区、第三浅槽隔离区交错的距离为0.1-0.3μm，相邻两个浅槽隔离区之间的间距为0.1μm-0.3μm。
与现有技术相比，本发明具有如下优点：
1、本发明结构与传统的带有部分浅槽隔离结构的LDMOS器件(如图1所示)相比，在缩短漂移区内浅槽隔离区长度的情况下，击穿电压基本不变。本发明器件结构如图2所示，第一浅槽隔离区6A、第二浅槽隔离区6B和第三浅槽隔离区6C在漂移区内呈交错叉指式排列。图3为图1所示传统的带有部分浅槽隔离结构的LDMOS器件的俯视结构，可以看出第一浅槽隔离区6A和第二浅槽隔离区6B从a、b两个方向耗尽漂移区。图4为本发明中具有交错叉指式浅槽隔离结构的横向器件的俯视结构，第一浅槽隔离区6A、第二浅槽隔离区6B和第三浅槽隔离区6C从多个方向辅助漂移区耗尽来维持击穿电压，图中还画出了其相邻的区域，两个区域之间相邻的漂移区同样从多个方向被耗尽，该方式可以使漂移区电场分布更加均匀，有效减小表面电场，降低器件内部的碰撞电离率。图7将本发明结构BB’截面电场分布图和传统结构AA’截面电场分布图进行比较，与传统结构相比，本发明结构的横向峰值电场有所下降。图5为具有交错叉指排列浅槽隔离结构的横向器件和传统的带有部分浅槽隔离结构的LDMOS器件关态击穿特性测试结果的比较图，与传统结构相比，本发明结构在缩短漂移区浅槽隔离区长度的情况下击穿电压基本不变。
2、本发明结构与图1所示传统的带有部分浅槽隔离结构的LDMOS器件相比，在保持击穿电压基本不变的基础上降低器件的导通电阻。这是由于第一浅槽隔离区6A、第二浅槽隔离区6B和第三浅槽隔离区6C的长度和宽度经过特定的设计，相互交错的浅沟槽隔离区对漂移区具有更好的耗尽作用。一方面，相邻的两个浅槽隔离区之间可以留有间距，提供了额外的电流通过路径，使器件具有多条电流流动路径。另一方面，与传统结构相比，浅槽隔离区长度可以变短，缩短电流在浅沟槽隔离区下方的流动路径，使器件的导通电阻进一步降低。因此，在相同击穿电压下，本发明结构与传统结构相比，在线性区和饱和区的电流更大，导通电阻更低(如图6所示)。
3、本发明器件结构的制造工艺可以与传统浅槽隔离结构制备工艺相兼容，仅需要改变有源区的版图方式就可以实现，故不需要额外的工艺流程，可以节约设计和制备成本。
附图说明
图1是三维立体剖面图，图示了传统的带有部分浅槽隔离结构的LDMOS器件的立体剖面结构。
图2是三维立体剖面图，图示了本发明中具有交错叉指式排列的浅槽隔离结构LDMOS器件的立体剖面结构。
图3是俯视图，图示了传统的带有部分浅槽隔离结构的LDMOS器件的俯视结构。
图4是俯视图，图示了本发明中具有交错叉指式浅槽隔离结构的横向器件俯视结构。
图5所示为本发明中具有交错叉指式浅槽隔离结构的横向器件和传统的LDMOS结构的器件关态击穿特性测试结果的比较图。
图6所示为本发明中具有交错叉指式浅槽隔离结构的横向器件和传统的LDMOS结构的器件的I-V测试结果的比较图。
图7所示为本发明中具有交错叉指式浅槽隔离结构的横向器件和传统的LDMOS结构的器件的横向截面电场的比较图。
具体实施方式
一种具有交错叉指式浅槽隔离结构的横向半导体器件，包括：P型衬底1，在P型衬底1的上方设有高压N型区2，在高压N型区2的上方设有N型漂移区3和P型体区4，在N型漂移区3内设有N型漏区5、第一浅槽隔离区6A、第二浅槽隔离区6B和第三浅槽隔离区6C，在P型体区4内设有N型源区7和P型区8，在高压N型区2上还设有U形栅氧化层9且所述栅氧化层9的U形开口朝向漏端并且两端分别延伸至P型体区4的上方和第一浅槽隔离区6A、第三浅槽隔离区6C的上方，在栅氧化层9的上方设有多晶硅栅场板10，在N型漏区5、N型源区7和P型区8的上表面分别设有漏极金属接触11、源极金属接触12和体区金属接触13，所述的第一浅槽隔离区6A、第二浅槽隔离区6B和第三浅槽隔离区6C在漂移区3内呈交错叉指式排列，并且所述的第二浅槽隔离区6B在第一浅槽隔离区6A和第三浅槽隔离区6C的中间，所述的第一浅槽隔离区6A和第三浅槽隔离区6C距N型漏区5有一定距离且向源端延伸，所述的第二浅槽隔离区6B的一个边界紧靠N型漏区5且向源端延伸，另一个边界延伸进入第一浅槽隔离区6A和第三浅槽隔离区6C之间的区域。
在实施例中，所述的第一浅槽隔离区6A和第三浅槽隔离区6C距离漏端的距离为0.2μm-0.4μm，第二浅槽隔离区6B和第一浅槽隔离区6A、第三浅槽隔离区6C交错的距离为0.1-0.3μm，相邻两个浅槽隔离区之间的间距为0.1μm-0.3μm。
制备如上所述的一种具有交错叉指式浅槽隔离结构的横向半导体器件，具体步骤如下：
第一步，取P型衬底硅圆片，对其进行预清洗，然后通过N型离子注入高温退火后形成高压N型区2。
第二步，光刻，利用离子刻蚀先形成深的沟槽，再刻蚀出浅的沟槽，之后淀积二氧化硅填充沟槽，最后利用化学机械抛光使硅片表面平整形成交错叉指排列的浅槽隔离区6A、6B和6C。
第三步，通过N型离子注入高温退火后形成N型漂移区3。
第四步，生长栅氧化层9，并淀积刻蚀多晶硅形成多晶硅栅场板10。
第五步，通过高剂量的硼离子和磷离子注入，形成N型漏区5、N型源区7和P型区8。
第六步，生长二氧化硅，光刻出沟道区，进行阈值电压调整注入。
第七步，光刻出金属电极引出孔，淀积金属层，刻蚀掉多余金属，形成漏极金属接触11、源极金属接触12和体区金属接触13。

Claims (2)

1.一种具有交错叉指式浅槽隔离结构的横向半导体器件，包括：P型衬底(1)，在P型衬底(1)的上方设有高压N型区(2)，在高压N型区(2)的上方设有N型漂移区(3)和P型体区(4)，在N型漂移区(3)内设有N型漏区(5)、第一浅槽隔离区(6A)、第二浅槽隔离区(6B)和第三浅槽隔离区(6C)，在P型体区(4)内设有N型源区(7)和P型区(8)，在高压N型区(2)上还设有U形栅氧化层(9)且所述栅氧化层(9)的U形开口朝向漏端并且两端分别延伸至P型体区(4)的上方和第一浅槽隔离区(6A)、第三浅槽隔离区(6C)的上方，在栅氧化层(9)的上方设有多晶硅栅场板(10)，在N型漏区(5)、N型源区(7)和P型区(8)的上表面分别设有漏极金属接触(11)、源极金属接触(12)和体区金属接触(13)，其特征在于，所述的第一浅槽隔离区(6A)、第二浅槽隔离区(6B)和第三浅槽隔离区(6C)在漂移区(3)内呈交错叉指式排列，并且所述的第二浅槽隔离区(6B)在第一浅槽隔离区(6A)和第三浅槽隔离区(6C)的中间，所述的第一浅槽隔离区(6A)和第三浅槽隔离区(6C)距N型漏区(5)有一定距离且向源端延伸，所述的第二浅槽隔离区(6B)的一个边界紧靠N型漏区(5)且向源端延伸，另一个边界延伸进入第一浅槽隔离区(6A)和第三浅槽隔离区(6C)之间的区域。
2.根据权利要求1所述的一种具有交错叉指式浅槽隔离结构的横向半导体器件，其特征在于，所述的第一浅槽隔离区(6A)和第三浅槽隔离区(6C)距离漏端的距离为0.2μm-0.4μm，第二浅槽隔离区(6B)和第一浅槽隔离区(6A)、第三浅槽隔离区(6C)交错的距离为0.1-0.3μm，相邻两个浅槽隔离区之间的间距为0.1μm-0.3μm。
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