CN111799330A - 具有二极管耦合的隔离环的ldmos - Google Patents

具有二极管耦合的隔离环的ldmos Download PDF

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CN111799330A
CN111799330A CN202010262849.1A CN202010262849A CN111799330A CN 111799330 A CN111799330 A CN 111799330A CN 202010262849 A CN202010262849 A CN 202010262849A CN 111799330 A CN111799330 A CN 111799330A
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region
fet
ldmos
well
voltage
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林欣
张志宏
程序
祝荣华
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NXP USA Inc
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NXP USA Inc
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

Abstract

一种用于提高横向扩散金属氧化物半导体(LDMOS)的击穿电压的方法包括将场效应晶体管(FET)的第一阱偏置到第一电压。所述第一阱与第二阱横向分离。响应于所述第一电压超过连接在所述隔离环与所述第一阱之间的二极管的击穿电压将隔离环充电到第二电压。所述隔离环横向包围所述FET并接触在所述第一阱和所述第二阱下方延伸的掩埋层(BL)。将衬底偏置到小于或等于所述第一电压的第三电压。所述衬底在所述BL下方横向延伸并接触所述BL。

Description

具有二极管耦合的隔离环的LDMOS
技术领域
本公开总体上涉及高电压半导体装置，并且更具体地说，涉及横向扩散金属氧化物半导体(LDMOS)。
背景技术
在汽车应用、工业应用和消费应用中，对集成高压装置在更高电压下操作的需求不断增加。为了在可接受的击穿电压下实现高侧能力，这些装置可以被隔离槽区包围，所述隔离槽区由在装置的侧面的n型阱注入和在装置下面延伸的n型掩埋层(NBL)形成。在此类设计中，装置击穿电压通常受到NBL与其上方的隔离的p型之间的纵向结的限制。例如，n型LDMOS中的击穿电压通常由主体区域与底下的NBL隔离层之间的结确定。然而，由p型漂移区域和NBL形成的结常常确定了p型LDMOS中的击穿电压。
对于常规的LDMOS，可以通过增加外延层厚度来提高装置击穿电压，然而这将会产生许多制造工艺挑战。例如，当外延层厚度增加时，在隔离环与NBL之间形成稳健的电连接会更困难，并且可能需要昂贵的高能注入工具。另外，增加外延层厚度会使对准准确度降低或甚至引起对准问题。
发明内容
如将了解的，所公开的实施例包括至少以下内容。在一个实施例中，一种LDMOS包括FET，所述FET包括源极端、连接到主体区域的主体端和连接到漂移区域的漏极端。所述主体区域与所述漂移区域横向分离。隔离环被安置成横向包围FET。掩埋层(BL)位于所述FET下方并与所述隔离环接触。二极管包括阳极和阴极。所述阳极电耦合到所述隔离环，并且所述阴极电耦合到所述FET的区域。
所述LDMOS的替代性实施例包括以下特征中的一个特征或其任何组合。所述FET是p型FET，并且所述FET的所述区域是所述主体区域。所述FET是n型FET，并且所述FET的所述区域是所述漂移区域。所述FET的所述区域包括由n型阱注入形成的上部部分，以及由p型阱注入形成的下部部分安置在所述上部部分与所述BL之间。n型注入在所述阴极中形成，其中所述n型注入具有比所述FET的所述区域的上部部分更高的掺杂浓度。所述BL包括位于所述FET的所述区域下方的第一部分和位于所述FET的所述区域下方的第二部分，其中所述第二部分具有相对于所述第一部分更低的掺杂浓度。所述第一部分与靠近所述FET的栅极氧化物的硅表面之间的第一厚度小于所述第二部分与所述硅表面之间的第二厚度。深沟槽隔离被安置成横向包围所述隔离环。p型注入安置在所述主体区域与所述隔离环之间。
在另一个实施例中，一种LDMOS包括FET，所述FET包括源极端、连接到主体区域的主体端和连接到漂移区域的漏极端。隔离环被安置成横向包围FET。BL位于所述FET下方并与所述隔离环接触。二极管包括阳极和阴极。所述阳极利用金属互连电耦合到隔离环，并且所述阴极电耦合到所述FET的区域。
所述LDMOS的替代性实施例包括以下特征中的一个特征或其任何组合。所述FET的所述区域包括由n型阱注入形成的上部部分，以及由p型阱注入形成的下部部分安置在所述上部部分与所述BL之间。n型注入在所述阴极中形成，其中所述n型注入具有比所述FET的所述区域更高的掺杂浓度。所述BL包括位于所述FET的所述区域下方的第一部分和位于所述FET的所述区域下方的第二部分，其中所述第二部分具有相对于所述第一部分更低的掺杂浓度。所述第一部分与靠近所述FET的栅极氧化物的硅表面之间的第一厚度小于所述第二部分与所述硅表面之间的第二厚度。深沟槽隔离被安置成横向包围所述隔离环。p型注入安置在所述主体区域与所述隔离环之间。
在另一个实施例中，一种用于提高LDMOS的击穿电压的方法包括将FET的第一阱偏置到第一电压。所述第一阱与第二阱横向分离。响应于所述第一电压超过连接在所述隔离环与所述第一阱之间的二极管的击穿电压而将隔离环充电到第二电压。所述隔离环横向包围所述FET并接触在所述第一阱和所述第二阱下方延伸的BL。将衬底偏置到小于或等于所述第一电压的第三电压。所述衬底在所述BL下方横向延伸并接触所述BL。
所述用于提高LDMOS的击穿电压的方法的替代性实施例包括以下特征中的一个特征或其任何组合。所述FET是PFET，所述第一阱是所述PFET的主体区域，所述第二阱是所述PFET的漂移区域，并且将所述隔离环充电到所述第二电压增加了跨所述BL与所述漂移区域之间的纵向结的PFET击穿电压。所述FET是NFET，所述第一阱是所述NFET的漂移区域，所述第二阱是所述NFET的主体区域，并且将所述隔离环充电到所述第二电压增加了跨所述BL与所述主体区域之间的纵向结的NFET击穿电压。
附图说明
本发明是通过举例进行说明的并且不受附图限制，在附图中，类似的附图标记指示类似的元件。附图中的元件是为了简单和清楚起见而示出的并且不一定按比例绘制。
图1是根据本公开的示例实施例的p型LDMOS的横截面视图。
图2是示出了图1的LDMOS的掩模层的子集的放置的局部平面图。
图3是示出了处于“断开”状态的p型LDMOS的击穿电压(BV)特性的图形视图。
图4是示出了处于“导通”状态的p型LDMOS的BV特性的图形视图。
图5是将常规的p型LDMOS的直流(DC)安全操作区(SOA)与图1的p型LDMOS进行比较的图形视图。
图6是根据本公开的示例实施例的n型LDMOS的横截面视图。
图7是示出了处于“断开”状态的n型LDMOS的BV特性的图形视图。
图8是示出了左轴上的漏极电流和右轴上的跨导的影响的图形视图，比较了常规的n型LDMOS与图6的n型LDMOS。
图9是示出了处于“导通”状态的n型LDMOS的BV特性的图形视图。
图10是将常规的n型LDMOS的DC SOA与图6的n型LDMOS进行比较的图形视图。
图11是根据本公开的示例实施例的n型LDMOS的横截面视图。
图12是根据本公开的示例实施例的用于提高LDMOS的击穿电压的方法的流程图表示。
具体实施方式
本文所描述的各种实施例提供了通过动态偏置隔离槽区而具有提高的击穿电压的LDMOS。隔离槽区由包围LDMOS的隔离环形成并连接到在LDMOS下面延伸的掩埋层。LDMOS的隔离环电耦合到集成二极管的阳极。此二极管定位在装置操作区外部并且由p+有源区和n型区域(例如，分别为p型LDMOS 中的主体区域和n型LDMOS中的漂移区域，在装置操作期间通常被高电位偏置)构成。此类配置将隔离环上的电位降低了等于或大于二极管击穿电压的值，这导致LDMOS的击穿电压提高。偏置隔离槽区减小了掩埋层与纵向安置在掩埋层上方的LDMOS的阱之间跨临界击穿区域的电位差。本文所描述的LDMOS的实施例的其它变化是利用耦合到隔离环的类似二极管可实现的。
图1示出了根据本公开的p型LDMOS的示例实施例10。实施例10形成在p型衬底12上。N型掩埋层(NBL)14形成在p型衬底12之上并与p型衬底12接触。在一个实施例中，p型衬底12利用到接地端(未示出)的连接来接地，并且NBL充电到等于或大于接地的电压。在实施例10中，轻掺杂的NBL(LNBL)16形成在p型衬底12的一部分上并与p型衬底12的一部分接触。通过形成包括在NBL 14顶部的深n阱18和在深n阱18顶部的n阱20的纵向结构，隔离环形成以包围实施例10的场效应晶体管(FET)。隔离环与NBL 14和LNBL 16一起形成隔离槽区，以实现高电压操作。在一个实施例中，NBL 14延伸下面的p型衬底12的整个宽度，而不是形成LNBL 16。在另一个实施例中，深沟槽隔离(DTI)(未示出)围住隔离环以提高集成密度。
由硅化物24覆盖的n+区域22形成在n阱20上，以允许到隔离环的低阻抗连接。在NBL 14和LNBL 16之上形成p型外延层26，其中NBL 14与靠近NFET的栅极氧化物的硅表面之间的第一厚度27小于LNLB 16与硅表面之间的第二厚度28。FET的主体区域由超高压N阱(UHVNW)的链注入形成，包括上部部分30(UHVNW-N)和下部部分32(UHVNW-P)。下部部分32有助于将部分地由上部部分30形成的主体区域在纵向上与隔离槽区分离，这在主体区域上实现了与隔离槽区的不同偏置。
FET的漂移区域由超高压P阱34(UHVPW)形成。LNBL 16在UHVPW 34下面延伸。UHVPW34与LNBL 16之间的区域形成纵向结，所述纵向结还是FET的临界击穿区域。在各个实施例中，LNBL 16比NBL 14更深且掺杂更轻，由此增加了跨UHVPW 34与LNBL 16之间的纵向结的击穿电压。
FET的漂移区域另外受到浅沟槽隔离(STI)36的限制。栅极40形成在栅极氧化物42之上，所述栅极氧化物42跨主体区域和漂移区域延伸。栅极40被硅化物44覆盖，以促进到栅极40的低阻抗连接。侧壁间隔物46和侧壁间隔物48形成在栅极40的任一侧。漂移区域的UHVPW 34被由硅化物52覆盖的p+区域50接触。在一个实施例中，FET的漏极端连接到硅化物52。
p+区域54和n+区域56各自形成以接触主体区域的上部部分30并由硅化物58覆盖。在一个实施例中，FET的源极端连接到p+区域54，并且FET的主体端连接到n+区域56，其中源极端和主体端短接在一起。在另一个实施例中，源极端和主体端通过STI或其它隔离方案分离。在另一个实施例中，P型轻掺杂漏极(PLDD)60和p型延伸(PEXT)62与p+区域54相邻地形成。
由硅化物66覆盖的p+区域64形成在高压N阱(HVNW)区域68上，从而形成二极管。具体地，p+区域64形成二极管的阳极，并且HVNW区域68形成二极管的阴极。HVNW区域68通过与p+区域64相邻地提供更大的n型掺杂浓度来防止上部部分30耗尽。在另一个实施例中，为了简单起见，去除了HVNW区域68，并且利用p型区域64和上部部分30形成二极管。
金属互连70将n+区域22(例如，隔离槽区)的硅化物区域24连接到p+区域64(例如，阳极)的硅化物区域66。由p+区域64和HVNW区域68形成的二极管通过STI 72从FET操作区域(例如，部分地包括n+区域56、p+区域54和栅极40下方的区域)横向移位，所述STI 72形成主体区域的横向延伸。STI 74将隔离环(例如，部分地由n+区域22形成)与二极管(例如，部分地由p+区域64形成)分离。在一个实施例中，在n+区域22旁边还形成了STI 76。
高压P阱(HVPW)78另外提供了由上部部分30形成的主体区域与隔离环的隔离，因为主体区域和隔离环可以在不同的电位下操作。在另一个实施例中，STI区域36、72、74和76中的一个或多个STI区域被如硅化物阻挡层等不同的隔离方案代替。
图2示出了图1的局部平面图，以另外示出隔离环、二极管与FET装置之间的关系。实施例90包括第一漏极92和第二漏极94。源极区域96利用源极接触98、100和102连接到源极端。在一个实施例中，源极接触中的每一个包括主体接触，其中每个源极接触电短路到相应的主体接触。第一晶体管104a利用第一栅极指状物(未示出)形成在源极接触98与第一漏极92之间。第二晶体管104b利用第二栅极指状物(未示出)形成在源极接触100与第一漏极92之间。第三晶体管104c利用第三栅极指状物(未示出)形成在源极接触100与第二漏极94之间。第四晶体管104d利用第四栅极指状物(未示出)形成在源极接触102与第二漏极94之间。
隔离环106横向包围四个晶体管104a、104b、104c和104d(总称为104)。隔离环106通过多个金属互连110a、110b、110c和110d(总称为110)中的相应金属互连连接到由相应的p+区域108a、108b、108c和108d(总称为108)形成的二极管的阳极。p+区域108的总长度随着装置几何形状(例如，晶体管104的宽度和栅极指状物的数量)而缩放，这增强了隔离环对主体电压的响应。
图3、图4和图5示出了通过本公开提高的p型LDMOS的击穿特性。图3比较了常规结构132与具有将主体电位耦合到隔离环(并且因此耦合到隔离槽区)的集成二极管的新p型LDMOS 134之间的I-V曲线。图3的I-V曲线是在“断开”状态下测量的，其中栅极被设定为等于源极电压(例如，断开)，并且纵轴表示源极与漏极之间的泄漏电流。I-V曲线将穿过由相应的LDMOS结构形成的FET的漏极电流与跨FET的源极端和漏极端测量的电压降进行比较。如图3所示出的，提高的LDMOS 134的I-V曲线与常规结构132的115V相比具有126V的击穿电压，尽管两个结构均具有相同的累积长度、漂移长度、外延层26以及类似的多晶硅和金属堆叠。
如参考图1和图3所示出的，当通过p+区域54向主体区域施加0V的源极电压时，隔离槽区的电位最初由p型衬底12和在NBL 14上方的p型外延层26的接地电位限定。在其它实施例中，p型衬底12被偏置到小于或等于施加到主体区域的最低电压的低参考。随着主体区域的电位升高，HVNW区域68与p+区域64之间的电压差达到或超过在其中形成的二极管的反向击穿电压，由此使隔离槽区的电位维持在主体电位的一个反向二极管压降内，直到LNBL16与UHVPW漂移区域34之间的纵向结击穿。因此，新装置表现出相当于由p+区域64和HVNW区域68形成的反向二极管击穿电压的更高击穿电压。由于新LDMOS 134的阈值电压较低，装置具有比常规LDMOS 132略高的泄漏电流。新LDMOS 134的较低阈值电压归因于安置在源极侧处的沟道区域中的不同重掺杂浅注入。
与示出了处于“断开”状态的LDMOS的I-V特性的图3相比，图4示出了处于“导通”状态的I-V特性，其中栅极40被偏置以在源极与漏极之间形成沟道。在图4中，针对常规LDMOS的栅极偏置的增大的绝对值绘制了曲线140、142、144、146和148。针对新LDMOS的栅极偏置的增大的值绘制了曲线150、152、154、156和158，示出了每个曲线与常规LDMOS的对应曲线相比更高的击穿电压。
图5示出了图4的用于常规LDMOS 160相比于新LDMOS 162的DC SOA。例如，参考图4和图5两者，图4中用于常规LDMOS的曲线146恰好在纵向结击穿之前示出了在135V处出现的峰值电流，这类似地绘制在图5的曲线160上。新装置表现出提高的DC SOA，特别是在高栅极电压下。“导通”状态击穿电压对栅极电位也变得不太敏感。
继续参考图1，图6示出了根据本公开的n型LDMOS的另一个示例实施例170。图1和图6的隔离槽区、p型外延层、二极管的阳极以及到其的连接是相同的。因此，为简洁起见，将不重复其描述。虽然在图1与图6之间具有相同元件编号的元件在功能上是类似的，但是应当理解的是，这些元件形成的顺序不由图1或图6暗示。
实施例170的漂移区域由UHVNW的链注入形成，包括上部部分172(UHVNW-N)和下部部分174(UHVNW-P)。下部部分174有助于将部分地由上部部分172形成的漂移区域在纵向上与隔离槽区分离，这在漂移区域上实现了与隔离槽区的不同偏置。在一个实施例中，下部部分174是降低表面场(RESURF)区域。
实施例170的主体区域由P型高压(PHV)注入176形成。LNBL 16在PHV 176下面延伸。PHV 176与LNBL 16之间的区域形成纵向结，所述纵向结还是由n型LDMOS形成的n型FET的临界击穿区域。在各个实施例中，LNBL 16比NBL 14更深且掺杂更轻，由此增加了跨PHV176与LNBL 16之间的纵向结的击穿电压。在另一个实施例中，NBL 14跨p型衬底12的整个宽度延伸，并且LNBL 16未形成。
栅极178形成在栅极氧化物180之上，所述栅极氧化物180跨积累区域和主体区域延伸。栅极178被硅化物182覆盖，以促进到栅极178的低阻抗连接。侧壁间隔物184和侧壁间隔物186形成在栅极178的任一侧。漂移区域的上部部分172被由硅化物192覆盖的n+区域190接触并通过STI 194与p+区域64(例如，阳极)分离。在一个实施例中，n型FET的漏极端连接到硅化物192。n型FET的漂移区域另外受到浅沟槽隔离(STI)196的限制。
高压N型轻掺杂漏极(HVNLDD)注入198与N+区域200相邻地形成。n+区域200与p+区域202相邻。硅化物跨n+区域200和p+区域202延伸，以形成低阻抗连接。在一个实施例中，n型FET的源极端连接到n+区域200，并且n型FET的主体端连接到p+区域202，其中源极端和主体端短接在一起。在另一个实施例中，源极端和主体端通过STI或其它隔离方案分离。在另一个实施例中，STI区域74、76、194和196中的一个或多个STI区域被如硅化物阻挡层等不同的隔离方案代替。在另一个实施例中，深沟槽隔离(DTI)(未示出)围住隔离环以提高集成密度。
图7、图9和图10示出了通过本公开提高的n型LDMOS的击穿特性。图7比较了常规结构212与具有将漏极电位耦合到隔离环的集成二极管的n型LDMOS 214之间的I-V曲线。图7的I-V曲线是在“断开”状态下测量的，其中栅极被设定为等于源极电压(例如，断开)，并且纵轴表示源极与漏极之间的泄漏电流。I-V曲线将穿过由相应的LDMOS结构形成的FET的漏极电流与跨FET的源极端和漏极端测量的电压降进行比较。如图7所示出的，提高的LDMOS214的I-V曲线与常规结构212的85V相比具有108V的击穿电压，尽管两个结构均具有相同的累积长度、漂移长度、外延层26以及类似的多晶硅和金属堆叠。
如参考图6和图7所示出的，当通过n+区域190施加到漂移区域的漏极电压最初为0V时，隔离槽区的电位最初由p型衬底12和在NBL 14上方的p型外延层26的接地电位限定。在其它实施例中，p型衬底12被偏置到小于或等于施加到漏极区域的最低电压的低参考。随着漂移区域的电位升高，上部部分172与p+区域64之间的电压差达到或超过在其中形成的二极管的反向击穿电压，由此使隔离槽区的电位维持在漂移区域电位的一个反向二极管压降内，直到LNBL 16与PHV主体区域176之间的纵向结击穿。因此，新装置表现出相当于或高于由p+区域64和上部部分172形成的反向二极管击穿电压的更高击穿电压。
在漂移区域的中等偏置下，隔离环维持的电压等于漂移区域减少的反向二极管击穿电压。然而，当漂移区域的偏置具有高偏置，但低得足以防止纵向结的击穿时，漏极接触(由n+区域190形成)与阳极(例如，p+区域64)之间的上部部分172的n型区域被相邻的p型区域耗尽。因此，漏极接触与阳极之间出现了另外的电压降，从而进一步提高了跨纵向结的装置击穿电压。
图8比较了常规n型LDMOS 220与在右轴上示出的新n型LDMOS222的跨导。图8另外比较了常规n型LDMOS 224与在左轴上示出的新n型LDMOS 226的漏极电流。漏极电流比较和跨导比较均表明，从漏极到源极的“导通”电阻(例如，RDSon)不受隔离环的偏置配置影响。
与示出了处于“断开”状态的LDMOS的I-V特性的图8相比，图9示出了处于“导通”状态的I-V特性，其中栅极178被偏置以在源极与漏极之间形成沟道。在图9中，针对常规LDMOS的栅极偏置的增大的值绘制了曲线230、232、234、236和238。针对新LDMOS的栅极偏置的增大的值绘制了曲线240、242、244、246和248，示出了每个曲线与常规LDMOS的对应曲线相比更高的击穿电压。
图10示出了图9的用于常规LDMOS 250相比于新LDMOS 252的DC SOA。例如，参考图9和图10两者，图9中用于新LDMOS的曲线240恰好在纵向结击穿之前示出了在147V处出现的峰值电流，这类似地绘制在图10的曲线252上。
继续参考图6，图11示出了根据本公开的n型LDMOS的另一个实施例260。已知Kirk效应会使许多n型LDMOS装置中的SOA恶化。为了缓解此问题，在一些实施例中，在漏极有源区中添加较重掺杂的n型阱注入HVNW 262。图11示出了在漏极有源区域中以及在p+区域64周围以及在介于漏极接触(n+区域190)与阳极(p+区域64)之间的区中实施有HVNW 262的n型LDMOS的横截面。在此实施例260中，耗尽不再像图6的实施例170的情况那样沿着漏极接触与阳极之间的n型区域发生。因此，隔离环的电位比漏极电压小等于二极管反向击穿电压的恒定值。在此实施例中，FET通过NBL 14与邻近的电路系统隔离。在其它实施例中，如图6所示的LNBL 16或NBL 14和LNBL 16的组合用于形成隔离槽区。
图12示出了根据本公开的用于提高LDMOS的击穿电压的方法270。在272处，将FET的第一阱偏置到第一电压。在一个示例实施例中，第一阱是图1中的p型FET的主体区域的上部部分30或图6中的n型FET的漂移区域的上部部分172。在274处，通过连接在隔离环与第一阱之间的二极管将隔离环充电到第二电压。二极管由图1的p+区域64和HVNW区域68或由图6的p+区域64和上部部分172形成。在276处，将衬底12偏置到小于或等于第一电压的第三电压。衬底12接触FET下方的掩埋层NBL 14和LNBL 16。掩埋层14接触隔离环(例如，部分地由18和20形成)。隔离环增加了掩埋层LNBL 16与FET的第二阱之间的击穿电压。在一个示例实施例中，第二阱是图1中的p型FET的漂移区域的UHVPW区域34或图6中的n型FET的主体区域的PHV区域176。
尽管本文参考具体实施例描述了本发明，但是在不脱离如下文的权利要求书所阐述的本发明的范围的情况下，可以作出各种修改和改变。因此，本说明书和附图应被视为具有说明性而非限制性意义，并且所有此类修改旨在包括在本发明的范围内。本文关于具体实施例所描述的任何益处、优点或解决方案不旨在被解释为任何或所有权利要求的关键、必需或必要的特征或要素。
除非另外声明，否则如“第一”和“第二”等术语被用于任意地在此类术语所描述的元件之间进行区分。因此，这些术语不一定旨在指示这些元件的时间或其它优先级。

Claims (10)

1.一种横向扩散金属氧化物半导体(LDMOS)，其特征在于，包括：
场效应晶体管(FET)，所述FET包括源极端、连接到主体区域的主体端和连接到漂移区域的漏极端，所述主体区域与所述漂移区域横向分离；
隔离环，所述隔离环被安置成横向包围所述FET；
掩埋层(BL)，所述BL位于所述FET下方并与所述隔离环接触；以及
二极管，所述二极管包括阳极和阴极，所述阳极电耦合到所述隔离环，并且所述阴极电耦合到所述FET的区域。
2.根据权利要求1所述的LDMOS，其特征在于，所述FET的所述区域包括由n型阱注入形成的上部部分，以及由p型阱注入形成的下部部分安置在所述上部部分与所述BL之间。
3.根据权利要求1所述的LDMOS，其特征在于，所述BL包括位于所述FET的所述区域下方的第一部分和位于所述FET的所述区域下方的第二部分，其中所述第二部分具有相对于所述第一部分更低的掺杂浓度。
4.一种横向扩散金属氧化物半导体(LDMOS)，其特征在于，包括：
场效应晶体管(FET)，所述FET包括源极端、连接到主体区域的主体端和连接到漂移区域的漏极端；
隔离环，所述隔离环被安置成横向包围所述FET；
掩埋层(BL)，所述BL位于所述FET下方并与所述隔离环接触；以及
二极管，所述二极管包括阳极和阴极，所述阳极利用金属互连电耦合到所述隔离环，并且所述阴极电耦合到所述FET的区域。
5.根据权利要求4所述的LDMOS，其特征在于，所述FET的所述区域包括由n型阱注入形成的上部部分，以及由p型阱注入形成的下部部分安置在所述上部部分与所述BL之间。
6.根据权利要求4所述的LDMOS，其特征在于，所述BL包括位于所述FET的所述区域下方的第一部分和位于所述FET的所述区域下方的第二部分，其中所述第二部分具有相对于所述第一部分更低的掺杂浓度。
7.根据权利要求4所述的LDMOS，其特征在于，另外包括p型注入，所述p型注入安置在所述FET的所述区域与所述隔离环之间。
8.一种用于提高横向扩散金属氧化物半导体(LDMOS)的击穿电压的方法，其特征在于，包括：
将场效应晶体管(FET)的第一阱偏置到第一电压，所述第一阱与所述第二阱横向分离；
响应于所述第一电压超过连接在隔离环与所述第一阱之间的二极管的击穿电压而将所述隔离环充电到第二电压，所述隔离环横向包围所述FET并接触在所述第一阱和所述第二阱下方延伸的掩埋层(BL)；以及
将衬底偏置到小于或等于所述第一电压的第三电压，所述衬底在所述BL下方横向延伸并接触所述BL。
9.根据权利要求8所述的方法，其特征在于，所述FET是P沟道FET(PFET)，所述第一阱是所述PFET的主体区域，所述第二阱是所述PFET的漂移区域，并且将所述隔离环充电到所述第二电压增加跨所述BL与所述漂移区域之间的纵向结的PFET击穿电压。
10.根据权利要求8所述的方法，其特征在于，所述FET是N沟道FET(NFET)，所述第一阱是所述NFET的漂移区域，所述第二阱是所述NFET的主体区域，并且将所述隔离环充电到所述第二电压增加了跨所述BL与所述主体区域之间的纵向结的NFET击穿电压。
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