CN109599395B - Esd保护电路及其制造方法 - Google Patents

Esd保护电路及其制造方法 Download PDF

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CN109599395B
CN109599395B CN201811136885.2A CN201811136885A CN109599395B CN 109599395 B CN109599395 B CN 109599395B CN 201811136885 A CN201811136885 A CN 201811136885A CN 109599395 B CN109599395 B CN 109599395B
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CN109599395A (zh
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Y·F·M·索拉罗
C·E·吉尔
蔡宗哲
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Globalfoundries Semiconductor Pte Ltd
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Abstract

本发明涉及ESD保护电路及其制造方法，提供使用在源极区中的嵌入平缓PN接面形成高电压ESD GGNMOS的方法与所产生的装置。数个具体实施例包括有一衬底的一装置，该衬底包括有一ESD保护电路的一装置区；在该装置区上面的一栅极；在该装置区中的一源极区，其具有在该栅极的第一侧上横向分离的一N+植入物与一P+植入物；以及在该装置区中的一漏极区，其在该栅极与该第一侧相反的第二侧上。

Description

ESD保护电路及其制造方法
技术领域
本揭示内容涉及半导体装置中的保护电路。特别是，本揭示内容有关用于高电压半导体装置的静电放电(ESD)电路。
背景技术
双极互补金属氧化物半导体-双扩散金属氧化物半导体(BCD)为功率集成电路(IC)的技术。BCD结合数种不同的制程技术于单一芯片上：双极用于精确的模拟功能，CMOS用于数字设计，以及DMOS用于功率及高电压组件。BCD应付在功率管理、模拟数据撷取及功率致动器的领域中产品及应用的广泛范围。BCD技术广泛使用于各种应用且需要数种逻辑组件以实现许多功率管理效用。这些需求要求ESD保护的保证。
已开发出有深电流路径的p型(P+)隔离栅极接地N型通道金属氧化物半导体(p-type isolated gate-grounded N-channel metal oxide semiconductor；PI-GGNMOS)以改善低电压(LV)ESD保护装置的持有电压(Vh)。该LV ESD保护装置在源极及信道之间有P+柱段植入物(P+stud implant)而且该P+柱段植入物抵靠n型(N+)源极植入物。不过，此LVESD设计无法应用于横向扩散(LD)晶体管，例如需要调变Vh和触发电压(Vt1)的LD金属氧化物半导体(LDMOS)晶体管。
因此，亟须一种使得有ESD效能的LDMOS或GGNMOS晶体管能有改良Vh及Vt1的方法与所产生的装置。
发明内容
本揭示内容的一方面是要提供一种配合ESD设计窗格的高Vh。本揭示内容的另一方面是要高效控制/缩放(Vt1)而不牺牲装置面积且有低导通电阻(Ron)及高失效电流(It2)。外加嵌入源极区且与源极区中的N+植入物隔开的P+植入物，本揭示内容允许高效调整Vh及Vt1以满足ESD设计窗格目标而没有面积或电流密度损失。不需要额外掩模且维持反向保护能力(亦即，本体-漏极二极管)。本揭示内容的无闩锁(latchup-free)ESD保护电路提供配合ESD设计窗格的高Vh。本揭示内容的目标高电压装置有在20伏特(V)至30V之间及以上的电压。
本揭示内容的其他方面及特征会在以下说明中提出以及部分在本技艺一般技术人员审查以下内容或学习本揭示内容的实施后会明白。按照随附权利要求书的特别提示，可实现及得到本揭示内容的优点。
根据本揭示内容，有些技术效果部分可用一种装置达成，其包括：一衬底，其包括有一ESD保护电路的一装置区；在该装置区上面的一栅极；在该装置区中的一源极区，其具有在该栅极的第一侧上横向分离的一N+植入物与一P+植入物；以及在该装置区中的一漏极区，其在该栅极与该第一侧相反的第二侧上。
本揭示内容的数个方面包括该P+植入物的一边缘在该栅极的一边缘上对齐，以及该P+植入物的长度包含50纳米(nm)至500纳米的长度。其他方面包括另一N+植入物，其中各N+植入物有一边缘与该源极区的一相对边缘对齐且该P+植入物在其之间横向分离。另一方面包括在形成该N+及该P+植入物中的每一者之前形成于该装置区中的一低电压p型井(LVPW)，以及其中该N+及该P+植入物与该另一N+植入物的一部分在该LVPW中。额外数个方面包括该P+植入物与各N+植入物之间的分离是80纳米至100纳米。又数个方面包括在各N+植入物之间的该P+植入物的长度有400纳米至500纳米的长度。其他方面包括该ESD保护电路包括一LDMOS晶体管、GGNMOS晶体管或BCD晶体管。更有其他数个方面包括形成于该源极区上面的一接地垫(grounded pad)。又数个方面包括该漏极区包括N+植入物。
本揭示内容的另一方面为一种方法，其包括：提供一衬底，其具有有一ESD保护电路的一装置区；形成在该装置区上面的一栅极；形成在该装置区中的一源极区，其具有在该栅极的第一侧上横向分离的一N+植入物与一P+植入物；以及形成在该装置区中的一漏极区，其在该栅极与该第一侧相反的第二侧上。
数个方面包括形成该P+植入物，具有一边缘在该栅极的一边缘上对齐且有50纳米至500纳米的长度。其他方面包括在该源极区中形成另一N+植入物，其中各N+植入物有一边缘与该源极区的一相对边缘对齐且该P+植入物在其之间横向分离。额外数个方面包括在形成该N+及该P+植入物中的每一者之前，在该装置区中形成一LVPW，以及其中该N+及该P+植入物与该另一N+植入物的一部分形成于该LVPW中。其他方面包括形成分开80纳米至100纳米的该P+植入物及各N+植入物。又数个方面包括形成在各N+植入物之间有400纳米至500纳米的长度的该P+植入物。更有其他数个方面包括该ESD保护电路包括一LDMOS晶体管、GGNMOS晶体管或BCD晶体管。其他方面包括形成在该源极区上面的一接地垫。另一方面包括用一N+掺杂物植入该漏极区。
更有其他数个方面包括有一衬底的一装置，该衬底包括有一ESD保护电路的一装置区；在该装置区上面的一栅极；在该栅极的第一侧上位于一接地垫下面的该装置区中的一源极区，其具有在该源极区的相对两侧的一嵌入N+植入物与有长度400纳米至500纳米的一P+植入物，其中该P+植入物与各N+区分离80纳米至100纳米；以及在该装置区中的一N+漏极区，其在该栅极与该第一侧相反的第二侧上。
数个方面包括该ESD保护电路包括一LDMOS晶体管、GGNMOS晶体管或BCD晶体管。
本领域技术人员由以下详细说明可明白本揭示内容的其他方面及技术效果，其中是仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。应了解，本揭示内容能够做出其他及不同的具体实施例，以及在各种明显的方面，能够修改数个细节而不脱离本揭示内容。因此，图式及说明内容本质上应被视为图解说明用而不是用来限定。
附图说明
在此用所附图式举例说明而不是限定本揭示内容，图中类似的组件用相同的附图标记表示以及其中：
图1的横截面根据一示范具体实施例示意图标有ESD电路的MOS晶体管；
图2根据一示范具体实施例示意图示图1的MOS晶体管的运算电路；
图3的横截面根据另一示范具体实施例示意图标有ESD电路的MOS晶体管的一部分；以及
图4的横截面根据又一示范具体实施例示意图标有ESD电路的MOS晶体管。
主要附图标记说明
100 装置区
101 衬底
103 浅沟槽隔离(STI)区、STI区
105 栅极
107 源极区
109 漏极区
113 N+植入物
115 P+植入物
117 接地垫
119 高电压p型井、p型井
121 N+植入物
123 n型井
125 电气垫
127 深n型井
129 P+植入物
131 N+植入物
133 接地垫
201 电阻RB1
203 电阻RB2
401 LVPW
d 横向间距/横向分离
di 横向分离。
具体实施方式
为了解释的目的，在以下的说明中，提出许多特定细节供彻底了解示范具体实施例。不过，显然在没有该等特定细节下或用均等配置仍可实施示范具体实施例。在其他情况下，众所周知的结构及装置用方块图图标以免不必要地混淆示范具体实施例。此外，除非另有说明，在本专利说明书及权利要求书中表示成分、反应条件等等的数量、比例及数值性质的所有数字应被理解为在所有情况下可用措辞“约”来修饰。
本揭示内容针对且解决LDMOS、GGNMOS或BCD晶体管在ESD设计窗格内低效调变Vh及Vt1的当前问题。根据本揭示内容的数个具体实施例，P+植入物嵌入源极区且与源极区中的N+植入物隔开。此设计允许高效调变Vh及Vt1而没有面积或电流密度损失。P+植入物的间距允许形成平缓的接面且减少源极区中的总P+植入物剂量。相比于有抵接N+源极植入物的P+植入物的传统制程，P+植入物稍微增加基极电阻。
此外，本领域技术人员由以下详细说明可明白其他方面、特征及技术效果，其中是仅以预期的最佳模式的说明方式举例描述较佳具体实施例。本揭示内容能够做出其他及不同的具体实施例，而且能够修改其在各种不同明显方面的数个细节。因此，图式及说明内容本质上应被视为图解说明用而不是用来限定。
图1的横截面根据一示范具体实施例示意图标有ESD电路的MOS晶体管。装置区100包括ESD保护电路。在一具体实施例中，该ESD保护电路为LD晶体管。该ESD保护电路可为LDMOS晶体管、GGNMOS晶体管或BCD晶体管。衬底101为半导体衬底，例如硅衬底。在一具体实施例中，衬底101可为p型掺杂衬底。例如，该p型掺杂衬底为轻度p型掺杂衬底。其他类型的半导体衬底，包括掺杂其他类型掺杂物或浓度或无掺杂者，也可能是有用的。衬底101可由例如硅锗、锗、砷化镓或绝缘体上晶体(crystal-on-insulator；COI)，例如绝缘体上硅(SOI)来形成。浅沟槽隔离(STI)区103形成于衬底101中。STI区103延伸到在衬底101中有4000埃的深度。
栅极105在装置区中设置于衬底101的表面上。栅极105包括设置于栅极电介质(为了便于说明而未图示)上面的栅极电极。该栅极电极可为多晶硅。其他材料也可能是有用的。至于该栅极电介质，它可为氧化硅。其他栅极电介质材料也可能是有用的。栅极105可为形成多个晶体管的栅极的栅极导体。
栅极105的第一侧包括源极区107且栅极105的第二侧包括漏极区109。在该装置区中的源极区107包括数个N+植入物113以及与该等N+植入物113横向分离的P+植入物115。P+植入物115与各N+植入物113之间的横向分离(d)为80纳米至100纳米。在各N+植入物113之间的P+植入物115的长度为400纳米至500纳米。在此具体实施例中，各N+植入物113的一边缘与源极区107的相对边缘对齐且P+植入物115在其之间横向分离。在源极区107上面形成接地垫117以及在它的下面形成高电压p型井119。嵌入源极区107且与N+植入物113隔开的P+植入物115的横向分离允许高效调整Vt1及Vh。
漏极区109包括在n型井123上方且在电气垫125下方的N+植入物121。在p型井119及n型井123下方形成深n型井127。附加的P+植入物129和N+植入物131形成在STI区103之间，以及形成邻近接地垫117的接地垫133。P+掺杂物可包括硼(B)、铝(Al)、铟(In)或其组合，同时N+掺杂物可包括磷(P)、砷(As)、锑(Sb)或其组合。
参阅图2，其图示为有图1ESD电路的MOS晶体管的操作基础的原理。首先，添加P+植入物115与横向间距d显著减少如通过电阻RB1201//电阻RB2 203所算出的块体电阻(bulkresistance，RB)。嵌入源极区107的P+植入物115且与N+植入物113隔开的横向分离也用于恒定块体电流(IB)(由漏极-主体的突崩产生)，且因此，减少落在双极接面晶体管(VBE)的基极与射极之间的电压；减少βNPN；提高Vt1及Vh；横向间距d允许控制RB、Vt1及Vh以满足设计窗格目标；以及P+植入物115的间距提供更平缓的掺杂分布图且可用横向间距d调整P+在源极区107中的总浓度以及控制RB。
图3的横截面根据另一示范具体实施例示意图示有图1ESD电路的MOS晶体管的一部分。图3的MOS晶体管与图1的MOS晶体管相同，除了P+植入物115在栅极105边缘上自对齐且源极区107中只有一个N+植入物113的此情况下以外。此外，尽管图1的P+植入物115有例如400纳米至500纳米的长度，然而，在此具体实施例中，P+植入物115有50纳米至500纳米的长度。
图3的横截面根据另一示范具体实施例示意图示有图1ESD电路的MOS晶体管的一部分。图4的MOS晶体管与图1的MOS晶体管相同，除了在形成N+植入物113及P+植入物115之前形成于装置区的LVPW 401的此情况下以外。结果，在LVPW 401中形成N+植入物113、P+植入物115与另一N+植入物113的一部分。类似图1及图3，P+植入物115与N+植入物113之间的分离是80纳米至100纳米。在此情况下，横向分离di为LVPW 401边缘与N+植入物不在LVPW401内的边缘之间有50纳米至500纳米的距离。
本揭示内容的具体实施例可实现数种技术效果，包括通过操纵横向分离d参数来高效控制Vt1及Vh以满足ESD目标(设计窗格)而不需要附加屏蔽。其他技术效果包括维持反向保护能力(本体-漏极二极管)与也实现紧凑分散度(有制程稳定性)的电流密度/面积(无面积损失)。本揭示内容享有在各种工业应用例如微处理器、智能型手机、移动电话、手机、机顶盒、DVD刻录机及播放器、汽车导航、打印机及接口设备、网络及电信设备、游戏系统、数字相机、功率转换应用、功率管理、模拟数据撷取及功率致动器的任何一种中的工业可用性。因此，本揭示内容享有包括ESD电路的高电压半导体装置的数种类型的任何一种中的工业可用性。
在以上说明中，特别用数个示范具体实施例描述本揭示内容。不过，显然仍可做出各种修改及改变而不脱离本揭示内容更宽广的精神及范畴，如权利要求书所述。因此，本专利说明书及图式应被视为图解说明用而非限定。应了解，本揭示内容能够使用各种其他组合及具体实施例且在如本文所述的发明概念范畴内能够做出任何改变或修改。

Claims (16)

1.一种半导体装置，包含：
一衬底，包括有一静电放电保护电路的一装置区；
一栅极，在该装置区上面；
一源极区，在该装置区中，具有在该栅极的第一侧上横向分离的一N+植入物与一P+植入物；以及
一漏极区，在该装置区中，在该栅极与该第一侧相反的第二侧上；
另一N+植入物，其中，各N+植入物的一边缘与该源极区的一相对边缘对齐且该P+植入物在其之间横向分离；以及
低电压p型井，在形成该N+植入物及该P+植入物中的每一者之前形成于该装置区中，以及其中，该N+植入物及该P+植入物与该另一N+植入物的一部分在该低电压p型井中。
2.如权利要求1所述的半导体装置，其特征在于，该P+植入物的一边缘在该栅极的一边缘上对齐，以及该P+植入物的长度包含50纳米(nm)至500纳米的长度。
3.如权利要求1所述的半导体装置，其特征在于，该P+植入物与各N+植入物之间的分离包含80纳米至100纳米。
4.如权利要求1所述的半导体装置，其特征在于，在各N+植入物之间的该P+植入物的长度包含400纳米至500纳米的长度。
5.如权利要求1所述的半导体装置，其特征在于，该静电放电保护电路包含一横向扩散金属氧化物半导体晶体管、栅极接地N型通道金属氧化物半导体晶体管或BCD晶体管。
6.如权利要求1所述的半导体装置，进一步包含形成于该源极区上面的一接地垫。
7.如权利要求1所述的半导体装置，其特征在于，该漏极区包含N+植入物。
8.一种制造半导体装置的方法，该方法包含：
提供一衬底，具有有一静电放电保护电路的一装置区；
形成在该装置区上面的一栅极；
形成在该装置区中的一源极区，具有在该栅极的第一侧上横向分离的一N+植入物与一P+植入物；
形成在该装置区中的一漏极区，在该栅极与该第一侧相反的第二侧上；
形成在该源极区中的另一N+植入物，其中，各N+植入物有一边缘与该源极区的一相对边缘对齐且该P+植入物在其之间横向分离；以及
在形成该N+植入物及该P+植入物中的每一者之前，形成在该装置区中的一低电压p型井，以及其中，该N+植入物及该P+植入物与该另一N+植入物的一部分形成于该低电压p型井中。
9.如权利要求8所述的方法，包含：形成该P+植入物，具有一边缘在该栅极的一边缘上对齐且有50纳米(nm)至500纳米的长度。
10.如权利要求8所述的方法，包含：形成分开80纳米至100纳米的该P+植入物及各N+植入物。
11.如权利要求8所述的方法，包含：形成在各N+植入物之间有400纳米至500纳米的长度的该P+植入物。
12.如权利要求8所述的方法，其特征在于，该静电放电保护电路包含一横向扩散金属氧化物半导体晶体管、栅极接地N型通道金属氧化物半导体晶体管或BCD晶体管。
13.如权利要求8所述的方法，进一步包含：形成在该源极区上面的一接地垫。
14.如权利要求8所述的方法，包含：用一N+掺杂物植入该漏极区。
15.一种半导体装置，包含：
一衬底，包括有一静电放电保护电路的一装置区；
一栅极，在该装置区上面；
一源极区，在该栅极的第一侧上位于一接地垫下面的该装置区中，具有在该源极区的相对两侧的一嵌入N+植入物与有长度400纳米(nm)至500纳米的一P+植入物，其中，该P+植入物与各N+植入物分离80纳米至100纳米；
一N+漏极区，在该装置区中，在该栅极与该第一侧相反的第二侧上；
另一N+植入物，其中，各N+植入物的一边缘与该源极区的一相对边缘对齐且该P+植入物在其之间横向分离；以及
低电压p型井，在形成该N+植入物及该P+植入物中的每一者之前形成于该装置区中，以及其中，该N+植入物及该P+植入物与该另一N+植入物的一部分在该低电压p型井中。
16.如权利要求15所述的半导体装置，其特征在于，该静电放电保护电路包含一横向扩散金属氧化物半导体晶体管、栅极接地N型通道金属氧化物半导体晶体管或BCD晶体管。
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