TW201916313A - Ｅｓｄ保護電路及其製造方法 - Google Patents

Ｅｓｄ保護電路及其製造方法 Download PDF

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TW201916313A
TW201916313A TW106140109A TW106140109A TW201916313A TW 201916313 A TW201916313 A TW 201916313A TW 106140109 A TW106140109 A TW 106140109A TW 106140109 A TW106140109 A TW 106140109A TW 201916313 A TW201916313 A TW 201916313A
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優漢 菲德里克 米歇爾 索拉羅
凱 伊恩 吉爾
蔡宗哲
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新加坡商格羅方德半導體私人有限公司
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Abstract

提供使用在源極區中之嵌入平緩PN接面形成高電壓ESD GGNMOS的方法與所產生之裝置。數個具體實施例包括有一基板的一裝置，該基板包括有一ESD保護電路的一裝置區；在該裝置區上面的一閘極；在該裝置區中的一源極區，其具有在該閘極之第一側上橫向分離的一N+植入物與一P+植入物；以及在該裝置區中的一汲極區，其在該閘極與該第一相反的第二側上。

Description

ESD保護電路及其製造方法
本揭示內容係有關於半導體裝置中的保護電路。特別是，本揭示內容有關用於高電壓半導體裝置的靜電放電(ESD)電路。
雙極互補金屬氧化物半導體-雙擴散金屬氧化物半導體(BCD)為功率積體電路(IC)的技術。BCD結合數種不同的製程技術於單一晶片上：雙極用於精確的類比功能，CMOS用於數位設計，以及DMOS用於功率及高電壓元件。BCD應付在功率管理、類比資料擷取及功率致動器之領域中產品及應用的廣泛範圍。BCD技術廣泛使用於各種應用且需要數種邏輯組件以實現許多功率管理效用。這些需求要求ESD保護的保證。
已開發出有深電流路徑的p型(P+)隔離閘極接地N型通道金屬氧化物半導體(p-type isolated gate-grounded N-channel metal oxide semiconductor；PI-GGNMOS)以改善低電壓(LV)ESD保護裝置的持有電壓(Vh)。該LV ESD保護裝置在源極及通道之間有P+柱段植 入物(P+ stud implant)而且該P+柱段植入物抵靠n型(N+)源極植入物。不過，此LV ESD設計無法應用於橫向擴散(LD)電晶體，例如需要調變Vh和觸發電壓(Vt1)的LD金屬氧化物半導體(LDMOS)電晶體。
因此，亟須一種使得有ESD效能之LDMOS或GGNMOS電晶體能有改良Vh及Vt1的方法與所產生之裝置。
本揭示內容的一方面是要提供一種配合ESD設計窗格的高Vh。本揭示內容的另一方面是要高效控制/縮放(Vt1)而不犧牲裝置面積且有低導通電阻(Ron)及高失效電流(It2)。外加嵌入源極區且與源極區中之N+植入物隔開的P+植入物，本揭示內容允許高效調整Vh及Vt1以滿足ESD設計窗格目標而沒有面積或電流密度損失。不需要額外遮罩且維持反向保護能力(亦即，本體-汲極二極體)。本揭示內容的無閂鎖(latchup-free)ESD保護電路提供配合ESD設計窗格的高Vh。本揭示內容的標的高電壓裝置有在20伏特(V)至30V之間及以上的電壓。
本揭示內容的其他方面及特徵會在以下說明中提出以及部分在本技藝一般技術人員審查以下內容或學習本揭示內容的實施後會明白。按照隨附申請專利範圍的特別提示，可實現及得到本揭示內容的優點。
根據本揭示內容，有些技術效果部分可用一種裝置達成，其包括：一基板，其包括有一ESD保護電 路的一裝置區；在該裝置區上面的一閘極；在該裝置區中的一源極區，其具有在該閘極之第一側上橫向分離的一N+植入物與一P+植入物；以及在該裝置區中的一汲極區，其在該閘極與該第一相反的第二側上。
本揭示內容的數個方面包括該P+植入物的一邊緣在該閘極的一邊緣上對齊，以及該P+植入物的長度包含50奈米(nm)至500奈米的長度。其他方面包括另一N+植入物，其中各N+植入物有一邊緣與該源極區的一相對邊緣對齊且該P+植入物在其之間橫向分離。另一方面包括在形成該N+及該P+植入物中之每一者之前形成於該裝置區中的一低電壓p型井(LVPW)，以及其中該N+及該P+植入物與該另一N+植入物的一部分在該LVPW中。額外數個方面包括該P+植入物與各N+植入物之間的分離是80奈米至100奈米。又數個方面包括在各N+植入物之間的該P+植入物之長度有400奈米至500奈米的長度。其他方面包括該ESD保護電路包括一LDMOS電晶體、GGNMOS電晶體或BCD電晶體。更有其他數個方面包括形成於該源極區上面的一接地墊(grounded pad)。又數個方面包括該汲極區包括N+植入物。
本揭示內容的另一方面為一種方法，其包括：提供一基板，其具有有一ESD保護電路的一裝置區；形成在該裝置區上面的一閘極；形成在該裝置區中的一源極區，其具有在該閘極之第一側上橫向分離的一N+植入物與一P+植入物；以及形成在該裝置區中的一汲極區，其在 該閘極與該第一相反的第二側上。
數個方面包括形成該P+植入物，具有一邊緣在該閘極之一邊緣上對齊且有50奈米至500奈米的長度。其他方面包括在該源極區中形成另一N+植入物，其中各N+植入物有一邊緣與該源極區的一相對邊緣對齊且該P+植入物在其之間橫向分離。額外數個方面包括在形成該N+及該P+植入物中之每一者之前，在該裝置區中形成一LVPW，以及其中該N+及該P+植入物與該另一N+植入物的一部分形成於該LVPW中。其他方面包括形成分開80奈米至100奈米的該P+植入物及各N+植入物。又數個方面包括形成在各N+植入物之間有400奈米至500奈米之長度的該P+植入物。更有其他數個方面包括該ESD保護電路包括一LDMOS電晶體、GGNMOS電晶體或BCD電晶體。其他方面包括形成在該源極區上面的一接地墊。另一方面包括用一N+摻雜物植入該汲極區。
更有其他數個方面包括有一基板的一裝置，該基板包括有一ESD保護電路的一裝置區；在該裝置區上面的一閘極；在該閘極之第一側上位於一接地墊下面之該裝置區中的一源極區，其具有在該源極區之相對兩側的一嵌入N+植入物與有長度400奈米至500奈米的一P+植入物，其中該P+植入物與各N+區分離80奈米至100奈米；以及在該裝置區中的一N+汲極區，其在該閘極與該第一相反的第二側上。
數個方面包括該ESD保護電路包括一 LDMOS電晶體、GGNMOS電晶體或BCD電晶體。
熟諳此藝者由以下詳細說明可明白本揭示內容的其他方面及技術效果，其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。應瞭解，本揭示內容能夠做出其他及不同的具體實施例，以及在各種明顯的方面，能夠修改數個細節而不脫離本揭示內容。因此，圖式及說明內容本質上應被視為圖解說明用而不是用來限定。
100‧‧‧裝置區
101‧‧‧基板
103‧‧‧淺溝槽隔離(STI)區、STI區
105‧‧‧閘極
107‧‧‧源極區
109‧‧‧汲極區
113‧‧‧N+植入物
115‧‧‧P+植入物
117‧‧‧接地墊
119‧‧‧高電壓p型井、p型井
121‧‧‧N+植入物
123‧‧‧n型井
125‧‧‧電氣墊
127‧‧‧深n型井
129‧‧‧P+植入物
131‧‧‧N+植入物
133‧‧‧接地墊
201‧‧‧電阻RB1
203‧‧‧電阻RB2
401‧‧‧LVPW
d‧‧‧橫向間距/橫向分離
di‧‧‧橫向分離
在此用所附圖式舉例說明而不是限定本揭示內容，圖中類似的元件用相同的元件符號表示以及其中：第1圖的橫截面根據一示範具體實施例示意圖示有ESD電路的MOS電晶體；第2圖根據一示範具體實施例示意圖示第1圖之MOS電晶體的運算電路；第3圖的橫截面根據另一示範具體實施例示意圖示有ESD電路的MOS電晶體之一部分；以及第4圖的橫截面根據又一示範具體實施例示意圖示有ESD電路的MOS電晶體。
為了解釋的目的，在以下的說明中，提出許多特定細節供徹底瞭解示範具體實施例。不過，顯然在沒有該等特定細節下或用均等配置仍可實施示範具體實施例。在其他情況下，眾所周知的結構及裝置用方塊圖圖示 以免不必要地混淆示範具體實施例。此外，除非另有說明，在本專利說明書及申請專利範圍中表示成分、反應條件等等之數量、比例及數值性質的所有數字應被理解為在所有情況下可用措辭“約”來修飾。
本揭示內容針對且解決LDMOS、GGNMOS或BCD電晶體在ESD設計窗格內低效調變Vh及Vt1的當前問題。根據本揭示內容的數個具體實施例，P+植入物係嵌入源極區且與源極區中的N+植入物隔開。此設計允許高效調變Vh及Vt1而沒有面積或電流密度損失。P+植入物的間距允許形成平緩的接面且減少源極區中的總P+植入物劑量。相較於有抵接N+源極植入物之P+植入物的習知製程，P+植入物稍微增加基極電阻。
此外，熟諳此藝者由以下詳細說明可明白其他方面、特徵及技術效果，其中係僅以預期的最佳模式的說明方式舉例描述較佳具體實施例。本揭示內容能夠做出其他及不同的具體實施例，而且能夠修改其在各種不同明顯方面的數個細節。因此，圖式及說明內容本質上應被視為圖解說明用而不是用來限定。
第1圖的橫截面根據一示範具體實施例示意圖示有ESD電路的MOS電晶體。裝置區100包括ESD保護電路。在一具體實施例中，該ESD保護電路為LD電晶體。該ESD保護電路可為LDMOS電晶體、GGNMOS電晶體或BCD電晶體。基板101為半導體基板，例如矽基板。在一具體實施例中，基板101可為p型摻雜基板。例如， 該p型摻雜基板為輕度p型摻雜基板。其他類型的半導體基板，包括摻雜其他類型摻雜物或濃度或無摻雜者，也可能是有用的。基板101可由例如矽鍺、鍺、砷化鎵或絕緣體上晶體(crystal-on-insulator；COI)，例如絕緣體上矽(SOI)來形成。淺溝槽隔離(STI)區103形成於基板101中。STI區103延伸到在基板101中有4000埃(Å)的深度。
閘極105在裝置區中設置於基板101的表面上。閘極105包括設置於閘極電介質(為了便於說明而未圖示)上面的閘極電極。該閘極電極可為多晶矽。其他材料也可能是有用的。至於該閘極電介質，它可為氧化矽。其他閘極電介質材料也可能是有用的。閘極105可為形成多個電晶體之閘極的閘極導體。
閘極105的第一側包括源極區107且閘極105的第二側包括汲極區109。在該裝置區中的源極區107包括數個N+植入物113以及與該等N+植入物113橫向分離的P+植入物115。P+植入物115與各N+植入物113之間的橫向分離(d)為80奈米至100奈米。在各N+植入物113之間的P+植入物115的長度為400奈米至500奈米。在此具體實施例中，各N+植入物113的一邊緣與源極區107的相對邊緣對齊且P+植入物115在其之間橫向分離。在源極區107上面形成接地墊117以及在它的下面形成高電壓p型井119。嵌入源極區107且與N+植入物113隔開之P+植入物115的橫向分離允許高效調整Vt1及Vh。
汲極區109包括在n型井123上方且在電 氣墊125下方的N+植入物121。在p型井119及n型井123下方形成深n型井127。附加的P+植入物129和N+植入物131形成在STI區103之間，以及形成鄰近接地墊117的接地墊133。P+摻雜物可包括硼(B)、鋁(Al)、銦(In)或其組合，同時N+摻雜物可包括磷(P)、砷(As)、銻(Sb)或其組合。
參閱第2圖，其圖示為有第1圖ESD電路之MOS電晶體之操作基礎的原理。首先，添加P+植入物115與橫向間距d顯著減少如藉由電阻RB1 201//電阻RB2 203所算出的塊體電阻(bulk resistance，RB)。嵌入源極區107之P+植入物115且與N+植入物113隔開的橫向分離也用於恆定塊體電流(IB)(由汲極-主體的突崩產生)，且因此，減少落在雙極接面電晶體(VBE)之基極與射極之間的電壓；減少βNPN；提高Vt1及Vh；橫向間距d允許控制RB、Vt1及Vh以滿足設計窗格目標；以及P+植入物115的間距提供更平緩的摻雜分布圖且可用橫向間距d調整P+在源極區107中的總濃度以及控制RB。
第3圖的橫截面根據另一示範具體實施例示意圖示有第1圖ESD電路的MOS電晶體之一部分。第3圖的MOS電晶體與第1圖的MOS電晶體相同，除了P+植入物115在閘極105邊緣上自對齊且源極區107中只有一個N+植入物113的此情況下以外。此外，儘管第1圖的P+植入物115有例如400奈米至500奈米的長度，然而，在此具體實施例中，P+植入物115有50奈米至500奈米 的長度。
第3圖的橫截面根據另一示範具體實施例示意圖示有第1圖ESD電路的MOS電晶體之一部分。第4圖的MOS電晶體與第1圖的MOS電晶體相同，除了在形成N+植入物113及P+植入物115之前形成於裝置區的LVPW 401的此情況下以外。結果，在LVPW 401中形成N+植入物113、P+植入物115與另一N+植入物113的一部分。類似第1圖及第3圖，P+植入物115與N+植入物113之間的分離是80奈米至100奈米。在此情況下，橫向分離di為LVPW 401邊緣與N+植入物不在LVPW 401內的邊緣之間有50奈米至500奈米的距離。
本揭示內容的具體實施例可實現數種技術效果，包括藉由操縱橫向分離d參數來高效控制Vt1及Vh以滿足ESD目標(設計窗格)而不需要附加遮罩。其他技術效果包括維持反向保護能力(本體-汲極二極體)與也實現緊湊分散度(有製程穩定性)的電流密度/面積(無面積損失)。本揭示內容享有在各種工業應用例如微處理器、智慧型手機、行動電話、手機、機上盒、DVD燒錄機及播放機、汽車導航、印表機及周邊設備、網絡及電信設備、遊戲系統、數位相機、功率轉換應用、功率管理、類比資料擷取及功率致動器的任何一種中的工業可用性。因此，本揭示內容享有包括ESD電路的高電壓半導體裝置的數種類型的任何一種中的工業可用性。
在以上說明中，特別用數個示範具體實施 例描述本揭示內容。不過，顯然仍可做出各種修改及改變而不脫離本揭示內容更寬廣的精神及範疇，如申請專利範圍所述。因此，本專利說明書及圖式應被視為圖解說明用而非限定。應瞭解，本揭示內容能夠使用各種其他組合及具體實施例且在如本文所述的發明概念範疇內能夠做出任何改變或修改。

Claims (20)

  1. 一種裝置，包含：一基板，包括有一靜電放電(ESD)保護電路的一裝置區；一閘極，在該裝置區上面；一源極區，在該裝置區中，係具有在該閘極之第一側上橫向分離的一n型(N+)植入物與一p型(P+)植入物；以及一汲極區，在該裝置區中，係在該閘極與該第一相反的第二側上。
  2. 如申請專利範圍第1項所述之裝置，其中，該P+植入物的一邊緣在該閘極的一邊緣上對齊，以及該P+植入物的長度包含50奈米(nm)至500奈米的長度。
  3. 如申請專利範圍第1項所述之裝置，更包含另一N+植入物，其中，各N+植入物的一邊緣與該源極區的一相對邊緣對齊且該P+植入物在其之間橫向分離。
  4. 如申請專利範圍第3項所述之裝置，更包含在形成該N+植入物及該P+植入物中之每一者之前形成於該裝置區中的一低電壓p型井(LVPW)，以及其中，該N+植入物及該P+植入物與該另一N+植入物的一部分在該LVPW中。
  5. 如申請專利範圍第4項所述之裝置，其中，該P+植入物與各N+植入物之間的分離包含80奈米至100奈米。
  6. 如申請專利範圍第4項所述之裝置，其中，在各N+植 入物之間的該P+植入物的長度包含400奈米至500奈米的長度。
  7. 如申請專利範圍第1項所述之裝置，其中，該ESD保護電路包含一橫向擴散金屬氧化物半導體(LDMOS)電晶體、閘極接地N型通道金屬氧化物半導體(GGNMOS)電晶體或BCD電晶體。
  8. 如申請專利範圍第1項所述之裝置，更包含形成於該源極區上面的一接地墊。
  9. 如申請專利範圍第1項所述之裝置，其中，該汲極區包含N+植入物。
  10. 一種方法，包含：提供一基板，具有有一靜電放電(ESD)保護電路的一裝置區；形成在該裝置區上面的一閘極；形成在該裝置區中的一源極區，係具有在該閘極之第一側上橫向分離的一n型(N+)植入物與一p型(P+)植入物；以及形成在該裝置區中的一汲極區，係在該閘極與該第一相反的第二側上。
  11. 如申請專利範圍第1項所述之方法，包含：形成該P+植入物，具有一邊緣在該閘極之一邊緣上對齊且有50奈米(nm)至500奈米的長度。
  12. 如申請專利範圍第1項所述之方法，包含：在該源極區中形成另一N+植入物，其中，各N+植入物有一邊緣與 該源極區的一相對邊緣對齊且該P+植入物在其之間橫向分離。
  13. 如申請專利範圍第12項所述之方法，更包含：在形成該N+植入物及該P+植入物中之每一者之前，在該裝置區中形成一低電壓p型井(LVPW)，以及其中，該N+植入物及該P+植入物與該另一N+植入物的一部分形成於該LVPW中。
  14. 如申請專利範圍第13項所述之方法，包含：形成分開80奈米至100奈米的該P+植入物及各N+植入物。
  15. 如申請專利範圍第13項所述之方法，包含：形成在各N+植入物之間有400奈米至500奈米之長度的該P+植入物。
  16. 如申請專利範圍第10項所述之方法，其中，該ESD保護電路包含一橫向擴散金屬氧化物半導體(LDMOS)電晶體、閘極接地N型通道金屬氧化物半導體(GGNMOS)電晶體或BCD電晶體。
  17. 如申請專利範圍第10項所述之方法，更包含：形成在該源極區上面的一接地墊。
  18. 如申請專利範圍第10項所述之方法，包含：用一N+摻雜物植入該汲極區。
  19. 一種裝置，包含：一基板，包括有一靜電放電(ESD)保護電路的一裝置區；一閘極，在該裝置區上面； 一源極區，在該閘極之第一側上位於一接地墊下面之該裝置區中，係具有在該源極區之相對兩側的一嵌入n型(N+)植入物與有長度400奈米(nm)至500奈米的一p型(P+)植入物，其中，該P+植入物與各N+區分離80奈米至100奈米；以及一N+汲極區，在該裝置區中，係在該閘極與該第一相反的第二側上。
  20. 如申請專利範圍第19項所述之裝置，其中，該ESD保護電路包含一橫向擴散金屬氧化物半導體(LDMOS)電晶體、閘極接地N型通道金屬氧化物半導體(GGNMOS)電晶體或BCD電晶體。
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US10340266B2 (en) 2019-07-02
TWI678787B (zh) 2019-12-01
CN109599395A (zh) 2019-04-09

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