CN109411466B - 用于esd保护的高保持高电压fet及其制造方法 - Google Patents

用于esd保护的高保持高电压fet及其制造方法 Download PDF

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CN109411466B
CN109411466B CN201810550609.4A CN201810550609A CN109411466B CN 109411466 B CN109411466 B CN 109411466B CN 201810550609 A CN201810550609 A CN 201810550609A CN 109411466 B CN109411466 B CN 109411466B
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CN109411466A (zh
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Y·F·M·索拉罗
V·S·肖帕里
C·E·吉尔
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Globalfoundries Semiconductor Pte Ltd
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Abstract

本发明涉及用于ESD保护的高保持高电压FET及其制造方法，提供一种在源极侧形成具有自对准P+植入物与LVPW区的LDMOS的方法、以及所产生的装置。具体实施例包括形成位在p型衬底中的DNWELL；形成位在该DNWELL中的PWHV；形成位在该DNWELL中的NW；形成位在该PWHV中的LVPW；形成穿过该LVPW并分别穿过该DNWELL与NW的STI结构；形成位在该PWHV上方的栅极；形成位在该LVPW中的第一与第二P+植入物，该第二P+植入物的边缘与该栅极的边缘对准；形成位在该LVPW中介于该第一STI结构与该第二P+植入物之间的第一N+植入物、及位在该NW中相邻于该第二STI结构的第二N+；以及形成分别位在该第一与第二P+与N+植入物上方的接触部、及位在该第二N+植入物上方的电接触部。

Description

用于ESD保护的高保持高电压FET及其制造方法
技术领域
本发明涉及静电放电(electrostatic discharge；ESD)保护装置。本发明尤其适用于高保持高电压(high holding high voltage；HHHV)场效晶体管(FET)。
背景技术
由于需要更高的速度及装置比例缩放(scaling)，ESD对生产良率及产品质量的影响正日益更加显著。一般来说，ESD保护装置通过穿过具有高电流分流能力的集成电路(IC)提供路径来运作。高保持电压(VH)使此类装置能够进行锁存(latch-up)安全运作。然而，已知的高电压(HV)栅极接地N通道金属氧化物半导体(gate-grounded N-channel metaloxide semiconductor；GGNMOS)箝制呈现低VH，例如：低于漏极电压(VDD)。另外，在不包含装置面积之下，已知的解决方案无法使设计人员有能力有效率地控制/比例缩放VH。
因此，需要有方法能够形成一种不牺牲装置面积但呈现高VH且能够有效率控制Vt1与VH的ESD装置，还需要所产生的装置。
发明内容
本发明的一态样为一种形成侧向扩散金属氧化物半导体(laterally diffusedmetal oxide semiconductor；LDMOS)的程序，其在装置的源极侧具有附加自对准p型(P+)植入物、及第二本体井(低电压p型井(LVPW))区。
本发明的另一态样为一种LDMOS，其在装置的源极侧具有附加自对准P+植入物、及LVPW区。
本发明的附加态样及其它特征将会在以下说明中提出，并且对于审查以下内容的所属领域技术人员部分将会显而易见，或可经由实践本发明来学习。可如随附权利要求书中特别指出的内容来实现并且获得本发明的优点。
根据本发明，有一些技术功效可通过一种方法来部分达成，该方法包括：形成位在一部分p型衬底(p-sub)中的n掺杂井(DNWELL)区；形成位在一部分该DNWELL区中的高电压p型井(PWHV)区；形成位在一部分该DNWELL区中与该PWHV区侧向隔开的n型井(NW)；形成位在一部分该PWHV区中的LVPW区；形成分别穿过一部分该LVPW区及穿过一部分该DNWELL区与NW的第一及第二浅沟槽隔离(STI)结构；形成位在该PWHV区上方的栅极；形成位在一部分该LVPW区中侧向隔开的第一与第二P+植入物，该第二P+植入物的边缘与该栅极的边缘对准；形成位在该LVPW区中介于该第一STI结构与该第二P+植入物之间并与的相邻的第一n型(N+)植入物、及位在该NW中相邻于该第二STI结构的第二N+；以及形成分别位在该第一与第二P+与N+植入物上方的第一与第二接触部(contact)、及位在该第二N+植入物上方的电接触部。
本发明的一态样包括形成具有边缘延展通过该第二P+植入物的边缘一距离、并且位在一部分该栅极底下的该LVPW区。其它态样包括该距离为0.3微米(μm)至1.5μm。进一步态样包括形成具有边缘在最接近该栅极的该第二P+植入物的边缘前一距离处终止的该LVPW区。另一态样包括该距离为0.1μm至0.3μm。附加态样包括形成分别位在该第一与第二N+与P+植入物各者上方的接触部；以及形成位在该第二N+植入物上方的电接触部。其它态样包括形成分别透过一部分该p型衬底、该p型衬底与DNWELL区、及该DNWELL、PWHV与LVPW区侧向隔开的第一、第二及第三STI结构，其中，该第三STI结构的边缘相邻于该第一P+植入物；形成位在一部分该p型衬底中介于该第一与第二STI结构之间并与的相邻的P+植入物；形成位在一部分该DNWELL区中介于该第二与第三STI结构之间并与的相邻的N+植入物；以及形成穿过一部分该p型衬底与DNWELL区并且相邻于该NW与第二N+植入物的第四STI结构。进一步态样包括形成位在该P+与N+植入物各者上方的接触部。附加态样包括在形成该栅极前，先形成位在该PWHV与DNWELL区的各别部分上方的栅极介电层。
本发明的另一态样为一种装置，其包括：位在一部分p型衬底中的DNWELL区；位在一部分该DNWELL区中的PWHV区；位在一部分该DNWELL区中与该PWHV区侧向隔开的NW；位在一部分该PWHV区中的LVPW区；位在一部分该LVPW区中侧向隔开的第一与第二P+植入物、及介于该第一与第二P+植入物之间的第一N+植入物；位在一部分该NW中的第二N+植入物；穿过一部分该LVPW区介于该第一P+植入物与该第一N+植入物之间并与的相邻的第一STI结构；穿过一部分该DNWELL区与NW的第二STI结构；以及位在该PWHV区上方具有边缘而与该第二P+植入物的边缘对准的栅极。
该装置的态样包括该LVPW区的边缘延展通过该第二P+植入物的边缘一距离，并且位在一部分该栅极底下。其它态样包括该距离为0.3μm至1.5μm。进一步态样包括该LVPW区的边缘在最接近该栅极的该第二P+植入物的边缘前一距离处终止。附加态样包括该距离为0.1μm至0.3μm。另一态样包括分别位在该第一与第二N+与P+植入物各者上方的接触部；以及位在该第二N+植入物上方的电接触部。其它态样包括分别透过一部分该p型衬底、该p型衬底与DNWELL区、及该DNWELL、PWHV与LVPW区侧向隔开的第一、第二及第三STI结构，其中，该第三STI结构的边缘相邻于该第一P+植入物；位在一部分该p型衬底中介于该第一与第二STI结构之间并与的相邻的P+植入物；位在一部分该DNWELL区中介于该第二与第三STI结构之间并与的相邻的N+植入物；以及穿过一部分该p型衬底与DNWELL区并且相邻于该NW与第二N+植入物的第四STI结构。进一步态样包括位在该P+与N+植入物各者上方的接触部。另一态样包括介于该PWHV及DNWELL区与该栅极之间的栅极介电层。
本发明的再一态样为一种方法，其包括：形成位在一部分p型衬底中的DNWELL区；形成位在一部分该DNWELL区中的PWHV区；形成位在一部分该DNWELL区中与该PWHV区侧向隔开的NW；形成位在一部分该PWHV区中的LVPW区；形成位在一部分该LVPW区中侧向隔开的第一与第二P+植入物、及介于该第一与第二P+植入物之间的第一N+植入物；形成位在一部分该NW中的第二N+植入物；形成穿过一部分该LVPW区介于该第一P+植入物与该第一N+植入物之间并与的相邻的第一STI结构、及穿过一部分该N+植入物、NW及DNWELL区的第二STI；以及形成位在该PWHV区上方具有边缘而与该第二P+植入物的边缘对准的栅极，并且该栅极的该边缘位在该LVPW区的边缘上方。本发明的态样包括该第二P+植入物的该边缘与该LVPW区的该边缘之间的距离为0.3μm至1.5μm。
本发明的附加态样及技术功效经由以下详细说明对于所属领域技术人员将会轻易地变为显而易见，其中本发明的具体实施例单纯地通过经深思用以实行本发明的最佳模式的说明来描述。如将会了解的是，本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改，全都不会脱离本发明。因此，图式及说明本质上要视为说明性，而不是作为限制。
附图说明
本发明是在随附图式的附图中举例来说明，但非作为限制，图中相似的参考组件符号指类似的组件，并且其中：
图1根据一例示性具体实施例，示意性绘示在装置的源极侧具有附加自对准P+植入物及LVPW区的LDMOS晶体管的截面图；
图2示意性绘示图1的LDMOS晶体管的ESD运作原理；以及
图3根据一例示性具体实施例，示意性绘示在装置的源极侧具有附加自对准P+植入物及「拉回」LVPW区的LDMOS的截面图。
主要组件符号说明：
101 DNWELL区
103 p型衬底
105 PWHV区
107 NW
109 LVPW区
111、113、115 STI结构
117、119、121 STI结构
123 栅极
125 栅极介电层
127、135 P+植入物
129 P+植入物或P+条体
131、137、139 N+植入物
133、303 距离
141 接触部
143 电接触部
201、203 线条
301 LVPW区。
具体实施方式
在底下的说明中，为了解释，提出许多特定细节以便透彻理解例示性具体实施例。然而，应显而易知的是，没有这些特定细节或利用均等配置也可实践例示性具体实施例。在其它实例中，众所周知的结构及装置是以方块图形式来展示，为的是要避免不必要地混淆例示性具体实施例。另外，除非另有所指，本说明书及权利要求书中用来表达成分、反应条件等等的量、比率、及数值特性的所有数字都要了解为在所有实例中是以「约」一语来修饰。
本发明因应并解决已知ESD保护解决方案的当前问题，其呈现低VH，因此非属锁存安全，而且还牺牲装置面积才能有效率地控制/比例缩放凭靠形成HV ESD保护装置所带来的Vt1与VH。该等问题特别是通过在LDMOS的源极侧添加自对准P+植入物与LVPW区来解决。
根据本发明的具体实施例的方法包括形成位在一部分p型衬底中的DNWELL区。在一部分该DNWELL区中形成PWHV区。在一部分该DNWELL区中形成与该PWHV区侧向隔开的NW。在一部分该PWHV区中形成LVPW区。分别穿过一部分该LVPW区及穿过一部分该DNWELL区与NW形成第一及第二STI结构。在该PWHV与DNWELL区上方形成栅极，并且在一部分该LVPW区中形成侧向隔开的第一与第二P+植入物，该第二P+植入物的边缘与该栅极的边缘对准。形成位在该LVPW区中介于该第一STI结构与该第二P+植入物之间并与的相邻的第一N+植入物，还有位在该NW中相邻于该第二STI结构的第二N+。分别在该第一与第二P+与N+植入物上方形成第一与第二接触部，并且在该第二N+植入物上方形成电接触部。
单纯地通过所思最佳模式的描述，还有其它态样、特征、以及技术功效经由下文的详细说明对于所属领域技术人员将显而易知，其中表示并且说明的是较佳具体实施例。本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改。因此，图式及说明本质上要视为说明性，而不是作为限制。
图1根据一例示性具体实施例，示意性绘示在装置的源极侧具有附加自对准P+植入物及LVPW区的LDMOS晶体管的截面图。请参阅图1，在一部分p型衬底103中形成DNWELL区101。在装置的源极侧上一部分DNWELL区101中形成PWHV区105。在一部分DNWELL区101中形成与PWHV区105侧向隔开的NW 107。举例来说，通过以例如每立方公分(cm3)1e17至1e19cm3的剂量进行硼离子布植，在一部分PWHV区105中形成LVPW区109。分别穿过一部分LVPW区109及穿过一部分DNWELL区101与NW 107形成侧向隔开的STI结构111及113。同样地，分别穿过一部分p型衬底103；p型衬底103与DNWELL区101；DNWELL区101、PWHV区105与LVPW区109；以及p型衬底103与DNWELL区101，形成STI结构115、117、119与121。
栅极123分别在PWHV区105与DNWELL区101的各别部分上方所形成的栅极介电层125上方由例如多晶硅所构成。在一部分LVPW区109中形成P+植入物127与129及N+植入物131。特别的是，硅化P+植入物129的边缘与栅极123的边缘自对准。用于形成P+植入物129的掺杂浓度大于用于形成LVPW区109的掺杂浓度，其大于用于形成PWHV区105的掺杂浓度。再者，LVPW区109形成有边缘，其延展例如0.3μm至1.5μm(距离133)，通过P+植入物129的边缘并位在一部分栅极123底下。然而，应注意的是，距离133亦取决于栅极123的长度，并且对于更小的栅极长度而言，距离133应该更靠近下限0.3μm并远离上限1.5μm。亦应注意的是，距离133的范围是基于实验为了说明而提供，用意非作为限制。分别在一部分p型衬底103及DNWELL区101中形成P+植入物135及N+植入物137，并且在NW 107上面形成N+植入物139。另外，分别在P+植入物135、N+植入物137、P+植入物127、以及N+植入物131与P+植入物129上方形成接触部141。再者，在N+植入物139上方形成电接触部143。
图2示意性绘示图1的LDMOS晶体管的ESD运作原理。请参阅图2，由于LVPW区109的浓度(RB1)(线条201)更高，并且存在P+条体129(RB2)(线条203)，装置的体电阻(RB)得以降低。另外，对于恒定的基极电流(IB)(因漏极-本体的崩溃而产生)，连同NPN晶体管的贝他(βNPN)，落在双极性接面晶体管的基极与射极之间的电压(VBE)得以降低。特别的是，βNPN因基极中少数载子的复合更高而降低。所以，图1的装置的VH得以提升。
图3根据一例示性具体实施例，示意性绘示在装置的源极侧具有附加自对准P+植入物及「拉回」LVPW区的LDMOS的截面图。图3的装置几乎等同于图1的装置，差别为在此实例中，LVPW区301在远离P+植入物129的边缘最接近栅极123例如0.1μm至0.3μm(距离303)处终止形成有边缘，亦即LVPW区301下迭于P+植入物129。相比之下，图1的LVPW区109的边缘延展通过P+植入物129的边缘，并且位在一部分栅极123底下。此外，应注意的是，距离303的范围是基于实验为了说明而提供，用意非作为限制。
本发明的具体实施例可达到数种技术功效，包括VH提升且Vt1与VH的控制有效率，但不牺牲装置面积，也不需要另外的屏蔽。另外，连同紧密的分散度(无程序而稳定)，逆转保护能力(本体-漏极二极管)得以维持。再者，如相比于已知程序，例如栅极长度(LG)调大及加入更多本体接触部，得以获得类似或更大的电流密度/面积。举例而言，本发明的具体实施例在各种工业应用中享有实用性，如：微处理器、智能型手机、移动电话、蜂巢式手机、机顶盒、DVD录像机与播放器、汽车导航、打印机与外围装置、网络链接与电信设备、游戏系统、以及数字相机。本发明在包括HHHV FET等各种类型的高度整合型半导体装置的任一者中享有产业利用性。
在前述说明中，本发明乃参照其具体例示性具体实施例作说明。然而，明显的是，可对其实施各种修改和变更而不脱离本发明较广的精神与范畴，如权利要求书所提。本说明书及图式从而要视为说明性而非作为限制。了解的是，本发明能够使用各种其它组合及具体实施例，并且如本文中所表达，能够在本发明概念的范畴内作任何变更或修改。

Claims (20)

1.一种用于静电放电保护的方法，其包含：
形成位在一部分p型衬底中的n掺杂井区；
形成位在一部分该n掺杂井区中的高电压p型井区；
形成位在一部分该n掺杂井区中与该高电压p型井区侧向隔开的n型井；
形成位在一部分该高电压p型井区中的低电压p型井区；
形成分别穿过一部分该低电压p型井区及穿过一部分该n掺杂井区与n型井的第一浅沟槽隔离结构及第二浅沟槽隔离结构；
形成位在该p型衬底上方的栅极；
形成位在一部分该低电压p型井区中侧向隔开的第一P+植入物与第二P+植入物，该第二P+植入物的边缘与该栅极的边缘对准；
形成位在该低电压p型井区中介于该第一浅沟槽隔离结构与该第二P+植入物之间并与该第一浅沟槽隔离结构与该第二P+植入物相邻的第一N+植入物、及位在该n型井中相邻于该第二浅沟槽隔离结构的第二N+植入物；以及
形成分别位在该第一P+植入物、第一N+植入物、第二P+植入物与第二N+植入物上方的第一接触部与第二接触部、及位在该第二N+植入物的一部分上方而不形成该第一接触部与该第二接触部的电接触部。
2.如权利要求1所述的方法，其包含形成具有边缘延展通过该第二P+植入物的边缘一距离、并且位在一部分该栅极底下的该低电压p型井区。
3.如权利要求2所述的方法，其特征在于，该距离包含0.3微米(μm)至1.5μm。
4.如权利要求1所述的方法，其包含形成具有边缘在最接近该栅极的该第二P+植入物的边缘前一距离处终止的该低电压p型井区。
5.如权利要求4所述的方法，其特征在于，该距离包含0.1μm至0.3μm。
6.如权利要求1所述的方法，进一步包含：
形成分别位在该第一N+植入物、第一P+植入物、第二N+植入物与第二P+植入物各者上方的接触部；以及
形成位在该第二N+植入物的一部分上方而不形成该接触部的电接触部。
7.如权利要求1所述的方法，进一步包含：
形成分别透过一部分该p型衬底、该p型衬底与n掺杂井区、及该n掺杂井区、高电压p型井区与低电压p型井区侧向隔开的第一浅沟槽隔离结构、第二浅沟槽隔离结构及第三浅沟槽隔离结构，其中，该第三浅沟槽隔离结构的边缘相邻于该第一P+植入物；
形成位在一部分该p型衬底中介于该第一浅沟槽隔离结构与第二浅沟槽隔离结构之间并与该第一浅沟槽隔离结构与第二浅沟槽隔离结构相邻的P+植入物；
形成位在一部分该n掺杂井区中介于该第二浅沟槽隔离结构与第三浅沟槽隔离结构之间并与该第二浅沟槽隔离结构与第三浅沟槽隔离结构相邻的N+植入物；以及
形成穿过一部分该p型衬底与n掺杂井区并且相邻于该n型井与第二N+植入物的第四浅沟槽隔离结构。
8.如权利要求7所述的方法，其包含形成位在该P+植入物与N+植入物各者上方的接触部。
9.如权利要求1所述的方法，进一步包含在形成该栅极前，先形成位在该高电压p型井区与n掺杂井区的各别部分上方的栅极介电层。
10.一种用于静电放电保护的装置，其包含：
位在一部分p型衬底中的n掺杂井区；
位在一部分该n掺杂井区中的高电压p型井区；
位在一部分该n掺杂井区中与该高电压p型井区侧向隔开的n型井；
位在一部分该高电压p型井区中的低电压p型井区；
位在一部分该低电压p型井区中侧向隔开的第一P+植入物与第二P+植入物、及介于该第一P+植入物与第二P+植入物之间的第一N+植入物；
位在一部分该n型井中的第二N+植入物；
穿过一部分该低电压p型井区介于该第一P+植入物与该第一N+植入物之间并与该第一P+植入物与该第一N+植入物相邻的第一浅沟槽隔离结构；
穿过一部分该n掺杂井区与n型井的第二浅沟槽隔离结构；以及
位在该高电压p型井区上方具有边缘而与该第二P+植入物的边缘对准的栅极。
11.如权利要求10所述的装置，其特征在于，该低电压p型井区的边缘延展通过该第二P+植入物的边缘一距离，并且位在一部分该栅极底下。
12.如权利要求11所述的装置，其特征在于，该距离包含0.3微米(μm)至1.5μm。
13.如权利要求10所述的装置，其特征在于，该低电压p型井区的边缘在最接近该栅极的该第二P+植入物的边缘前一距离处终止。
14.如权利要求13所述的装置，其特征在于，该距离包含0.1μm至0.3μm。
15.如权利要求10所述的装置，进一步包含：
分别位在该第一N+植入物、第一P+植入物、第二N+植入物与第二P+植入物各者上方的接触部；以及
位在该第二N+植入物的一部分上方而不形成该接触部的电接触部。
16.如权利要求10所述的装置，进一步包含：
分别透过一部分该p型衬底、该p型衬底与n掺杂井区、及该n掺杂井区、高电压p型井区与低电压p型井区侧向隔开的第一浅沟槽隔离结构、第二浅沟槽隔离结构及第三浅沟槽隔离结构，其中，该第三浅沟槽隔离结构的边缘相邻于该第一P+植入物；
位在一部分该p型衬底中介于该第一浅沟槽隔离结构与第二浅沟槽隔离结构之间并与该第一浅沟槽隔离结构与第二浅沟槽隔离结构相邻的P+植入物；
位在一部分该n掺杂井区中介于该第二浅沟槽隔离结构与第三浅沟槽隔离结构之间并与该第二浅沟槽隔离结构与第三浅沟槽隔离结构相邻的N+植入物；以及
穿过一部分该p型衬底与n掺杂井区并且相邻于该n型井与第二N+植入物的第四浅沟槽隔离结构。
17.如权利要求16所述的装置，其包含：
位在该P+植入物与N+植入物各者上方的接触部。
18.如权利要求10所述的装置，进一步包含：
介于该高电压p型井区及n掺杂井区与该栅极之间的栅极介电层。
19.一种用于静电放电保护的方法，其包含：
形成位在一部分p型衬底中的n掺杂井区；
形成位在一部分该n掺杂井区中的高电压p型井区；
形成位在一部分该n掺杂井区中与该高电压p型井区侧向隔开的n型井；
形成位在一部分该高电压p型井区中的低电压p型井区；
形成位在一部分该低电压p型井区中侧向隔开的第一P+植入物与第二P+植入物、及介于该第一P+植入物与第二P+植入物之间的第一N+植入物；
形成位在一部分该n型井中的第二N+植入物；
形成穿过一部分该低电压p型井区介于该第一P+植入物与该第一N+植入物之间并与该第一P+植入物与该第一N+植入物相邻的第一浅沟槽隔离结构、及穿过一部分该N+植入物、n型井及n掺杂井区的第二浅沟槽隔离结构；以及
形成位在该高电压p型井区上方具有边缘而与该第二P+植入物的边缘对准的栅极，并且该栅极的该边缘位在该低电压p型井区的边缘上方。
20.如权利要求19所述的方法，其特征在于，该第二P+植入物的该边缘与该低电压p型井区的该边缘之间的距离包含0.3微米(μm)至1.5μm。
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