CN107910357A - 一种低导通电阻功率半导体器件 - Google Patents

一种低导通电阻功率半导体器件 Download PDF

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CN107910357A
CN107910357A CN201711007210.3A CN201711007210A CN107910357A CN 107910357 A CN107910357 A CN 107910357A CN 201711007210 A CN201711007210 A CN 201711007210A CN 107910357 A CN107910357 A CN 107910357A
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polysilicon gate
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刘斯扬
戴志刚
吴其祥
叶然
徐志远
孙伟锋
陆生礼
时龙兴
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Southeast University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

一种低导通电阻功率半导体器件，其特征在于，在P型体区内横向设有凹槽且所述凹槽向N型漂移区延伸、经过高压N型区后进入N型漂移区，最终止于浅槽隔离区的边界，在P型体区的表面以及凹槽的底部和侧壁依次注硼、注磷、生长二氧化硅层1和二氧化硅层2，并分别由此形成P型源区、N源型区，隔离氧化层和栅氧化层，在P型源区的表面及N型源区的一部分表面上设有源极金属接触，在栅氧化层的表面设有多晶硅栅极，所述多晶硅栅极的中间部分向下延伸至凹槽底部的栅氧化层的上表面，所述隔离氧化层将源极金属接触和多晶硅栅极隔开。本发明结构与传统的功率半导体器件相比，在保持较高的击穿电压的同时，能得到极低的导通电阻，并具有较高的可靠性。

Description

一种低导通电阻功率半导体器件
技术领域
本发明属于半导体器件领域，尤其涉及一种低导通电阻的功率半导体器件。
背景技术
功率半导体器件具有高耐压、高工作电流及高可靠性等优势，被广泛应用在半导体集成电路中。与传统半导体器件相比，功率半导体器件一般具有一个低掺杂的漂移区，由于漂移区具有很高的电阻，在施加高压时，漂移区会承担大部分电压，提高器件的高压性能。
对于功率半导体器件而言，一方面，要提高器件的击穿电压需要引入更长或更低掺杂浓度的漂移区，相应的，器件的导通电阻会大大提高。但另一方面，随着器件导通电阻的提高，器件的功耗和响应速度等性能会恶化，无法满足更高性能应用的需求。在尽量不影响击穿电压的情况下，如何得到低导通电阻的功率半导体器件，成为了本领域人员致力研究的方向。
发明内容
针对上述功率半导体的导通电阻和击穿电压之间的矛盾关系，本发明提供一种低导通电阻的功率半导体器件，与传统的器件相比，可在保持较高击穿电压的同时，获得极低的导通电阻。
本发明采用如下技术方案：
一种低导通电阻的功率半导体器件，包括：P型衬底，在P型衬底的上方设有高压N型区，在高压N型区内设有N型漂移区和P型体区，在N型漂移区内设有浅槽隔离区和N型漏区，在N型漏区的上方设有漏极金属接触，其特征在于，在P型体区内横向设有凹槽且所述凹槽向N型漂移区延伸、经过高压N型区后进入N型漂移区，最终止于浅槽隔离区的边界，在P型体区的表面以及凹槽的底部和侧壁依次注硼、注磷、生长二氧化硅层1和二氧化硅层2，并分别由此形成P型源区、N源型区，隔离氧化层和栅氧化层，在P型源区的表面及N型源区的一部分表面上设有源极金属接触，在栅氧化层的表面设有多晶硅栅极，所述多晶硅栅极的中间部分向下延伸至凹槽底部的栅氧化层的上表面，所述隔离氧化层将源极金属接触和多晶硅栅极隔开，所述多晶硅栅极的向下延伸部分的深度为0.5μm～2.5μm，且多晶硅栅极的向下延伸部分与浅槽隔离区相邻，多晶硅栅极的上方靠近浅槽隔离区的部分向漏端延伸并盖过浅槽隔离区的上表面，浅槽隔离区的纵向宽度和多晶硅栅极的向下延伸部分的宽度相等，且浅槽隔离区的沟槽深度超过多晶硅栅极的向下延伸部分的深度0.1μm～0.3μm。
与现有技术相比，本发明具有如下优点：
(1)本发明结构与传统的功率半导体器件相比，在保持较高的击穿电压的同时，能得到极低的导通电阻。与传统功率半导体器件结构相比，本发明结构的多晶硅栅极的中间部分向下延伸至硅中(如图1所示)，在相同的器件面积下，致使栅极感应形成的含可移动电子的薄表面区域增加(如图6所示)，器件的有效导电面积增加，在器件开启时获得更大的电流，从而具有更低的导通电阻(如图7所示)。
(2)本发明结构在使器件具备极低的导通电阻的同时，又能保持击穿电压基本不变(如图8所示)。由于浅槽隔离区10紧靠多晶硅栅极9，且深度超过多晶硅栅极的底部，可以屏蔽多晶硅栅极向下延伸部分的下方的峰值电场。如图9的圆圈内所示，器件该处的电场峰值明显降低，电势由整个浅槽隔离区10共同承担。浅槽隔离区10的纵向宽度等于栅极向下延伸部分的宽度，在不阻挡栅极两侧的沟道的同时，屏蔽了部分栅极拐角处的电场，同时对两侧的漂移区进行辅助耗尽，降低了器件表面多晶硅栅极末端的峰值电场。如图10的圆圈内所示，栅极末端的峰值电场也大大降低，从而使得器件的击穿电压保持不变。
(3)本发明结构具有较高的可靠性。由于浅槽隔离区10对器件两侧的漂移区进行辅助耗尽，降低了多晶硅栅极向下延伸部分的底部和器件表面多晶硅栅极末端的峰值电场，从而大大降低了器件的碰撞电离率。如图11所示，器件的碰撞电离率的峰值有明显的降低。因此，器件的可靠性得到了大幅提升。
附图说明
图1是三维立体剖面图，图示了本发明中低导通电阻的功率半导体器件的立体剖面结构(不含漏、源极金属接触及隔离氧化层)。
图2是三维立体剖面图，图示了本发明中低导通电阻的功率半导体器件的立体剖面结构(含漏、源极金属接触及隔离氧化层)。
图3为图2所示本发明中低导通电阻的功率半导体器件俯视结构示意图。
图4是剖面图，图示了本发明中功率半导体器件的立体剖面图2中BB’剖面的器件剖面结构。
图5是剖面图，图示了本发明中功率半导体器件的立体剖面图2中CC’剖面的器件剖面结构。
图6是剖面图，图示了传统结构的功率半导体器件的立体剖面图1中AA’剖面的器件剖面结构。
图7所示为本发明中低导通电阻的功率半导体器件与传统功率半导体器件的I-V结果比较图。
图8所示为本发明中低导通电阻的功率半导体器件与传统功率半导体器件的关态击穿特性结果的比较图。
图9所示为本发明功率半导体器件有无浅槽隔离区10时，如图4所示BB’剖面的硅与硅氧化物界面处电场分布结果比较图。
图10所示为本发明功率半导体器件有无浅槽隔离区10时，如图5所示CC’剖面的硅与硅氧化物界面处电场分布结果比较图。
图11所示为本发明功率半导体器件有无浅槽隔离区10时，如图4所示BB’剖面的硅与硅氧化物界面处碰撞电离率分布结果比较图。
具体实施方式
一种低导通电阻的功率半导体器件，包括：P型衬底1，在P型衬底1的上方设有高压N型区2，在高压N型区2内设有N型漂移区3和P型体区4，在N型漂移区3内设有浅槽隔离区10和N型漏区5，在N型漏区5的上方设有漏极金属接触11，在P型体区4内横向设有凹槽且所述凹槽向N型漂移区3延伸、经过高压N型区2后进入N型漂移区3，最终止于浅槽隔离区10的边界，在P型体区4的表面以及凹槽的底部和侧壁依次注硼、注磷、生长二氧化硅层1和二氧化硅层2，并分别由此形成P型源区7、N源型区6、隔离氧化层13和栅氧化层8，在P型源区7的表面及N型源区6的一部分表面上设有源极金属接触12，在栅氧化层8的表面设有多晶硅栅极9，所述多晶硅栅极9的中间部分向下延伸至凹槽底部的栅氧化层8的上表面，所述隔离氧化层13将源极金属接触12和多晶硅栅极9隔开。
所述多晶硅栅极9的向下延伸部分的深度为0.5μm～2.5μm，且多晶硅栅极9的向下延伸部分与浅槽隔离区10相邻，多晶硅栅极9的上方靠近浅槽隔离区10的部分向漏端延伸并盖过浅槽隔离区10的上表面。
所述浅槽隔离区10的纵向宽度和多晶硅栅极9的向下延伸部分的宽度相等，且浅槽隔离区10的沟槽深度超过多晶硅栅极9的向下延伸部分的深度0.1μm～0.3μm。

Claims (3)

1.一种低导通电阻功率半导体器件，包括：P型衬底(1)，在P型衬底(1)的上方设有高压N型区(2)，在高压N型区(2)内设有N型漂移区(3)和P型体区(4)，在N型漂移区(3)内设有浅槽隔离区(10)和N型漏区(5)，在N型漏区(5)的上方设有漏极金属接触(11)，其特征在于，在P型体区(4)内横向设有凹槽且所述凹槽向N型漂移区(3)延伸、经过高压N型区(2)后进入N型漂移区(3)，最终止于浅槽隔离区(10)的边界，在P型体区(4)的表面以及凹槽的底部和侧壁依次注硼、注磷、生长二氧化硅层1和二氧化硅层2，并分别由此形成P型源区(7)、N源型区(6)，隔离氧化层(13)和栅氧化层(8)，在P型源区(7)的表面及N型源区(6)的一部分表面上设有源极金属接触(12)，在栅氧化层(8)的表面设有多晶硅栅极(9)，所述多晶硅栅极(9)的中间部分向下延伸至凹槽底部的栅氧化层(8)的上表面，所述隔离氧化层(13)将源极金属接触(12)和多晶硅栅极(9)隔开。
2.根据权利要求1所述的一种低导通电阻功率半导体器件，其特征在于，多晶硅栅极(9)的向下延伸部分的深度为0.5μm～2.5μm，且多晶硅栅极(9)的向下延伸部分与浅槽隔离区(10)相邻，多晶硅栅极(9)的上方靠近浅槽隔离区(10)的部分向漏端延伸并盖过浅槽隔离区(10)的上表面。
3.根据权利要求1所述的一种低导通电阻功率半导体器件，其特征在于，浅槽隔离区(10)的纵向宽度和多晶硅栅极(9)的向下延伸部分的宽度相等，且浅槽隔离区(10)的沟槽深度超过多晶硅栅极(9)的向下延伸部分的深度0.1μm～0.3μm。
CN201711007210.3A 2017-10-24 2017-10-24 一种低导通电阻功率半导体器件 Pending CN107910357A (zh)

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Application publication date: 20180413