CN111524798B - 一种具有纵向线性变掺杂的深槽横向耐压区的制备方法 - Google Patents

一种具有纵向线性变掺杂的深槽横向耐压区的制备方法 Download PDF

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CN111524798B
CN111524798B CN202010261119.XA CN202010261119A CN111524798B CN 111524798 B CN111524798 B CN 111524798B CN 202010261119 A CN202010261119 A CN 202010261119A CN 111524798 B CN111524798 B CN 111524798B
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程骏骥
武世英
陈为真
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University of Electronic Science and Technology of China
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Abstract

本发明涉及半导体功率器件领域，涉及横向耐压区，具体提供一种具有纵向线性变掺杂的深槽横向耐压区的制备方法，用以克服现有具有纵向线性变掺杂的深槽横向耐压区仅能实现掺杂浓度随纵向深度阶梯式变化的纵向变掺杂、导致其效果不够理想的问题。采用本发明制备得深槽横向耐压区具有接近理想分布的纵向变掺杂柱区，并通过控制离子注入的剂量和侧壁倾角β，能够调节耐压区的电场分布使其接近理想超结结构的电场分布。

Description

一种具有纵向线性变掺杂的深槽横向耐压区的制备方法
技术领域
本发明涉及半导体功率器件领域，涉及横向耐压区，特别是涉及一种深槽横向耐压区的纵向线性变掺杂方法；可应用于横向的半导体功率器件包括LDMOS(LateralDouble-Diffused MOSFET)、LIGBT(Lateral Insulated Gate Bipolar Transistor)等的耐压区工艺设计。
背景技术
深槽横向耐压区中有一个填充了绝缘介质的深槽，利用这个深槽，可以对漂移区进行折叠，从而增加漂移区的有效长度，优化器件击穿电压和比导通电阻之间的折中关系。
为进一步优化深槽横向耐压区，已有一种具有掺杂柱区的深槽横向耐压区结构，它是在深槽的双侧加入与原漂移区杂质类型相反的掺杂柱区；一种典型的结构如图1所示，包括：衬底01、重掺杂N型衬底区02、介质材料03、N型耐压区04、P型耐压区05、P型离子注入区10、阳极P型重掺杂区06、阴极N型重掺杂区07、阳极08及阴极09，如图1所示结构中，加入P型耐压区05与N型耐压区04相互补偿，从而在保持相同击穿电压的前提下，可以提高N型耐压区04掺杂浓度，降低比导通电阻。但深槽本身具有电容性，槽两端的半导体区是电容的两个极板，槽中的介质为电容介质；由于深槽两侧电势差自上而下逐渐变小，深槽电容引起的、位于半导体与深槽界面的电荷也自上而下逐渐浓度变小；同时，由深槽电容引起的、位于半导体与深槽界面的电荷的种类在槽的左右两端是相反的；因此，深槽电容的存在使得如图1所示的深槽横向耐压区的漂移区中往往难以达到电荷平衡状态，限制了器件性能的进一步提高。
针对上述问题，现有方法是通过控制深槽耐压区侧边的掺杂柱区，使它的掺杂剂量随两侧电势差也自上而下地逐渐线性变化，来克服深槽电容的影响，这种方法被称之为纵向线性变掺杂，其理想结构如图4所示；该结构在如图1所示结构基础上改变P型离子注入区10形状为三角形或梯形，通过控制P型离子注入区10宽度自上而下线性变化，实现掺杂剂量自上而下线性逐渐减小，从而使耐压区(04、05和10)净掺杂剂量自上而下实现线性逐渐变化，对深槽电容实现补偿。但是，上述如图4所示的纵向线性变掺杂结构仅仅为理想结构；目前，实现纵向线性变掺杂的工艺方法是对深槽侧壁进行分段的、带一定倾斜角度的离子注入，如图2所示，其结构将P型耐压区05分成n段，自上而下每段的掺杂浓度满足：NP1>NP2>…>NPn-1>NPn，具体制备工艺流程如图3所示；该结构实现的效果是使耐压区(04和05)净掺杂剂量自上而下阶梯式逐渐减小；基于如图2所示的单侧纵向线性变掺杂结构，可以设计得如图4所示的双侧纵向线性变掺杂结构，其制备工艺流程如图5所示；但是，这种方法只能实现掺杂浓度随纵向深度阶梯式变化的纵向变掺杂，而非严格的线性递减，导致其效果不如理想线性变掺杂。
发明内容
本发明的目的在于针对上述技术问题，提供一种具有纵向线性变掺杂的深槽横向耐压区的制备方法，采用该方法制备得深槽横向耐压区具有接近理想分布的纵向变掺杂柱区。
为实现上述目的，本发明采用的技术方案如下：
一种单侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，包括以下步骤：
步骤1：在预清洗后衬底01上进行外延形成第一耐压区04；
步骤2：对第一耐压区04进行刻蚀，于第一耐压区中形成第一矩形深槽，并再次进行外延，于第一矩形深槽内形成第二耐压区05；
步骤3：对第二耐压区05进行斜槽加工，于第二耐压区中形成呈“倒梯形”的第一斜槽，且第一斜槽的开口宽度为w1、斜槽侧壁倾角为β、深度为h；
步骤4：对第一斜槽侧壁进行带倾斜角度α的离子注入，于第一斜槽两侧侧壁分别形成第一种导电类型离子注入区10，该离子注入区10的宽度为w2、深度为h，并满足：tanβ＝w2/h；
步骤5：沿第一斜槽开口的左侧或右侧边沿，对第二耐压区05和第一种导电类型离子注入区10进行刻蚀，形成宽度为w1+w2、深度为h的第二矩形深槽，并于第二矩形深槽的左侧或右侧形成短直角边为w2、长直角边为h的“倒直角三角形”第一种导电类型离子注入区，该“倒直角三角形”离子注入区为自上而下宽度线性递减，实现离子注入区10对应侧耐压区04和05以及离子注入区10的净掺杂剂量自上而下线性递减，即实现纵向线性变掺杂；
步骤6：对第二矩形深槽进行介质03填充，并于填充后进行平坦化；
步骤7：采用离子注入和淀积工艺完成器件有源区和电极的制作。
一种双侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，包括以下步骤：
步骤1～步骤6与上述步骤相同；
步骤7：对介质03和第二耐压区05再次进行斜槽加工，形成呈“倒梯形”的第二斜槽，且第二斜槽的开口宽度为w3、斜槽侧壁倾角为β、深度为h；
步骤8：对第二斜槽侧壁进行带倾斜角度α的离子注入，于第二斜槽的第二耐压区05一侧形成第二种导电类型离子注入区11，该离子注入区11的宽度为w2、深度为h，并满足：tanβ＝w2/h；
步骤9：沿第二斜槽开口的第二耐压区05侧边沿，对介质03和第二种导电类型离子注入区11进行刻蚀，形成宽度为w3+w2、深度为h的第三矩形深槽，将第二种导电类型离子注入区11刻蚀为短直角边为w2、长直角边为h的“倒直角三角形”的第二种导电类型离子注入区；同理实现纵向线性变掺杂；
步骤10：对第三矩形深槽进行介质03填充，并于填充后进行平坦化；
步骤11：采用离子注入和淀积工艺完成器件有源区和电极的制作。
需要说明的是，上述第一种导电类型与第二种导电类型用于区分不同的离子注入类型，通常在具有深槽横向耐压区的器件的耐压状态下，靠近高电压侧的离子注入类型为N型，靠近低电压侧的离子注入类型为P型。
本发明的有益效果在于：
本发明提供一种具有纵向线性变掺杂的深槽横向耐压区的制备方法，采用本发明制备得深槽横向耐压区具有接近理想分布的纵向变掺杂柱区，并通过控制离子注入的剂量和侧壁倾角β，能够调节耐压区的电场分布使其接近理想超结结构的电场分布。
附图说明
图1为现有典型的深槽横向耐压区的结构示意图。
图2为现有单侧具有阶梯式纵向渐变掺杂的深槽横向耐压区的结构示意图。
图3为如图2所示结构的制备工艺流程图。
图4为现有双侧具有阶梯式纵向渐变掺杂的深槽横向耐压区的结构示意图。
图5为如图4所示结构的制备工艺流程图。
图6为单侧具有理想纵向线性渐变掺杂的深槽横向耐压区的结构示意图。
图7为本发明提出如图6所示结构的制备工艺流程图。
图8为双侧具有理想纵向线性渐变掺杂的深槽横向耐压区的结构示意图。
图9为本发明提出如图8所示结构的制备工艺流程图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
实施例1
本实施例提供一种单侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，所述单侧具有纵向线性变掺杂的深槽横向耐压区的结构如图6所示，具体工艺流程如图7所示，包括以下步骤：
步骤1：进行加工前准备，清洗半导体；
步骤2：在衬底01上进行外延形成耐压区04，如图7(a)所示；
步骤3：对耐压区04进行刻蚀，于耐压区中形成第一矩形深槽，如图7(b)所示；
步骤4：对深槽进行外延，于深槽内形成耐压区05，如图7(c)所示；
步骤5：对耐压区05进行斜槽加工，形成呈下窄上宽的“倒梯形”的第一斜槽，第一斜槽的开口宽度为w1，斜槽侧壁与垂直方向夹角为β、为斜槽侧壁倾角，斜槽的深度为h，实现效果如图7(d)所示；
步骤6：对步骤5中加工完成的斜槽侧壁进行带倾斜角度α的离子注入，形成如图7(e)所示的第一离子注入区10，离子注入的导电类型为第一种导电类型，离子注入区10的宽度为w2、深度为h；斜槽侧壁倾角β与离子注入区的高度h和宽度w2之间需要满足(工艺精度内近似满足)：tanβ＝w2/h；实现效果如图7(e)所示；
步骤7：沿第一斜槽开口的左侧边沿，对耐压区05和离子注入区10进行刻蚀，形成一个宽度为w1+w2、深度为h的第二矩形深槽，如图7(f)所示，位于右侧的离子注入区被全部去除，于第二矩形深槽的左侧形成呈短直角边为w2、长直角边为h的“倒直角三角形”的离子注入区；由图7(f)可见，该“倒直角三角形”离子注入区为自上而下宽度线性递减，实现离子注入区10对应侧耐压区04和05以及离子注入区10的净掺杂剂量自上而下线性递减；同理，当沿斜槽开口的右侧边沿刻蚀第二矩形深槽，则可于第二矩形深槽的右侧形成“倒直角三角形”离子注入区；
步骤8：对步骤7中刻蚀形成的深槽进行介质03填充，介质类型不限于二氧化硅，实现效果如图7(g)所示；
步骤9：完成介质填充后进行平坦化操作，实现效果如图7(h)所示；
步骤10：采用离子注入和淀积工艺完成器件有源区和电极的制作；即制备得单侧具有理想纵向线性渐变掺杂的深槽横向耐压区。
实施例2
本实施例提供一种双侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，所述双侧具有纵向线性变掺杂的深槽横向耐压区的结构如图8所示，具体工艺流程如图9所示，包括以下步骤：
步骤1～步骤9与实施例1完全相同；
步骤10：对平坦后介质03和耐压区05再次进行斜槽加工，形成呈下窄上宽的“倒梯形”的第二斜槽，第二斜槽的开口宽度为w3，形成如图9(i)所示斜槽，斜槽倾角为β、深度为h；
步骤11：对步骤10中加工完成的第二斜槽侧壁进行带倾斜角度α的离子注入，于第二斜槽右侧形成如图9(j)所示的第二离子注入区11，第二离子注入区11的导电类型为第二种导电类型，离子注入区11的宽度为w2、深度为h，斜槽侧壁倾角β与离子注入区的高度h和宽度w之间需要满足(工艺精度内近似满足)：tanβ＝w2/h；实现效果如图9(j)所示；
步骤12：沿第二斜槽开口的右侧边沿，对介质03和第二离子注入区11进行刻蚀，形成一个宽度为w3+w2、深度为h的第三矩形深槽，如图9(k)所示，于第三矩形深槽的右侧形成呈短直角边为w2、长直角边为h的“倒直角三角形”的第二离子注入区；由图9(k)可见，该“倒直角三角形”离子注入区为自上而下宽度线性递减，实现第二离子注入区11对应侧耐压区04和05以及离子注入区11的净掺杂剂量自上而下线性递减；
步骤13：对步骤12中刻蚀形成的深槽再次进行介质03填充，介质类型与步骤8中所述介质相同，实现效果如图9(l)所示；
步骤14：完成步骤13介质填充后进行平坦化操作，实现效果如图9(m)所示；
步骤15：采用离子注入和淀积工艺完成器件有源区和电极的制作，即制备得单侧具有理想纵向线性渐变掺杂的深槽横向耐压区，如图9(n)所示。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。

Claims (2)

1.一种单侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，包括以下步骤：
步骤1：在预清洗后衬底(01)上进行外延形成第一耐压区(04)；
步骤2：对第一耐压区进行刻蚀，于第一耐压区中形成第一矩形深槽，并再次进行外延，于第一矩形深槽内形成第二耐压区(05)；
步骤3：对第二耐压区进行斜槽加工，于第二耐压区中形成呈“倒梯形”的第一斜槽，且第一斜槽的开口宽度为w1、斜槽侧壁倾角为β、深度为h；
步骤4：对第一斜槽侧壁进行带倾斜角度α的离子注入，于第一斜槽两侧侧壁分别形成第一种导电类型离子注入区(10)，该离子注入区(10)的宽度为w2、深度为h，并满足：tanβ＝w2/h；
步骤5：沿第一斜槽开口的左侧或右侧边沿，对第二耐压区和第一种导电类型离子注入区进行刻蚀，形成宽度为w1+w2、深度为h的第二矩形深槽，并于第二矩形深槽的左侧或右侧形成短直角边为w2、长直角边为h的“倒直角三角形”第一种导电类型离子注入区，实现纵向线性变掺杂；
步骤6：对第二矩形深槽进行介质(03)填充，并于填充后进行平坦化；
步骤7：采用离子注入和淀积工艺完成器件有源区和电极的制作。
2.一种双侧具有纵向线性变掺杂的深槽横向耐压区的制备方法，包括以下步骤：
步骤1：在预清洗后衬底(01)上进行外延形成第一耐压区(04)；
步骤2：对第一耐压区进行刻蚀，于第一耐压区中形成第一矩形深槽，并再次进行外延，于第一矩形深槽内形成第二耐压区(05)；
步骤3：对第二耐压区进行斜槽加工，于第二耐压区中形成呈“倒梯形”的第一斜槽，且第一斜槽的开口宽度为w1、斜槽侧壁倾角为β、深度为h；
步骤4：对第一斜槽侧壁进行带倾斜角度α的离子注入，于第一斜槽两侧侧壁分别形成第一种导电类型离子注入区(10)，该离子注入区(10)的宽度为w2、深度为h，并满足：tanβ＝w2/h；
步骤5：沿第一斜槽开口的左侧或右侧边沿，对第二耐压区和第一种导电类型离子注入区进行刻蚀，形成宽度为w1+w2、深度为h的第二矩形深槽，并于第二矩形深槽的左侧或右侧形成短直角边为w2、长直角边为h的“倒直角三角形”第一种导电类型离子注入区，实现纵向线性变掺杂；
步骤6：对第二矩形深槽进行介质(03)填充，并于填充后进行平坦化；
步骤7：对介质和第二耐压区再次进行斜槽加工，形成呈“倒梯形”的第二斜槽，且第二斜槽的开口宽度为w3、斜槽侧壁倾角为β、深度为h；
步骤8：对第二斜槽侧壁再次进行带倾斜角度α的离子注入，于第二斜槽的第二耐压区一侧形成第二种导电类型离子注入区(11)，该离子注入区(11)的宽度为w2、深度为h，并满足：tanβ＝w2/h；
步骤9：沿第二斜槽开口的第二耐压区侧边沿，对介质和第二种导电类型离子注入区进行刻蚀，形成宽度为w3+w2、深度为h的第三矩形深槽，将第二种导电类型离子注入区刻蚀为短直角边为w2、长直角边为h的“倒直角三角形”的第二种导电类型离子注入区，实现纵向线性变掺杂；
步骤10：对第三矩形深槽再次进行介质填充，并于填充后进行平坦化；
步骤11：采用离子注入和淀积工艺完成器件有源区和电极的制作。
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Publication number Priority date Publication date Assignee Title
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969315A (zh) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 一种逆导型集成门极换流晶闸管
CN103545350A (zh) * 2013-10-30 2014-01-29 电子科技大学 一种横向高压器件漂移区的制造方法
CN105957896A (zh) * 2016-06-24 2016-09-21 上海华虹宏力半导体制造有限公司 超结功率器件及其制造方法
CN107068736A (zh) * 2017-03-30 2017-08-18 电子科技大学 一种soi横向高压器件
CN107275388A (zh) * 2017-06-26 2017-10-20 电子科技大学 一种横向高压器件
CN108389892A (zh) * 2018-02-02 2018-08-10 电子科技大学 一种具有纵向变掺杂剂量的深槽型横向耐压区
CN108598150A (zh) * 2018-04-25 2018-09-28 西安理工大学 一种横向变掺杂-结终端延伸复合终端结构及其制造方法
CN109449083A (zh) * 2018-10-24 2019-03-08 武汉新芯集成电路制造有限公司 缓变结、高压器件和半导体器件及其制造方法
CN110021655A (zh) * 2019-04-19 2019-07-16 西安电子科技大学 一种具有阶梯n型重掺杂埋层的半超结横向双扩散金属氧化物半导体场效应管

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19843959B4 (de) * 1998-09-24 2004-02-12 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem sperrenden pn-Übergang
US6621121B2 (en) * 1998-10-26 2003-09-16 Silicon Semiconductor Corporation Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes
US7015104B1 (en) * 2003-05-29 2006-03-21 Third Dimension Semiconductor, Inc. Technique for forming the deep doped columns in superjunction
CN106024866B (zh) * 2016-07-25 2019-03-29 电子科技大学 一种功率半导体器件的沟槽型终端结构

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969315A (zh) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 一种逆导型集成门极换流晶闸管
CN103545350A (zh) * 2013-10-30 2014-01-29 电子科技大学 一种横向高压器件漂移区的制造方法
CN105957896A (zh) * 2016-06-24 2016-09-21 上海华虹宏力半导体制造有限公司 超结功率器件及其制造方法
CN107068736A (zh) * 2017-03-30 2017-08-18 电子科技大学 一种soi横向高压器件
CN107275388A (zh) * 2017-06-26 2017-10-20 电子科技大学 一种横向高压器件
CN108389892A (zh) * 2018-02-02 2018-08-10 电子科技大学 一种具有纵向变掺杂剂量的深槽型横向耐压区
CN108598150A (zh) * 2018-04-25 2018-09-28 西安理工大学 一种横向变掺杂-结终端延伸复合终端结构及其制造方法
CN109449083A (zh) * 2018-10-24 2019-03-08 武汉新芯集成电路制造有限公司 缓变结、高压器件和半导体器件及其制造方法
CN110021655A (zh) * 2019-04-19 2019-07-16 西安电子科技大学 一种具有阶梯n型重掺杂埋层的半超结横向双扩散金属氧化物半导体场效应管

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
《一种基于扩展栅的改进的双通道OPTVLD p-LDMOS》;李欢 程骏骥 陈星弼;《微电子学》;20190220;第49卷(第01期);正文全文 *
《薄外延阶梯掺杂漂移区RESURF耐压模型》;李琦 李肇基 张波;《固体电子学研究与进展》;20060325;第26卷(第1期);正文全文 *
硅材料功率半导体器件结终端技术的新发展;张彦飞等;《电子器件》;20090620(第03期);正文全文 *

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