JP6293436B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP6293436B2
JP6293436B2 JP2013166974A JP2013166974A JP6293436B2 JP 6293436 B2 JP6293436 B2 JP 6293436B2 JP 2013166974 A JP2013166974 A JP 2013166974A JP 2013166974 A JP2013166974 A JP 2013166974A JP 6293436 B2 JP6293436 B2 JP 6293436B2
Authority
JP
Japan
Prior art keywords
core
pair
wiring
support
support plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013166974A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015035560A5 (enExample
JP2015035560A (ja
Inventor
孝之 極並
孝之 極並
淳史 佐藤
淳史 佐藤
深瀬　克哉
克哉 深瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013166974A priority Critical patent/JP6293436B2/ja
Priority to US14/446,794 priority patent/US9420696B2/en
Publication of JP2015035560A publication Critical patent/JP2015035560A/ja
Publication of JP2015035560A5 publication Critical patent/JP2015035560A5/ja
Application granted granted Critical
Publication of JP6293436B2 publication Critical patent/JP6293436B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2013166974A 2013-08-09 2013-08-09 配線基板の製造方法 Active JP6293436B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013166974A JP6293436B2 (ja) 2013-08-09 2013-08-09 配線基板の製造方法
US14/446,794 US9420696B2 (en) 2013-08-09 2014-07-30 Method of manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013166974A JP6293436B2 (ja) 2013-08-09 2013-08-09 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2015035560A JP2015035560A (ja) 2015-02-19
JP2015035560A5 JP2015035560A5 (enExample) 2016-07-21
JP6293436B2 true JP6293436B2 (ja) 2018-03-14

Family

ID=52447575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013166974A Active JP6293436B2 (ja) 2013-08-09 2013-08-09 配線基板の製造方法

Country Status (2)

Country Link
US (1) US9420696B2 (enExample)
JP (1) JP6293436B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102268388B1 (ko) * 2014-08-11 2021-06-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP2016076658A (ja) * 2014-10-08 2016-05-12 イビデン株式会社 電子部品内蔵配線板及びその製造方法
CN109637981B (zh) * 2018-11-20 2021-10-12 奥特斯科技(重庆)有限公司 制造部件承载件的方法、部件承载件以及半制成产品
US10624213B1 (en) * 2018-12-20 2020-04-14 Intel Corporation Asymmetric electronic substrate and method of manufacture
CN114582729A (zh) * 2022-01-20 2022-06-03 珠海越亚半导体股份有限公司 封装基板制作方法及封装基板
EP4576950A1 (en) * 2023-12-19 2025-06-25 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with stacks connected by intermediate layer, and manufacturing method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5064583A (en) * 1989-08-01 1991-11-12 Zycon Corporation Method for applying mold release coating to separator plates for molding printed circuit boards
US6391220B1 (en) * 1999-08-18 2002-05-21 Fujitsu Limited, Inc. Methods for fabricating flexible circuit structures
JP4648230B2 (ja) 2006-03-24 2011-03-09 日本特殊陶業株式会社 配線基板の製造方法
KR100796523B1 (ko) * 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
KR100999531B1 (ko) * 2008-10-20 2010-12-08 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR101058621B1 (ko) * 2009-07-23 2011-08-22 삼성전기주식회사 반도체 패키지 및 이의 제조 방법
JP5001395B2 (ja) 2010-03-31 2012-08-15 イビデン株式会社 配線板及び配線板の製造方法
WO2011145490A1 (ja) * 2010-05-17 2011-11-24 太陽誘電株式会社 基板内蔵用電子部品および部品内蔵型基板
JP2013030603A (ja) * 2011-07-28 2013-02-07 Hitachi Chem Co Ltd 配線基板の製造方法
JP2013105992A (ja) * 2011-11-16 2013-05-30 Casio Comput Co Ltd 半導体装置内蔵基板モジュール及びその製造方法

Also Published As

Publication number Publication date
US20150041053A1 (en) 2015-02-12
JP2015035560A (ja) 2015-02-19
US9420696B2 (en) 2016-08-16

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