JP6209826B2 - リードフレーム、樹脂付きリードフレーム、リードフレームの多面付け体、樹脂付きリードフレームの多面付け体、光半導体装置、光半導体装置の多面付け体 - Google Patents

リードフレーム、樹脂付きリードフレーム、リードフレームの多面付け体、樹脂付きリードフレームの多面付け体、光半導体装置、光半導体装置の多面付け体 Download PDF

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Publication number
JP6209826B2
JP6209826B2 JP2013033390A JP2013033390A JP6209826B2 JP 6209826 B2 JP6209826 B2 JP 6209826B2 JP 2013033390 A JP2013033390 A JP 2013033390A JP 2013033390 A JP2013033390 A JP 2013033390A JP 6209826 B2 JP6209826 B2 JP 6209826B2
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Prior art keywords
lead frame
terminal
resin
outer peripheral
optical semiconductor
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Japanese (ja)
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JP2014165262A (ja
JP2014165262A5 (enrdf_load_stackoverflow
Inventor
中村　誠
誠 中村
和幸 宮野
和幸 宮野
雅樹 矢崎
雅樹 矢崎
和範 小田
小田　　和範
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Publication of JP2014165262A5 publication Critical patent/JP2014165262A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
JP2013033390A 2013-02-22 2013-02-22 リードフレーム、樹脂付きリードフレーム、リードフレームの多面付け体、樹脂付きリードフレームの多面付け体、光半導体装置、光半導体装置の多面付け体 Active JP6209826B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013033390A JP6209826B2 (ja) 2013-02-22 2013-02-22 リードフレーム、樹脂付きリードフレーム、リードフレームの多面付け体、樹脂付きリードフレームの多面付け体、光半導体装置、光半導体装置の多面付け体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013033390A JP6209826B2 (ja) 2013-02-22 2013-02-22 リードフレーム、樹脂付きリードフレーム、リードフレームの多面付け体、樹脂付きリードフレームの多面付け体、光半導体装置、光半導体装置の多面付け体

Related Child Applications (1)

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JP2016079475A Division JP6115671B2 (ja) 2016-04-12 2016-04-12 リードフレーム、樹脂付きリードフレーム、光半導体装置

Publications (3)

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JP2014165262A JP2014165262A (ja) 2014-09-08
JP2014165262A5 JP2014165262A5 (enrdf_load_stackoverflow) 2016-06-02
JP6209826B2 true JP6209826B2 (ja) 2017-10-11

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6291713B2 (ja) 2013-03-14 2018-03-14 日亜化学工業株式会社 発光素子実装用基体及びそれを備える発光装置、並びにリードフレーム
JP2014199873A (ja) * 2013-03-29 2014-10-23 株式会社カネカ 発光素子実装用リードフレーム、発光素子実装用樹脂成型体及び表面実装型発光装置
JP6362108B2 (ja) * 2014-09-08 2018-07-25 大口マテリアル株式会社 半導体素子搭載用リードフレーム及びその製造方法
CN107004648B (zh) * 2014-11-20 2019-04-23 日本精工株式会社 电子部件搭载用散热基板
EP3223307A4 (en) * 2014-11-20 2018-08-29 NSK Ltd. Heat dissipation substrate for mounting electric component
JP6213582B2 (ja) 2016-01-22 2017-10-18 日亜化学工業株式会社 発光装置
JP6544410B2 (ja) * 2017-11-08 2019-07-17 日亜化学工業株式会社 発光素子実装用基体及びそれを備える発光装置
JP6986539B2 (ja) * 2019-11-25 2021-12-22 Ｔｏｗａ株式会社 樹脂成形済リードフレームの製造方法、樹脂成形品の製造方法、及びリードフレーム
JP7495610B2 (ja) 2020-07-06 2024-06-05 日亜化学工業株式会社 発光装置及び発光装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2862106B2 (ja) * 1991-11-05 1999-02-24 日立電線株式会社 リードフレームの製造方法
JPH0832001A (ja) * 1994-07-11 1996-02-02 Dainippon Printing Co Ltd リードフレームの製造方法及びリードフレーム
JPH08316392A (ja) * 1995-05-16 1996-11-29 Dainippon Printing Co Ltd リードフレームの製造方法とリードフレーム
JP4574868B2 (ja) * 2001-01-12 2010-11-04 ローム株式会社 半導体装置
JP2004031775A (ja) * 2002-06-27 2004-01-29 Mitsui High Tec Inc リードフレーム及びその製造方法
JP2009302209A (ja) * 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法
JP5453642B2 (ja) * 2009-02-20 2014-03-26 Ｓｈマテリアル株式会社 リードフレームの製造方法
JP5710128B2 (ja) * 2010-01-19 2015-04-30 大日本印刷株式会社 樹脂付リードフレームの製造方法
JP5587625B2 (ja) * 2010-02-01 2014-09-10 アピックヤマダ株式会社 リードフレーム及びｌｅｄパッケージ用基板
JP2012104542A (ja) * 2010-11-08 2012-05-31 Toppan Printing Co Ltd Ｌｅｄ発光素子用リードフレーム及びそれを用いたｌｅｄパッケージ、およびその製造方法
JP2012142426A (ja) * 2010-12-28 2012-07-26 Toshiba Corp Ｌｅｄパッケージ及びその製造方法
JP2012204754A (ja) * 2011-03-28 2012-10-22 Toppan Printing Co Ltd Ｌｅｄ発光素子用リードフレーム、およびその製造方法、並びにそれを用いたｌｅｄパッケージ

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