JP6113200B2 - 不揮発性メモリアレイに使用するための自己整合スタックゲート構造 - Google Patents
不揮発性メモリアレイに使用するための自己整合スタックゲート構造 Download PDFInfo
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- JP6113200B2 JP6113200B2 JP2014560917A JP2014560917A JP6113200B2 JP 6113200 B2 JP6113200 B2 JP 6113200B2 JP 2014560917 A JP2014560917 A JP 2014560917A JP 2014560917 A JP2014560917 A JP 2014560917A JP 6113200 B2 JP6113200 B2 JP 6113200B2
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- 238000003491 array Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 49
- 239000011810 insulating material Substances 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 230000014759 maintenance of location Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims 1
- 239000002131 composite material Substances 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Description
Claims (7)
- 不揮発性メモリアレイに使用するための複数の連結されたスタックゲート構造を形成する方法であって、該方法が、
スタックゲート構造を、
半導体基板上に第1の絶縁層を形成することと、
前記第1の絶縁層上に電荷保持層を形成することと、
前記電荷保持層上に第2の絶縁層を形成することと、
前記第2の絶縁層上に第1のポリシリコン層であって、第1の上面を有する、第1のポリシリコン層を形成することと、
前記第1のポリシリコン層の前記第1の上面上の第3の絶縁材料で第3の絶縁層を形成することと、
前記第3の絶縁層上に第1の犠牲層であって、第2の上面を有する、第1の犠牲層を形成することと、によって形成することと、
複数の離間配置された実質的に平行な領域内の前記スタックゲート構造を、前記第2の上面から前記半導体基板の中に下方にエッチングすることであって、各領域が第1の方向に延在する、前記スタックゲート構造をエッチングすることと、
前記第3の絶縁材料で前記エッチングされた離間配置された領域を充填し、それにより前記半導体基板内の隣接する活性領域間、及び隣接するスタックゲート構造間に分離領域を形成することと、
前記エッチングされた離間配置された領域上の前記第3の絶縁材料の前記上面が前記第2の上面と実質的に同一平面上になるように、前記第3の絶縁材料を平坦化することと、 前記第1の犠牲層を除去することと、
前記第1のポリシリコン層の前記第1の上面が、いかなる第3の絶縁材料も実質的に除去されるように、前記第3の絶縁材料をエッチングすることと、
前記第1のポリシリコン層上、かつ前記エッチングされた離間配置された領域上の前記第3の絶縁材料上に第2のポリシリコン層を形成し、前記複数の離間配置されたスタックゲート構造を連結することと、
前記第2のポリシリコン層上に第4の絶縁材料を形成することと、
前記第1の方向に実質的に垂直な第2の方向で前記結果として得られた構造をエッチングすることと、を含み、
前記第3の絶縁材料をエッチングする前記工程が、前記第1のポリシリコン層の前記上面と実質的に同一平面上になるように、スタックゲート構造間の前記第3の絶縁材料をエッチングするように構成された、方法。 - 前記第1の絶縁層の材料及び前記第3の絶縁材料が同じである、請求項1に記載の方法。
- 前記第3の絶縁材料が、二酸化ケイ素である、請求項2に記載の方法。
- 前記第1の犠牲層が、窒化ケイ素である、請求項1に記載の方法。
- 前記電荷保持層が、ポリシリコンである、請求項1に記載の方法。
- 前記電荷保持層が、電荷トラッピング層である、請求項1に記載の方法。
- 前記第3の絶縁材料を平坦化する前記工程が、CMPプロセスである、請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/414,400 | 2012-03-07 | ||
US13/414,400 US9330922B2 (en) | 2012-03-07 | 2012-03-07 | Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure |
PCT/US2013/024288 WO2013133919A1 (en) | 2012-03-07 | 2013-02-01 | Self-aligned stack gate structure for use in a non-volatile memory array |
Publications (2)
Publication Number | Publication Date |
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JP2015513221A JP2015513221A (ja) | 2015-04-30 |
JP6113200B2 true JP6113200B2 (ja) | 2017-04-12 |
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JP2014560917A Active JP6113200B2 (ja) | 2012-03-07 | 2013-02-01 | 不揮発性メモリアレイに使用するための自己整合スタックゲート構造 |
Country Status (7)
Country | Link |
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US (2) | US9330922B2 (ja) |
EP (1) | EP2823506B1 (ja) |
JP (1) | JP6113200B2 (ja) |
KR (1) | KR101541677B1 (ja) |
CN (1) | CN104246985B (ja) |
TW (1) | TWI559505B (ja) |
WO (1) | WO2013133919A1 (ja) |
Families Citing this family (6)
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US9136360B1 (en) | 2014-06-06 | 2015-09-15 | Freescale Semiconductor, Inc. | Methods and structures for charge storage isolation in split-gate memory arrays |
TWI588992B (zh) * | 2015-01-13 | 2017-06-21 | Xinnova Tech Ltd | Non-volatile memory components and methods of making the same |
TWI606551B (zh) * | 2015-02-16 | 2017-11-21 | Xinnova Tech Ltd | Non-volatile memory device method |
CN107305892B (zh) | 2016-04-20 | 2020-10-02 | 硅存储技术公司 | 使用两个多晶硅沉积步骤来形成三栅极非易失性闪存单元对的方法 |
US11164881B2 (en) * | 2018-09-11 | 2021-11-02 | Globalfoundries Singapore Pte. Ltd. | Transistor device, memory arrays, and methods of forming the same |
CN110931500B (zh) * | 2019-10-25 | 2023-09-05 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
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US6689658B2 (en) | 2002-01-28 | 2004-02-10 | Silicon Based Technology Corp. | Methods of fabricating a stack-gate flash memory array |
TW535242B (en) | 2002-05-30 | 2003-06-01 | Silicon Based Tech Corp | Methods of fabricating a stack-gate non-volatile memory device and its contactless memory arrays |
KR100520846B1 (ko) * | 2004-05-11 | 2005-10-12 | 삼성전자주식회사 | 플로팅 게이트 형성 방법 및 이를 이용한 불휘발성 메모리장치의 제조방법 |
TWI233691B (en) | 2004-05-12 | 2005-06-01 | Powerchip Semiconductor Corp | Nonvolatile memory, nonvolatile memory array and manufacturing method thereof |
JP4620437B2 (ja) | 2004-12-02 | 2011-01-26 | 三菱電機株式会社 | 半導体装置 |
TWI277179B (en) * | 2005-09-08 | 2007-03-21 | Ememory Technology Inc | Non-volatile memory device |
KR100833444B1 (ko) * | 2006-03-28 | 2008-05-29 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조 방법 |
KR100823704B1 (ko) | 2006-10-20 | 2008-04-21 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그 제조 방법 |
JP2008192991A (ja) | 2007-02-07 | 2008-08-21 | Toshiba Corp | 半導体装置 |
JP2008211022A (ja) * | 2007-02-27 | 2008-09-11 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US7714377B2 (en) | 2007-04-19 | 2010-05-11 | Qimonda Ag | Integrated circuits and methods of manufacturing thereof |
US20090039410A1 (en) | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
JP4594973B2 (ja) * | 2007-09-26 | 2010-12-08 | 株式会社東芝 | 不揮発性半導体記憶装置 |
FR2917533A1 (fr) | 2007-11-14 | 2008-12-19 | Commissariat Energie Atomique | Substrat a couche de stockage de charges electriques enterree et procede de realisation |
US8008707B2 (en) | 2007-12-14 | 2011-08-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device provided with charge storage layer in memory cell |
JP2009283827A (ja) * | 2008-05-26 | 2009-12-03 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
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2012
- 2012-03-07 US US13/414,400 patent/US9330922B2/en active Active
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- 2013-02-01 JP JP2014560917A patent/JP6113200B2/ja active Active
- 2013-02-01 CN CN201380022225.0A patent/CN104246985B/zh active Active
- 2013-02-01 KR KR1020147028236A patent/KR101541677B1/ko active IP Right Grant
- 2013-02-01 WO PCT/US2013/024288 patent/WO2013133919A1/en active Application Filing
- 2013-02-01 EP EP13757434.9A patent/EP2823506B1/en active Active
- 2013-02-08 TW TW102105246A patent/TWI559505B/zh active
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Also Published As
Publication number | Publication date |
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WO2013133919A1 (en) | 2013-09-12 |
CN104246985A (zh) | 2014-12-24 |
US9570581B2 (en) | 2017-02-14 |
TW201351618A (zh) | 2013-12-16 |
EP2823506A4 (en) | 2015-11-04 |
KR20140144206A (ko) | 2014-12-18 |
EP2823506A1 (en) | 2015-01-14 |
US20160225878A1 (en) | 2016-08-04 |
JP2015513221A (ja) | 2015-04-30 |
US20130234223A1 (en) | 2013-09-12 |
KR101541677B1 (ko) | 2015-08-03 |
US9330922B2 (en) | 2016-05-03 |
TWI559505B (zh) | 2016-11-21 |
CN104246985B (zh) | 2017-05-24 |
EP2823506B1 (en) | 2018-01-10 |
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