JP6110769B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6110769B2 JP6110769B2 JP2013198300A JP2013198300A JP6110769B2 JP 6110769 B2 JP6110769 B2 JP 6110769B2 JP 2013198300 A JP2013198300 A JP 2013198300A JP 2013198300 A JP2013198300 A JP 2013198300A JP 6110769 B2 JP6110769 B2 JP 6110769B2
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- semiconductor chip
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- semiconductor device
- die pad
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- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013198300A JP6110769B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
| US14/487,762 US9257400B2 (en) | 2013-09-25 | 2014-09-16 | Semiconductor device |
| CN201410498376.XA CN104465592B (zh) | 2013-09-25 | 2014-09-25 | 半导体器件 |
| HK15108392.0A HK1207743B (zh) | 2013-09-25 | 2015-08-28 | 半导体器件 |
| US14/982,155 US20160111357A1 (en) | 2013-09-25 | 2015-12-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013198300A JP6110769B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
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| JP2015065296A JP2015065296A (ja) | 2015-04-09 |
| JP2015065296A5 JP2015065296A5 (enExample) | 2016-03-24 |
| JP6110769B2 true JP6110769B2 (ja) | 2017-04-05 |
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| JP2013198300A Expired - Fee Related JP6110769B2 (ja) | 2013-09-25 | 2013-09-25 | 半導体装置 |
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| Country | Link |
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| US (2) | US9257400B2 (enExample) |
| JP (1) | JP6110769B2 (enExample) |
| CN (1) | CN104465592B (enExample) |
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| JP2017037911A (ja) * | 2015-08-07 | 2017-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2017112327A (ja) * | 2015-12-18 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| CN111383542A (zh) | 2018-12-29 | 2020-07-07 | 广东聚华印刷显示技术有限公司 | 像素结构和显示面板 |
| US11393774B2 (en) * | 2019-08-21 | 2022-07-19 | Stmicroelectronics, Inc. | Semiconductor device having cavities at an interface of an encapsulant and a die pad or leads |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08130284A (ja) * | 1994-10-31 | 1996-05-21 | Fuji Electric Co Ltd | 半導体装置 |
| JP2000156464A (ja) * | 1998-11-20 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法 |
| US6476474B1 (en) * | 2000-10-10 | 2002-11-05 | Siliconware Precision Industries Co., Ltd. | Dual-die package structure and method for fabricating the same |
| JP3670625B2 (ja) * | 2001-06-13 | 2005-07-13 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
| JP2004296613A (ja) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | 半導体装置 |
| JP2005150647A (ja) * | 2003-11-20 | 2005-06-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| JP4759948B2 (ja) * | 2004-07-28 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2007165459A (ja) * | 2005-12-12 | 2007-06-28 | Mitsubishi Electric Corp | マルチチップモジュール |
| JP2008091627A (ja) * | 2006-10-02 | 2008-04-17 | Toshiba Corp | 半導体集積チップ及び半導体装置 |
| JP5646830B2 (ja) | 2009-09-02 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及びリードフレーム |
| JP5667381B2 (ja) * | 2010-06-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
| KR20140011687A (ko) * | 2012-07-18 | 2014-01-29 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
| US9379048B2 (en) * | 2013-02-28 | 2016-06-28 | Semiconductor Components Industries, Llc | Dual-flag stacked die package |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20150084209A1 (en) | 2015-03-26 |
| CN104465592A (zh) | 2015-03-25 |
| US20160111357A1 (en) | 2016-04-21 |
| HK1207743A1 (en) | 2016-02-05 |
| JP2015065296A (ja) | 2015-04-09 |
| CN104465592B (zh) | 2018-10-19 |
| US9257400B2 (en) | 2016-02-09 |
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