CN104465592A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN104465592A
CN104465592A CN201410498376.XA CN201410498376A CN104465592A CN 104465592 A CN104465592 A CN 104465592A CN 201410498376 A CN201410498376 A CN 201410498376A CN 104465592 A CN104465592 A CN 104465592A
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China
Prior art keywords
semiconductor chip
interarea
lead terminal
chip
closing line
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Granted
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CN201410498376.XA
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CN104465592B (zh
Inventor
内田慎一
西川健次
菅野正人
米泽美香
归山隼一
清原俊范
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及一种半导体器件。半导体器件具有芯片安装部，第一半导体芯片以及第二半导体芯片。第一半导体芯片在其主面面对芯片安装部的方向上安装在芯片安装部上。第二半导体芯片的一部分在其第三主面面对第一半导体芯片的方向上安装在芯片安装部上。元件安装部具有凹陷部。第二半导体芯片的一部分与凹口部重叠。在第二半导体芯片的第三主面的与凹口部重叠的区域中，设置第二电极焊盘。

Description

半导体器件
相关申请交叉引用
将2013年9月25日提交的日本专利申请No.2013-198300的公开内容，包括说明书，附图和摘要，整体并入本文作为参考。
技术领域
本发明涉及一种半导体器件，并且本发明例如是一种适用于其中层叠两个半导体芯片的半导体器件的技术。
背景技术
在半导体器件中，有一种器件，其中第一半导体芯片和第二半导体芯片的两个半导体芯片以其元件形成面相互面对的方式层叠(例如，日本未审专利申请公布No.2011-54800)。日本未审专利申请公布No.2011-54800中描述的技术是一种使第一半导体芯片和第二半导体芯片在它们之间发送和接收信号的技术。具体地，电感器形成在第一半导体芯片和第二半导体芯片的每一个中，并且这些电感器相互面对。随后，通过在这些电感器之间发送和接收信号而在第一半导体芯片和第二半导体芯片之间执行信号的发送和接收。
而且，日本未审专利申请公布No.2011-54800描述了一种半导体器件，其中第一半导体芯片安装在引线框架的元件安装部上，而且第二半导体芯片安装在该第一半导体芯片上。在这种半导体器件中，第二半导体芯片的元件形成面的一部分从第一半导体芯片突出。随后，通过采用接合线耦合到第二半导体芯片和引线端子。
发明内容
本发明已经调查了一种方法，借助该方法，第一半导体芯片安装在引线框架的元件安装部上，第二半导体芯片以其元件形成面面对第一半导体芯片的方式安装在该第一半导体芯片上，而且第二半导体芯片和引线端子借助接合线彼此耦合。在这种情况下，当小型化半导体器件时，由于本发明人的调查，已经考虑到会出现用于将接合线耦合到第二半导体芯片的接合头将干扰元件安装部的可能性。将从本说明书的说明和附图中使其他问题和新特征变得清楚。
根据一个实施例，半导体器件具有芯片安装部，第一半导体芯片和第二半导体芯片。第一半导体芯片在其第一主面面对芯片安装部的方向上安装在芯片安装部上。第二半导体芯片的一部分在其第三主面面对第一半导体芯片的方向上安装在第一半导体芯片上。元件安装部具有凹口部。第二半导体芯片的一部分与凹口部重叠。第二电极焊盘设置在与凹口部重叠的第二半导体芯片的第三主面的区域中。第一接合线耦合到第一半导体芯片的第一电极焊盘，并且第二接合线耦合到第二电极焊盘。
根据一个实施例，能抑制用于将接合线耦合到第二半导体芯片的接合头干扰元件安装部。
附图说明
图1是示出根据一个实施例的半导体器件的构造的平面图；
图2是图1的A-A'截面图；
图3是放大由图1中的虚线围绕的区域的示意图；
图4是放大由图2中的虚线围绕的区域的示意图；
图5是示出第一半导体芯片的结构的一个实例的平面图；
图6是图5的B-B'截面图；
图7是示出第二半导体芯片的结构的一个实例的平面图；
图8是图7的C-C'截面图；
图9是示出固定层的形状的第一实例的截面图；
图10是示出固定层的形状的第二实例的截面图；
图11是示出固定层的形状的第三实例的截面图；
图12A和12B是用于解释制造半导体器件的方法的截面图；
图13A和13B是用于解释制造半导体器件的方法的截面图；
图14A，14B和14C是用于解释制造半导体器件的方法的截面图；
图15A，15B和15C是用于解释制造半导体器件的方法的截面图；
图16A和16B是示出图13A和13B中所示的步骤细节的流程图；
图17A和17B是示出图13A和13B中所示的步骤细节的流程图；
图18是根据一个变型例的第一半导体芯片的平面图；以及
图19是根据一个变型例的第二半导体芯片的平面图。
具体实施方式
以下将利用附图解释实施例。顺便提及，在所有附图中，相同的符号指定相同的部件并且适当省略其说明。
实施例
图1是示出根据一个实施例的半导体器件SD的构造的平面图。图2是图1的A-A'截面图。图3是放大由图1的虚线围绕的区域的示意图。图4是放大由图2的虚线围绕的区域的示意图。根据该实施例的半导体器件SD具有芯片安装部DP，第一半导体芯片SC1以及第二半导体芯片SC2。第一半导体芯片SC1安装在芯片安装部DP上；第二半导体芯片SC2的一部分安装在第一半导体芯片SC1上。
详细来说，如图2中所示，第一半导体芯片SC1具有第一主面SFC1和第二主面SFC2。第二主面SFC2是与第一主面SFC1相反的面。第一半导体芯片SC1在第二主面SFC2面对芯片安装部DP的方向上安装在芯片安装部DP上。
而且，如图2中所示，第二半导体芯片SC2具有第三主面SFC3和第四主面SFC4。第四主面SFC4是与第三主面SFC3相反的面。随后，第二半导体芯片SC2的一部分在其中第三主面SFC3面对第一主面SFC1的方向上安装在第一半导体芯片SC1上。
如图1和图3中所示，在平面图中，芯片安装部DP具有凹口部CP。第二半导体芯片SC2的一部分与凹口部CP重叠。而且，在第一半导体芯片SC1的第一主面SFC1的不与第二半导体芯片SC2重叠的部分中，提供第一电极焊盘PAD11、PAD12；在第二半导体芯片SC2的第三主面SFC3的不与凹口部CP重叠的区域中，提供第二电极焊盘PAD2。此外，半导体器件SD具有第一接合线WIR1和第二接合线WIR2。第一接合线WIR1的一端耦合到第一电极焊盘PAD11(或第一电极焊盘PAD12)；第二接合线WIR2的一端耦合到第二电极焊盘PAD2。以下将详细解释。
第一半导体芯片SC1例如是用于功率控制的半导体芯片，并具有用于功率控制的功率晶体管和用于控制该功率晶体管的控制电路。而且，第一半导体芯片SC1可以具有逻辑电路。第二半导体芯片SC2例如是微型计算机(微控制器(MCU：微控制单元))，微处理器(MPU：微处理单元)等等。则，第一半导体芯片SC1的尺寸大于第二半导体芯片SC2。在这种情况下，如本实施例中所示，通过将第一半导体芯片SC1设置在第二半导体芯片SC2下而稳定半导体器件SD的结构。但是，第一半导体芯片SC1可以具有与第二半导体芯片SC2相同量级的尺寸。
而且，第二半导体芯片SC2比第一半导体芯片SC1厚。例如，第一半导体芯片SC1的厚度不小于100μm且不大于300μm；第二半导体芯片SC2的厚度不小于300μm且不大于500μm。
在图1和图2中所示的实例中，芯片安装部DP是引线框架的管芯焊盘，并且为近似多边形，例如矩形。随后，凹口部CP设置在芯片安装部DP的边SID1上。将平面图中以及垂直于边SID1的方向上的第二半导体芯片SC2的长度定义为L(参考图1和3)，从第二半导体芯片SC2位于第一半导体芯片SC1上的部分的端部至凹口部CP的距离e设定为大于或等于L/2(参考图1和3)。在图1中所示的实例中，芯片安装部DP为近似矩形且边SID1是芯片安装部DP的长边。随后，支撑部FS1(例如悬置引脚)的一端耦合到芯片安装部DP的三个剩余边当中的与边SID1相交的两个边中的每一个。在图1中所示的实例中，支撑部FS1耦合到芯片安装部DP的短边的大致中心。
而且，支撑部FS2还耦合到芯片安装部DP。支撑部FS2也是悬置引脚，并且位于引线框架的引线端子之间。换言之，支撑部FS2是被制成为悬置引脚的引线端子当中的、既未耦合到第一半导体芯片SC1也未耦合到第二半导体芯片SC2的端子。为此，没有耦合到芯片安装部DP的支撑部FS2的端部延伸至密封树脂MDR(将在下文说明)外部。通过提供支撑部FS2，可以稳定芯片安装部DP的位置和方向。而且，因为引线端子被转用为支撑部FS2，与增加新的悬置引脚的情况相比，能抑制引线框架扩大。
在图1中所示的实例中，多个第二引线端子LT2设置在芯片安装部DP面对边SID1的一侧。随后，在平面图中，多个第一引线端子LT1隔着芯片安装部DP设置在第二引线端子LT2的相反侧。第二接合线WIR2的另一端耦合到第二引线端子LT2，并且第一接合线WIR1的另一端耦合到第一引线端子LT1。随后，在多个第一引线端子LT1当中提供支撑部FS2。具体地，提供两个支撑部FS2。该两个支撑部FS2都分别耦合到芯片安装部DP的四个角当中与没有联接到边SID1的两个角。顺便提及，耦合到第一接合线WIR1的第一引线端子LT1的端部面对芯片安装部DP的短边。
而且，第一引线端子LT1耦合到第一接合线WIR1的面(在图2中所示的实例中，与第一半导体芯片SC1的第一主面SFC1相对的面)以及第二引线端子LT1耦合到第二接合线WIR2的面(在图2中所示的实例中，与第二半导体芯片SC2的第三主面SFC3相对的面)彼此相反。随后，金属层ML1形成在第一引线端子LT1的引线耦合侧端部的、第一接合线WIR1耦合到的面上；金属层ML2形成在第二引线端子LT2的引线耦合侧端部的、第二接合线WIR2耦合到的面上。换言之，其上形成金属层ML2的第二引线端子LT2的面与其上形成金属层ML1的第一引线端子LT1的面相反。金属层ML1、ML2由容易接合接合线的金属形成。在接合线是金线的情况下，金属层ML1、ML2例如由锡银镀覆等形成。
顺便提及，因为第一半导体芯片SC1安装在芯片安装部DP上，因此希望芯片安装部DP的电势与第一半导体芯片SC1的衬底电势一致。在第一半导体芯片SC1是用于功率控制的元件的情况下，第一半导体芯片SC1的衬底电势和第二半导体芯片SC2的衬底电势之间存在大差异。为此，如果芯片安装部DP和第二引线端子LT2彼此靠近，则会发生将不能确保它们之间的绝缘的可能性。与此相反，在图1中所示的实例中，在平面图中，从第二引线端子LT2至芯片安装部DP的距离w2大于从第一引线端子LT1至芯片安装部DP的距离w1。为此，能确保芯片安装部DP和第二引线端子LT2之间的绝缘。
如图2中所示，第一接合线WIR1和第二接合线WIR2中的每一个都具有在半导体器件SD的厚度方向上的拐点。
此外，在平面图中，从第一引线端子LT1至第一接合线WIR1的拐点BP1的距离比从第一半导体芯片SC1的第一电极焊盘PAD11(或第一电极焊盘PAD12)至拐点BP1的距离长。此外，第一接合线WIR1的另一端部(耦合到第一引线端子LT1的端部)相对于第一引线端子LT1的角度小于第一接合线WIR1的一端(耦合到第一半导体芯片SC1的端部)相对于第一半导体芯片SC1的角度。这是因为第一接合线WIR1的一端耦合到第一电极焊盘PAD11(或第一电极焊盘PAD12)，并且随后，第一接合线WIR1的另一端耦合到第二引线端子LT2。
与此相反，在平面图中，从第二引线端子LT2至第二接合线WIR2的拐点BP2的距离比从第二半导体芯片SC2的第二电极焊盘PAD2至拐点BP2的距离短。此外，第二接合线WIR2的另一端(耦合到第二引线端子LT2的端部)相对于第二引线端子LT2的角度大于第二接合线WIR2的一端(耦合到第二半导体芯片SC2的端部)相对于第二半导体芯片SC2的角度。这是因为在第二接合线WIR2的该另一端耦合到第二引线端子LT2之后，第二接合线WIR2的该一端耦合到第二电极焊盘PAD2。
而且，半导体器件SD具有树脂保持部PH。树脂保持部PH包括两个相邻的第三引线端子LT3和一个端子耦合部LC。端子耦合部LC与位于密封树脂MDR内部的第三引线端子LT3的端部相互耦合。端子耦合部LC与第三引线端子LT3一体形成。在图1中所示的实例中，虽然第三引线端子LT3与第二引线端子LT2并排设置，但是它们都不耦合到接合线。而且，接合线也不耦合到端子耦合部LC。随后，树脂保持部PH在边SID1延伸的方向上(图1中的X方向)分别设置在多个第二引线端子LT2的两侧。换言之，多个第二引线端子LT2设置在第一树脂保持部PH和第二树脂保持部PH之间。设置树脂保持部PH以便抑制端子耦合部LC从密封树脂MDR脱落。
顺便提及，在图1中所示的实例中，第二引线端子LT2的数量少于第一引线端子LT1的数量。为此，树脂保持部PH与第二引线端子LT2并排设置。但是，在第一引线端子LT1的数量少于第二引线端子LT2的数量的情况下，树脂保持部PH可以与第一引线端子LT1并排排列。
第一半导体芯片SC1布置为与芯片安装部DP的中心重叠。与此相反，第二半导体芯片SC2小于第一半导体芯片SC1，并且为此，其放置为朝向芯片安装部DP的边SID1靠近。此外，在平面图中，第二半导体芯片SC2的一部分从第一半导体芯片SC1突出，并且这种突出部与设置在芯片安装部DP中的凹口部CP重叠。
在图1中所示的实例中，在边SID1延伸的方向上(图1中的X方向)，使凹口部CP的宽度大于第二半导体芯片SC2的宽度。为此，在图1的X方向上，整个第二半导体芯片SC2位于凹口部CP内部。但是，在图1的X方向上，第二半导体芯片SC2的端部与芯片安装部DP重叠。
而且，在平面图中，斜度形成在凹口部CP的开口侧的端部TP中。这种斜度面对凹口部CP随位置不断向外而宽度增加的方向。虽然端部TP相对于边SID1的角度α(参考图3)例如为不小于135°且不大于180°，但不限于这个范围。
面对第一半导体芯片SC1的凹口部CP的边SID2的宽度比凹口部CP的宽度宽。为此，在边SID2延伸的方向上，第一半导体芯片SC1位于边SID2附近的部分的两端都由芯片安装部DP支撑。因此，与使芯片安装部DP在垂直于边SID2的方向上的宽度小的情况相比，可以改善第一半导体芯片SC1的稳定性。顺便提及，在平面图中，边SID2的一部分与凹口部CP重叠。
第一半导体芯片SC1具有半导体元件以及在第一主面SFC1上的第一多层布线层MINC1(下文说明)。第一电极焊盘PAD11和第一电极焊盘PAD12形成在第一多层布线层MINC1上。在图1中所示的实例中，第一电极焊盘PAD11沿第一半导体芯片SC1的边缘布置，并且第一电极焊盘PAD12比第一电极焊盘PAD11布置得更靠近第一半导体芯片SC1的内部。为此，从第一电极焊盘PAD12至第二半导体芯片SC2的距离短于从第一电极焊盘PAD11至第二半导体芯片SC2的距离。第一电极焊盘PAD12耦合到第一半导体芯片SC1具有的功率晶体管；第一电极焊盘PAD11耦合到该功率晶体管的控制电路或逻辑电路中的任一个。
第二半导体芯片SC2具有半导体元件以及第三主面SFC3上的第二多层布线层MINC2(下文说明)。第二电极焊盘PAD2形成在第二多层布线层MINC2上。
随后，如图4中详细示出，第一半导体芯片SC1利用固定层FR1固定至芯片安装部DP。芯片安装部DP例如是导电浆料，例如银浆。
而且，如图1和图4详细示出，第二半导体芯片SC2在第二多层布线层MINC2面对第一半导体芯片SC1的第一多层布线层MINC1的方向上利用固定层FR2固定在第一半导体芯片SC1上。固定层FR2例如利用非导电膜(NCF)形成。随后，如图3和图4中所示，固定层FR2的一部分蔓延至第二半导体芯片SC2的侧面位于第一半导体芯片SC1上的部分上，从而形成填角(fillet)FR21。
顺便提及，第二半导体芯片SC2的第四主面SFC4由保护层PR1覆盖。在图4中所示的实例中，保护层PR1覆盖第四主面SFC4的整个表面。保护层PR1例如是管芯附接膜(DAF)，并且被提供为以便在第二半导体芯片SC2安装至第一半导体芯片SC1上时保护第二半导体芯片SC2。顺便提及，可以不提供保护层PR1。
而且，第一电感器IND1(下文说明)形成在第一半导体芯片SC1的第一多层布线层MINC1上；第二电感器IND2形成在第二半导体芯片SC2的第二多层布线层MINC2上。在平面图中，第一电感器IND1和第二电感器IND2彼此重叠，并且它们相互电结合(例如电感耦合)。随后，第二半导体芯片SC2产生的用于功率晶体管控制的信号通过第二电感器IND2和第一电感器IND1输入至用于第一半导体芯片SC1的功率晶体管控制的电路。
而且，如图1和图2中所示，半导体器件SD具有密封树脂MDR。密封树脂MDR密封以下元件：芯片安装部DP；第一半导体芯片SC1；第二半导体芯片SC2；第一接合线WIR1；第二接合线WIR2；第一引线端子LT1与第一接合线WIR1的耦合部；第二引线端子LT2与第二接合线WIR2的耦合部；端子耦合部LC；第三引线端子LT3与端子耦合部LC的耦合部；以及支撑部FS2的一部分。在图2中所示的实例中，芯片安装部DP的背面位于密封树脂MDR内部。顺便提及，因为图1和图2示出半导体器件SD的密封结构的一个实例，因此半导体器件SD的密封结构不限于图1和图2中所示的实例。
图5是示出第一半导体芯片SC1的结构的一个实例。图6是图5的B-B'截面图。如图5中所示，第一半导体芯片SC1具有作为功率控制的元件的多个晶体管(本附图中所示的实例中，一个第一晶体管TR1以及两个第二晶体管TR2)。第一晶体管TR1是第一导电类型(例如p沟道型)的晶体管，并且第二晶体管TR2是第二导电类型(例如n沟道型)的晶体管。第一晶体管TR1和两个第二晶体管TR2沿第一半导体芯片SC1的、在边SID2相反侧的边布置。那么，第一晶体管TR1位于两个第二晶体管TR2之间。在第一晶体管TR1和第二晶体管TR2上，形成分别耦合到相应晶体管的第一电极焊盘PAD12。
而且，第一半导体芯片SC1具有至少一个第一电感器IND1(在本附图中所示的实例中为两个电感器)。第一电感器IND1位于平面图中与第二半导体芯片SC2重叠的区域中。如图6中所示，第一电感器IND1利用第一多层布线层MINC1形成。换言之，形成在同一层中的布线(未示出)或过孔(via)作为第一电感器IND1。第一多层布线层MINC1形成在第一衬底SUB1上。第一衬底SUB1是诸如硅衬底的半导体衬底。顺便提及，第一晶体管TR1和第二晶体管TR2形成在第一衬底SUB1上。而且，第一电感器IND1的卷轴面对与第一衬底SUB1相交的方向(例如垂直方向)。
顺便提及，如图5和图6中所示，第一凹陷DEP1形成在平面图中第一半导体芯片SC1的与第二半导体芯片SC2重叠的区域中。第一凹陷DEP1的宽度大于第二半导体芯片SC2的宽度。为此，当使第一半导体芯片SC1和第二半导体芯片SC2彼此重叠时，第二半导体芯片SC2适配在第一凹陷DEP1中。顺便提及，因为需要第二半导体芯片SC2的一部分从边SID2向第一半导体芯片SC1的外部突出，因此第一凹陷DEP1与边SID2相连。
通过部分地不形成在第一半导体芯片SC1具有的第一多层布线层MINC1中的、位于比其上形成了第一电感器IND1的层高的布线层中的至少一层(包括其上形成第一电极焊盘PAD11和第一电极焊盘PAD12的层)而形成第一凹陷DEP1。这就缩短了第一电感器IND1和下述第二电感器IND2之间的距离，并且由此可以提升它们之间的通信精度。顺便提及，第一半导体芯片SC1可以不具有第一凹陷DEP1。
图7是示出第二半导体芯片SC2的结构的一个实例。图8是图7的C-C'截面图。第二半导体芯片SC2具有至少一个第二电感器IND2(在本附图中所示的实例中为两个电感器)。第二电感器IND2的数量与第一电感器IND1的数量相同。当第二半导体芯片SC2布置在第一半导体芯片SC1上时，第二电感器IND2形成在其与第一电感器IND1重叠的位置中。由此，在第二半导体芯片SC2与第一半导体芯片SC1隔离的状态下，第二半导体芯片SC2能通过第二电感器IND2和第一电感器IND1与第二半导体芯片SC2通信。
如图8中所示，第二电感器IND2利用第二多层布线层MINC2形成。第二多层布线层MINC2形成在第二衬底SUB2上。第二衬底SUB2是诸如硅衬底的半导体衬底。形成电路的元件(例如MOS晶体管)形成在第二衬底SUB2上。而且，第二电感器IND2的中心轴面对与第二衬底SUB2相交的方向(例如垂直方向)。
顺便提及，如图7和图8中所示，第二凹陷DEP2形成在平面图中第二半导体芯片SC2的与第一半导体芯片SC1重叠的区域中。第二凹陷DEP2与第二半导体芯片SC2的三个边耦合。
通过部分地不形成在第二半导体芯片SC2具有的第二多层布线层MINC2中的、位于比其上形成了形成第二电感器IND2的层高的布线层中的至少一层(包括其上形成第二电极焊盘PAD2的层)而形成第二凹陷DEP2。这就缩短了第二电感器IND2和第一电感器IND1之间的距离，并且由此可以提升它们之间的通信精度。顺便提及，第二半导体芯片SC2可以不具有第二凹陷DEP2。
而且，第二衬底SUB2的厚度厚于第一衬底SUB1的厚度。由此，使第二半导体芯片SC2厚于第一半导体芯片SC1。第二衬底SUB2的厚度例如为不小于300μm且不大于500μm；第一衬底SUB1的厚度例如为不小于100μm且不大于300μm。
图9是示出固定层FR2的形状的第一实例的截面图。在本附图中所示的实例中，使填角FR21高于第二半导体芯片SC2的保护层PR1。而且，固定层FR2的一部分突出进入第一半导体芯片SC1在边SID2一侧的侧面中，并构成填角FR22。因此，因为固定层FR2也形成填角FR22，因此第二半导体芯片SC2与第一半导体芯片SC1的固定强度变大。由此，如将在下文说明的，在将第二接合线WIR2附接至第二半导体芯片SC2的步骤中，能抑制第二半导体芯片SC2从第一半导体芯片SC1上脱落。而且，通过形成的填角FR21、FR22，能抑制第二半导体芯片SC2由于应力而导致的弯曲。
而且，还能抑制第二半导体芯片SC2和第一半导体芯片SC1之间的介电击穿的发生。详细来说，第二半导体芯片SC2和第一半导体芯片SC1之间的介电击穿的起始点是第二半导体芯片SC2距第一半导体芯片SC1的距离短的部分。在本实施例中，第二半导体芯片SC2的侧面的位于第一半导体芯片SC1上的部分由填角FR21覆盖。为此，能抑制在第二半导体芯片SC2的侧面作为起始点的情况下在第一半导体芯片SC1和第二半导体芯片SC2之间发生介电击穿。
图10是示出固定层FR2的形状的第二实例的截面图。除填角FR21没有到达保护层PR1这一点之外，本附图中所示的实例与图9中所示的实例相同。
图11是示出固定层FR2的形状的第三实例的截面图。虽然本附图中所示的实例中，使填料FR21的一部分高于保护层PR1，但是除填料FR21的剩余部分没有到达保护层PR1这一点之外，其与图9中所示的实例相同。
图12至图15的各个附图都是用于解释制造半导体器件SD的方法的截面图。首先，制造第一半导体芯片SC1和第二半导体芯片SC2。第一半导体芯片SC1和第二半导体芯片SC2例如如下制造。
首先，元件隔离膜形成在处于晶片状态下的第一衬底SUB1(或第二衬底SUB2)上。由此，隔离了元件形成区。例如通过采用STI方法形成元件隔离膜，但是也可通过采用LOCOS方法形成。随后，栅极绝缘膜和栅电极形成在位于元件形成区中的半导体衬底上。栅极绝缘膜可以是氧化硅膜或可以是其介电常数高于氧化硅膜的介电常数的高介电常数膜(例如硅酸铪膜)。在栅极绝缘膜是氧化硅膜的情况下，借助多晶硅膜形成栅电极。而且，在栅极绝缘膜是高介电常数膜的情况下，借助金属膜(例如TiN)和多晶硅膜的叠层膜形成栅电极。而且，当借助多晶硅形成栅电极时，在形成栅电极的步骤中，可以在元件隔离膜上形成多晶硅阻挡。
随后，源极和漏极的延伸区形成在位于元件形成区中的半导体衬底上。随后，侧壁形成在栅电极的侧壁上。随后，变成源极和漏极的杂质区形成在位于元件形成区的半导体衬底中。因此，MOS晶体管形成在半导体衬底上。
而且，在第一半导体芯片SC1的制造步骤中，通过采用上述步骤的至少一部分形成第一晶体管TR1和第二晶体管TR2。
随后，第一多层布线层MINC1(或第二多层布线层MINC2)形成在元件隔离膜和MOS晶体管上。第一电极焊盘PAD11、PAD12(或第二电极焊盘PAD2)形成在最上层的布线层上。随后，保护绝缘膜(钝化膜)形成在多层布线层上。位于电极焊盘上的孔形成在保护绝缘膜中。
此后，通过将变成第一半导体芯片SC1的晶片切割成独立的芯片而形成第一半导体芯片SC1。
而且，对于变成第二半导体芯片SC2的晶片来说，如图12A中所示，保护层PR1粘在作为晶片中的第二半导体芯片SC2的第四主面SFC4的面上。而且，凸块BMP形成在各个第二电极焊盘PAD2上。利用诸如金的容易接合第二接合线WIR2的金属形成凸块BMP。
随后，如图12B中所示，变成第二半导体芯片SC2的晶片被切割成具有保护层PR1的独立的芯片。由此，借助提供在其上的保护层PR1制造第二半导体芯片SC2。
顺便提及，在将晶片切割成第一半导体芯片SC1之前，研磨第一半导体芯片SC1的第一衬底SUB1以减薄。类似地，在第二半导体芯片SC2上提供保护层PR1之前，如果需要，则研磨第二半导体芯片SC2的第二衬底SUB2以减薄。
随后，如图13A中所示，固定层FR2设置在第一半导体芯片SC1的第一主面SFC1的其上安装第二半导体芯片SC2的区域上。随后，如图13B中所示，第二半导体芯片SC2安装在第一半导体芯片SC1上。此时，使第二半导体芯片SC的第三主面SFC3面对固定层FR2。而且，使第二半导体芯片SC2的凸块BMP此时没有被第一半导体芯片SC1或固定层FR2覆盖。
随后，如图14A中所示，利用固定层FR1将第一半导体芯片SC1和第二半导体芯片SC2的层叠体安装在引线框架的芯片安装部DP上。此时，使芯片安装部DP的凹口部CP以及第二半导体芯片SC2的凸块BMP彼此重叠。
随后，如图14B中所示，通过使用第一接合线WIR1将第一半导体芯片SC1的第一电极焊盘PAD11和第一电极焊盘PAD12耦合到第一引线端子LT1。此时，在第一接合线WIR1的一端固定至第一电极焊盘PAD11(或第一电极焊盘PAD12)之后，第一接合线WIR1的另一端固定至第一引线端子LT1。
随后，如图14C中所示，将引线框架翻转。
随后，如图15A中所示，通过使用第二接合线WIR2将第二半导体芯片SC2的第二电极焊盘PAD2耦合到第二引线端子LT2。此时，在第二接合线WIR2的另一端固定至第二引线端子LT2之后，第二接合线WIR2的一端固定至凸块BMP(即，第二电极焊盘PAD2)。顺便提及，为了执行本步骤，也需要在保持引线框架的阶段提供与凹口部CP相同的凹口。
在本步骤中，凸块BMP预先形成在第二电极焊盘PAD2上。为此，第二接合线WIR2的一端可以在第二接合线WIR2的一端没有牢固地压至第二电极焊盘PAD2的情况下耦合到第二电极焊盘PAD2。因此，当第二接合线WIR2固定至第二电极焊盘PAD2时，能抑制第二半导体芯片SC2从第一半导体芯片SC1上脱落。
而且，在第二接合线WIR2的一端附接至第二电极焊盘PAD2之后，当第二接合线WIR2的另一端附接至第二引线端子LT2时，在第二接合线WIR2的一端附接至第二电极焊盘PAD2之后，当第二接合线WIR2的另一端附接至第二引线端子LT2时的过程中，会出现通过第二接合线WIR2将力施加至第二半导体芯片SC2的可能性。在这种情况下，会出现第二半导体芯片SC2从第一半导体芯片SC1上脱落的可能性。在本实施例中，因为第二接合线WIR2在其附接至第二引线端子LT2之后附接至第二电极焊盘PAD2，因此能抑制这种问题发生。
而且，使第二半导体芯片SC2厚于第一半导体芯片SC1。因此，当第二接合线WIR2附接至第二半导体芯片SC2时，能抑制第二半导体芯片SC2被损坏。
随后，如图15B中所示，将引线框架翻转。由此，引线框架的输送变得容易。随后，通过使用用于密封的金属模具形成密封树脂MDR。
随后，如图15C中所示，使第一引线端子LT1和第二引线端子LT2位于密封树脂MDR外部的部分变形以制成端子。
顺便提及，在将第一半导体芯片SC1安装在芯片安装部DP上之后，第二半导体芯片SC2可以安装在第一半导体芯片SC1上。
图16和图17是示出图13A和13B中所示的步骤的细节的流程图。首先，如图16A中所示，通过使用组装设备AT保持(例如被吸附)被切割成预定形状的片状固定层FR2。在这种状态下，覆盖膜CF设置在由组装设备AT保持的固定层FR2的面上。随后，通过使用组装设备AT，将固定层FR2压至第一半导体芯片SC1的其上安装了第二半导体芯片SC2的区域。
随后，如图16B中所示，将吸附了覆盖膜CF的组装设备AT升高。由此从固定层FR2上移除覆盖膜CF。
随后，如图17A中所示，使组装设备AT保持第二半导体芯片SC2。组装设备AT例如吸附第二半导体芯片SC2的第四主面SFC4。因为此时第四主面SFC4由保护层PR1覆盖，因此没有对第四主面SFC4造成裂纹。
随后，使用组装设备AT将第二半导体芯片SC2压至固定层FR2。由此，第二半导体芯片SC2固定在第一半导体芯片SC1上。而且，此时在固定层FR2中形成填角FR21、FR22。
随后，如图17B中所示，从组装设备AT上分离第二半导体芯片SC2。
以下，将解释本实施例的效果。本实施例中，凹陷部CP形成在芯片安装部DP中。则在平面图中，第二半导体芯片SC2的第二电极焊盘PAD2与凹陷部CP重叠。因此，当将第二接合线WIR2的一端附接至第二电极焊盘PAD2时，能抑制接合工具和芯片安装部DP彼此干扰。
而且，位于多个第二接合线WIR2当中的端部处的第二接合线WIR21(例如，图3中位于右端的第二接合线WIR2以及位于左端的第二接合线WIR2)倾斜延伸至芯片安装部DP的边SID1。为此，会产生第二接合线WIR21或用于附接该线的接合工具与凹陷部CP的端部TP接触的可能性。与此相反，在本实施例中，在凹陷部CP的端部TP处提供斜度。因此，能抑制第二接合线WIR21或用于附接该线的接合工具与凹陷部CP的端部TP接触。
变型例
图18是根据变型例的第一半导体芯片SC1的平面图，并且图19是根据变型例的第二半导体芯片SC2的平面图。除在第一半导体芯片SC1的第一主面SFC1上形成凸起PTN1以及在第二半导体芯片SC2的第二主面SFC2上形成凹陷PTN2这一点之外，根据本变型例的半导体器件SD具有与根据实施例的半导体器件SD相同的构造。
利用第一半导体芯片SC1的第一多层布线层MINC1或其上的保护绝缘膜形成凸起PTN1；利用第二半导体芯片SC2的第二多层布线层MINC2或其上的保护绝缘膜形成凹陷PTN2。具体地，通过移除第一半导体芯片SC1的最上层的至少一层上的位于凸起PTN1周围的部分而形成凸起PTN1。而且，通过在第一半导体芯片SC1的最上层的至少一层中移除将作为凹陷PTN2的区域而形成凹陷PTN2。
凹陷PTN2的平面形状与凸起PTN1的平面形状相同。则在第一半导体芯片SC1和第二半导体芯片SC2彼此重叠的情况下，凸起PTN1与凹陷PTN2重叠。凸起PTN1的至少上部可以适配于凹陷PTN2中。
借助本变型例，也可以获得与实施例相同的效果。而且，可以通过重叠凸起PTN1和凹陷PTN2的位置提升第一半导体芯片SC1和第二半导体芯片SC2的相对位置精度。这样能抑制第一电感器IND1和第二电感器IND2之间发生通信错误。特别地，在使凸起PTN1的至少上部适配进凹陷PTN2的情况下，第一半导体芯片SC1和第二半导体芯片SC2的相对位置精度变得特别高。
顺便提及，即使在第一半导体芯片SC1的第一主面SFC1中形成凹陷且在第二半导体芯片SC2的第三主面SFC3中形成凸起的情况下，也能获得与本变型例相同的效果。
上文中，虽然根据实施例具体解释了由本发明人提出的本发明，但是不言而喻的是本发明不限于实施例，并且可以在不脱离其主旨的范围内进行各种变型。

Claims (14)

1.一种半导体器件，包括：
芯片安装部；
第一半导体芯片，所述第一半导体芯片具有第一主面以及作为所述第一主面的相反侧的面的第二主面，并且所述第一半导体芯片在所述第二主面面对所述芯片安装部的方向上安装在所述芯片安装部上；以及
第二半导体芯片，所述第二半导体芯片具有第三主面以及作为所述第三主面的相反侧的面的第四主面，并且所述第二半导体芯片的一部分在所述第三主面面对所述第一主面的方向上安装在所述第一半导体芯片上，
其中，在平面图中，所述芯片安装部具有凹口部，并且所述第二半导体芯片的一部分与所述凹口部重叠，并且进一步
其中，所述半导体器件包括：
第一电极焊盘，所述第一电极焊盘位于所述第一半导体芯片的所述第一主面的不与所述第二半导体芯片重叠的部分中；
第二电极焊盘，所述第二电极焊盘位于所述第二半导体芯片的所述第三主面的与所述凹口部重叠的区域中；
第一接合线，所述第一接合线的一端耦合到所述第一电极焊盘；以及
第二接合线，所述第二接合线的一端耦合到所述第二电极焊盘。
2.根据权利要求1所述的半导体器件，包括：
第一电感器，所述第一电感器形成在所述第一半导体芯片的所述第一主面上；以及
第二电感器，所述第二电感器形成在所述第二半导体芯片的所述第三主面上，
其中，在平面图中，所述第一电感器和所述第二电感器彼此重叠。
3.根据权利要求1所述的半导体器件，
其中，所述第一半导体芯片的面对所述凹口部的边的宽度比所述凹口部的宽度宽，并且
其中，在平面图中，所述第一半导体芯片的一部分与所述凹口部重叠。
4.根据权利要求1所述的半导体器件，
其中，在平面图中，在所述凹口部的开口侧的端部中形成斜度。
5.根据权利要求1所述的半导体器件，包括：
第一引线端子，所述第一接合线的另一端耦合到所述第一引线端子；
第二引线端子，所述第二接合线的另一端耦合到所述第二引线端子；
两个第三引线端子，所述两个第三引线端子与所述第二引线端子并排布置；
端子耦合部，所述端子耦合部将所述两个第三引线端子的在所述芯片安装部一侧的端部相互耦合；以及
密封树脂，所述密封树脂密封以下：所述芯片安装部；所述第一半导体芯片；所述第二半导体芯片；所述第一接合线；所述第二接合线；所述第一引线端子的至少所述第一接合线耦合到的部分；所述第二引线端子的至少所述第二接合线耦合到的部分；所述两个第三端子的至少所述端子耦合部耦合到的部分；以及所述端子耦合部。
6.根据权利要求5所述的半导体器件，
其中，在平面图中，所述第二引线端子和所述第三引线端子隔着所述芯片安装部布置在所述第一引线端子的相反侧，并且
其中，从所述第二引线端子至所述芯片安装部的距离比从所述第一引线端子至所述芯片安装部的距离远。
7.根据权利要求5所述的半导体器件，包括：
多个组，所述多个组每个均包括所述两个第三引线端子和所述端子耦合部；并且
在第一组和第二组之间具有多个所述第二引线端子。
8.根据权利要求5所述的半导体器件，在平面图中，所述第二引线端子和所述第三引线端子隔着所述芯片安装部布置在所述第一引线端子的相反侧，所述器件包括：
多个所述第一引线端子；以及
支撑部，所述支撑部位于所述第一引线端子之间并且耦合到所述芯片安装部。
9.根据权利要求5所述的半导体器件，
其中，所述第一接合线的所述另一端相对于所述第一引线端子的角度小于所述第一接合线的所述一端相对于所述第一半导体芯片的角度，并且
其中，所述第二接合线的所述另一端相对于所述第二引线端子的角度大于所述第二接合线的所述一端相对于所述第二半导体芯片的角度。
10.根据权利要求1所述的半导体器件，
其中，所述第二半导体芯片比所述第一半导体芯片厚。
11.根据权利要求1所述的半导体器件，包括：
保护层，所述保护层设置在所述第二半导体芯片的所述第四主面上。
12.根据权利要求1所述的半导体器件，包括：
功率控制器元件，所述功率控制器元件形成在所述第一半导体芯片上。
13.根据权利要求1所述的半导体器件，包括：
固定层，所述固定层位于所述第二半导体芯片的所述第三主面和所述第一半导体芯片的所述第一主面之间，
其中，所述固定层的一部分位于所述第二半导体芯片的侧面上，并且所述固定层的另一部分位于所述第一半导体芯片的侧面的与所述第二半导体芯片重叠的区域上。
14.根据权利要求1所述的半导体器件，包括：
凸起，所述凸起形成在所述第一半导体芯片的所述第一主面以及所述第二半导体芯片的所述第三主面中的任一个中；以及
凹口部，所述凹口部形成在所述第一半导体芯片的所述第一主面以及所述第二半导体芯片的所述第三主面中的另一个中，
其中，在平面图中，所述凸起的外形和所述凹口部的外形具有相同形状，并且所述凸起和所述凹口部彼此重叠。
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US20150084209A1 (en) 2015-03-26

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