JP6029756B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6029756B2 JP6029756B2 JP2015526185A JP2015526185A JP6029756B2 JP 6029756 B2 JP6029756 B2 JP 6029756B2 JP 2015526185 A JP2015526185 A JP 2015526185A JP 2015526185 A JP2015526185 A JP 2015526185A JP 6029756 B2 JP6029756 B2 JP 6029756B2
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- semiconductor element
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
- B23K20/004—Wire welding
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/3006—Ag as the principal constituent
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C5/00—Alloys based on noble metals
- C22C5/06—Alloys based on silver
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Description
図1は、本発明の実施の形態1による半導体装置の断面図及び上面図である。図1(a)は半導体装置の断面図であり、図1(b)は半導体装置の上面図である。半導体装置30は、シリコン(Si)やシリコンカーバイド(SiC)等のワイドバンドギャップ半導体材料を基材とした半導体素子9に形成されたAg層10と回路基板12に形成されたAg層4との間に狭持された合金層13を備えており、合金層13は、Ag層4、Ag層10のAg成分とSnによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤ5が合金層13の外周側から延伸して配置されている。半導体素子9を実装する実装基板である回路基板12は、DBC(Direct Bonded Cupper)基板であり、絶縁材2と、絶縁材2の上側に形成された上電極1と、絶縁材2の下側に形成された下電極3を備える。合金層13は、金属間化合物であり、例えばAg3Snである。合金層13を形成するために、回路基板12のAg層4に複数のワイヤ5が配置されたワイヤ構造体20が形成されている。複数のワイヤ5は、同一の方向に、合金層13の外周側から延伸して配置されている。ワイヤ構造体20は、半導体素子9のX方向の幅c1、Z方向の幅c2よりも広い範囲に形成される。ワイヤ構造体20のX方向の幅b3、Z方向の幅b2である。図1(b)では、複数のワイヤ5のうち、7本のワイヤ5a、5b、5c、5d、5e、5f、5gを明示的に記載した。複数のワイヤ5を配置するピッチは、b1である。なお、ワイヤの符号は、総括的に5を用い、区別して説明する場合に5a乃至5gを用いる。
y=2.5x ・・・(1)
y≧2.5x ・・・(2)
Agの供給量×0.5≧abcdで囲まれた領域A1 ・・・(3)
0.5×(2yz+π(x/2)2)≧(xy−π(x/2)2)
・・・(4)
ここで、左辺における2yzは領域A2と領域A3の合計面積であり、左辺におけるπ(x/2)2は半円領域A4と半円領域A5の合計面積である。右辺は領域A1の面積である。
yz+1/8πx2 ≧ xy−2/8πx2 ・・・(5)
yz+3/8πx2 ≧ xy ・・・(6)
2.5xz+3/8πx2 ≧ 2.5x2 ・・・(7)
2.5z+3/8πx ≧ 2.5x ・・・(8)
2.5z ≧ (2.5−3/8π)x ・・・(9)
z ≧ ((2.5−3/8π)/2.5)x ・・・(10)
z ≧ 0.53x ・・・(11)
z≧0.21y ・・・(12)
y=2.5x ・・・(1)
z≧0.53x ・・・(11)
z≧0.21y ・・・(12)
t≒(xy−π(x/2)2)/y ・・・(13)
式(13)に式(1)を適用して、yまたはxを消去すると、式(14)、式(15)のようになる。
t≒0.68x ・・・(14)
t≒0.27y ・・・(15)
Agのワイヤ5の配置形状は、実施の形態1で示した配置形状に限らず、例えば図13のように放射状に配置させた配置形状でも良い。図13は、本発明の実施の形態2によるワイヤの配置を示す図である。図13に示したワイヤ構造体20は、4つのワイヤ5a1、5a2、5a3、5a4で区切られた領域が同じ形状である例である。便宜上、ワイヤ5a1〜ワイヤ5a2を第1領域と呼び、ワイヤ5a2〜ワイヤ5a3を第2領域と呼び、ワイヤ5a3〜ワイヤ5a4を第3領域と呼び、ワイヤ5a4〜ワイヤ5a1を第4領域と呼ぶことにする。
5a1、5a2、5a3、5a4、5b1、5b2、5b3、5b4、
5c1、5c2、5d1、5d2、5e1、5e2…ワイヤ、8…Sn層、
9…半導体素子、10…Ag層、11…屈曲部、12…回路基板、
13…合金層、20…ワイヤ構造体、30…半導体装置。
Claims (16)
- 半導体素子が実装基板に接合された半導体装置であって、
前記実装基板に形成された第1のAg層と、前記半導体素子に形成された第2のAg層との間に挟持された合金層を備え、
前記合金層は、
第1のAg層及び第2のAg層のAg成分と、Snによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤが当該合金層の外周側から延伸して配置されたことを特徴とする半導体装置。 - 前記ワイヤは、同一の方向に延伸して配置されたことを特徴とする請求項1記載の半導体装置。
- 前記ワイヤは、前記合金層の外周側から放射状に延伸して配置されたことを特徴とする請求項1記載の半導体装置。
- 前記ワイヤの材質は、Ag以外に、Pd、Ni、Cu、Fe、Au、Pt、Al、Sn、Sb,Ti、Pのうち少なくとも1種類以上添加されていることを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記半導体素子は、ワイドバンドギャップ半導体材料であり、シリコンカーバイド、窒化ガリウム系材料、またはダイヤモンドのうちのいずれかであることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。
- 半導体素子が実装基板に接合された半導体装置を製造する半導体装置の製造方法であって、
前記実装基板に形成された第1のAg層に、Agを含んだ複数のワイヤが平行に又は放射状に配置されたワイヤ構造体を形成するワイヤ構造体形成工程と、
前記ワイヤ構造体の外形面積よりも実装面の面積が小さくて、前記実装面に第2のAg層が形成された前記半導体素子を、前記ワイヤ構造体に、Sn層を介在させて搭載する半導体素子搭載工程と、
前記半導体素子搭載工程の後に、熱処理を行い、前記実装基板と前記半導体素子とが接合された接合部に、Ag3Snの金属間化合物を有する合金層を形成する合金層形成工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記ワイヤ構造体形成工程において、前記ワイヤ構造体は、外周側に当該ワイヤ構造体の最大高さとなる屈曲部を有するように形成され、
前記半導体素子搭載工程において、前記半導体素子は、前記ワイヤ構造体における最大高さの80%よりも低い領域に搭載されることを特徴とする請求項6記載の半導体装置の製造方法。 - 前記ワイヤ構造体形成工程は、前記ワイヤを互いに平行になるように前記第1のAg層に接続するワイヤ接続工程を含むことを特徴とする請求項6または7に記載の半導体装置の製造方法。
- 前記ワイヤ構造体形成工程は、前記ワイヤを前記ワイヤ構造体の外側から内側に延伸させながら前記第1のAg層に接続するワイヤ接続工程を含むことを特徴とする請求項6または7に記載の半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、
前記第1のAg層及び前記第2のAg層の厚さをzとし、前記ワイヤのワイヤ直径をxとし、前記ワイヤが配置されるピッチをyとした場合に、
y=2.5x、z≧0.53x、z≧0.21y
を満たすことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記Sn層の厚さをtとした場合に、
t≧0.68x、t≧0.27y
を満たすことを特徴とする半導体装置の製造方法。 - 請求項6から11のいずれか1項に記載の半導体装置の製造方法において、
前記ワイヤのワイヤ直径が、12μm以上で50μm以下であることを特徴とする半導体装置の製造方法。 - 請求項6から11のいずれか1項に記載の半導体装置の製造方法において、
前記第1のAg層及び前記第2のAg層の厚さが、6.3μm以上で26.3μm以下であることを特徴とする半導体装置の製造方法。 - 請求項8、10、11のいずれか1項に記載の半導体装置の製造方法において、
前記ワイヤが配置されるピッチが、30μm以上で125μm以下であることを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記Sn層の厚さが、9μm以上で35μm以下であることを特徴とする半導体装置の製造方法。 - 請求項6から15のいずれか1項に記載の半導体装置の製造方法において、
前記Sn層は、Sn以外に、Ag、Cu、Sb、Bi、In,Zn、Mg、Si、P、Ga、Ni、Co、Geのうち少なくとも1種類以上含まれていることを特徴とする半導体装置の製造方法。
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JP6795307B2 (ja) * | 2016-02-12 | 2020-12-02 | 国立大学法人大阪大学 | 接合材、接合材の製造方法、接合構造体の作製方法 |
DE112017002961B4 (de) | 2016-06-14 | 2022-06-09 | Mitsubishi Electric Corporation | Leistungs-halbleitereinheit |
JP6621714B2 (ja) * | 2016-07-01 | 2019-12-18 | 三菱電機株式会社 | 半導体装置 |
WO2018008168A1 (ja) * | 2016-07-04 | 2018-01-11 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP6858642B2 (ja) * | 2017-05-25 | 2021-04-14 | 三菱電機株式会社 | パワーモジュール |
US10763192B2 (en) | 2017-12-07 | 2020-09-01 | Stmicroelectronics S.R.L. | Method of manufacturing semiconductor devices and corresponding semiconductor device |
WO2022049697A1 (ja) * | 2020-09-03 | 2022-03-10 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
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JPH11186331A (ja) * | 1997-12-19 | 1999-07-09 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2005032834A (ja) * | 2003-07-08 | 2005-02-03 | Toshiba Corp | 半導体チップと基板との接合方法 |
WO2011064873A1 (ja) * | 2009-11-27 | 2011-06-03 | トヨタ自動車株式会社 | 半導体装置およびその製造方法 |
JP2012054264A (ja) * | 2010-08-31 | 2012-03-15 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2013038330A (ja) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
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US6822331B2 (en) | 2001-06-14 | 2004-11-23 | Delphi Technologies, Inc. | Method of mounting a circuit component and joint structure therefor |
JP3836349B2 (ja) | 2001-09-27 | 2006-10-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2004174522A (ja) | 2002-11-25 | 2004-06-24 | Hitachi Ltd | 複合はんだ、その製造方法および電子機器 |
JP2005236019A (ja) | 2004-02-19 | 2005-09-02 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
CN101432095B (zh) | 2006-04-28 | 2013-01-16 | 株式会社电装 | 泡沫焊锡和电子器件 |
JP2009164261A (ja) | 2007-12-28 | 2009-07-23 | Seiko Epson Corp | 半導体装置および電子機器 |
US8592986B2 (en) | 2010-11-09 | 2013-11-26 | Rohm Co., Ltd. | High melting point soldering layer alloyed by transient liquid phase and fabrication method for the same, and semiconductor device |
JP5444299B2 (ja) | 2011-09-02 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH11186331A (ja) * | 1997-12-19 | 1999-07-09 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2005032834A (ja) * | 2003-07-08 | 2005-02-03 | Toshiba Corp | 半導体チップと基板との接合方法 |
WO2011064873A1 (ja) * | 2009-11-27 | 2011-06-03 | トヨタ自動車株式会社 | 半導体装置およびその製造方法 |
JP2012054264A (ja) * | 2010-08-31 | 2012-03-15 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2013038330A (ja) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
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US9536855B2 (en) | 2017-01-03 |
JPWO2015004956A1 (ja) | 2017-03-02 |
CN105247666A (zh) | 2016-01-13 |
DE112014003203B4 (de) | 2019-08-01 |
CN105247666B (zh) | 2017-12-01 |
DE112014003203T5 (de) | 2016-04-07 |
WO2015004956A1 (ja) | 2015-01-15 |
US20160035691A1 (en) | 2016-02-04 |
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