JPWO2015004956A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JPWO2015004956A1
JPWO2015004956A1 JP2014058852A JP2015526185A JPWO2015004956A1 JP WO2015004956 A1 JPWO2015004956 A1 JP WO2015004956A1 JP 2014058852 A JP2014058852 A JP 2014058852A JP 2015526185 A JP2015526185 A JP 2015526185A JP WO2015004956 A1 JPWO2015004956 A1 JP WO2015004956A1
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semiconductor
wire
layer
wires
alloy
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JP6029756B2 (ja
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浩次 山▲崎▼
浩次 山▲崎▼
荒木 健
健 荒木
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三菱電機株式会社
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004Wire welding
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/30Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/3006Ag as the principal constituent
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C5/00Alloys based on noble metals
    • C22C5/06Alloys based on silver
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Abstract

接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物を形成することを目的とする。本発明の半導体装置(30)は、実装基板(回路基板(12))に形成された第1のAg層(4)と、半導体素子(9)に形成された第2のAg層(10)との間に挟持された合金層(13)を備え、合金層(13)は、第1のAg層(4)及び第2のAg層(10)のAg成分と、Snによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤ(5)が当該合金層(13)の外周側から延伸して配置されたことを特徴とする。An object of the present invention is to form a high-melting intermetallic compound with few voids at the joint where the objects to be joined are joined. The semiconductor device (30) of the present invention includes a first Ag layer (4) formed on a mounting substrate (circuit board (12)) and a second Ag layer (10) formed on a semiconductor element (9). The alloy layer (13) is sandwiched between the first Ag layer (4) and the second Ag layer (10), and the Ag3Sn formed by Sn. A plurality of wires (5) containing an intermetallic compound and containing Ag are arranged extending from the outer peripheral side of the alloy layer (13).

Description

本発明は、半導体装置及び半導体装置の製造方法に関し、特に、半導体素子を実装する実装基板と半導体素子等との金属接合や、半導体素子とリード端等の金属接合に関するものである。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to metal bonding between a mounting substrate on which a semiconductor element is mounted and a semiconductor element, and metal bonding between a semiconductor element and a lead end.

近年、半導体装置に対する信頼性の要求はますます高まり、特に熱膨張係数差の大きい半導体素子と回路基板との接合部に対する信頼性向上が強く求められている。従来、半導体素子はシリコン(Si)やガリウム砒素(GaAs)を基材としたものが多く使われ、その動作温度は100℃〜125℃である。半導体素子を電子回路の電極に接合するはんだ材料としては、半導体素子と回路基板との熱膨張の差に起因する繰り返し熱応力に対する耐クラック性、組み立てる際の多段階はんだ接合に対応するための高融点、さらにデバイスの汚染耐性の点などから、Siデバイスでは95Pb−5Sn(質量%)、ガリウム砒素デバイスでは80Au−20Sn(質量%)などが使われてきた。しかしながら、環境負荷低減の観点から有害な鉛(Pb)を大量に含有する95Pb−5Snは問題があり、また貴金属の高騰や埋蔵量の点から80Au−20Snは代替材が強く望まれていた。   In recent years, there has been an increasing demand for reliability of semiconductor devices, and in particular, there is a strong demand for improved reliability of a junction between a semiconductor element having a large difference in thermal expansion coefficient and a circuit board. Conventionally, a semiconductor element based on silicon (Si) or gallium arsenide (GaAs) is often used, and its operating temperature is 100 ° C. to 125 ° C. Solder materials for joining semiconductor elements to the electrodes of electronic circuits include high resistance to cracking against repeated thermal stress caused by the difference in thermal expansion between the semiconductor elements and the circuit board, and multi-step solder joints during assembly. From the viewpoint of melting point and resistance to contamination of devices, 95Pb-5Sn (mass%) has been used for Si devices, and 80Au-20Sn (mass%) has been used for gallium arsenide devices. However, there is a problem with 95Pb-5Sn containing a large amount of harmful lead (Pb) from the viewpoint of reducing the environmental load, and 80Au-20Sn has been strongly desired as a substitute for 80Au-20Sn from the viewpoint of soaring precious metals and reserves.

一方、省エネルギーの観点から次世代デバイスとして、シリコンカーバイド(SiC)や窒化ガリウム(GaN)を基材としたデバイスの開発が盛んになされている。これらは、電力損失低減の観点からその動作温度が175℃以上とされており、将来的には300℃になるとも言われている。   On the other hand, development of devices based on silicon carbide (SiC) or gallium nitride (GaN) has been actively conducted as next-generation devices from the viewpoint of energy saving. These have an operating temperature of 175 ° C. or higher from the viewpoint of reducing power loss, and are said to be 300 ° C. in the future.

上記要求に対して、融点が高く、しかも耐熱性に優れた高温はんだ材(高温はんだ合金)が必要である。このようなはんだ合金は、これまで、溶融温度が300℃前後のPbベースのはんだ合金であった。例えば、Pb−10Sn(質量%)、Pb−5Sn(質量%)、Pb−2Ag−8Sn(質量%)、Pb−5Ag(質量%)などがあり、主にPbが主成分となっている。Pb−10Snの固相線温度は268℃であり、その液相線温度は302℃である。Pb−5Snの固相線温度は307℃であり、その液相線温度は313℃である。Pb−2Ag−8Snの固相線温度は275℃であり、その液相線温度は346℃である。Pb−5Agの固相線温度は304℃であり、その液相線温度は365℃である。   In response to the above requirements, a high-temperature solder material (high-temperature solder alloy) having a high melting point and excellent heat resistance is required. Such solder alloys have heretofore been Pb-based solder alloys having a melting temperature of around 300 ° C. For example, there are Pb-10Sn (mass%), Pb-5Sn (mass%), Pb-2Ag-8Sn (mass%), Pb-5Ag (mass%), etc., and Pb is mainly used as a main component. Pb-10Sn has a solidus temperature of 268 ° C and a liquidus temperature of 302 ° C. Pb-5Sn has a solidus temperature of 307 ° C and a liquidus temperature of 313 ° C. Pb-2Ag-8Sn has a solidus temperature of 275 ° C and a liquidus temperature of 346 ° C. Pb-5Ag has a solidus temperature of 304 ° C and a liquidus temperature of 365 ° C.

ところで、環境保護の観点から、最近では、はんだ付け技術全般において、Pb系はんだ合金に代えて、Pbフリーはんだ合金を用いることが求められている。当然、従来の半導体装置に使用されてきた前述のようなPb−Sn系高温はんだについても、Pbフリーはんだ合金の使用が求められている。   By the way, from the viewpoint of environmental protection, recently, in general soldering technology, it is required to use a Pb-free solder alloy instead of a Pb-based solder alloy. Naturally, the use of Pb-free solder alloys is also required for the Pb—Sn high-temperature solder as described above, which has been used in conventional semiconductor devices.

しかしながら、Pbフリーはんだ合金はこれまで種々提案されてきたが、Snが主成分であり、固相線温度が260℃以上の高温はんだ合金はなかった。例えば、固相線温度(共晶温度)が221℃のSn−Ag系はんだ合金において、Agを増やしていくと液相線温度は上がるが、固相線温度は上がらない。固相線温度227℃のSn−Sb系はんだ合金では、固相線温度を高くするために、Sbを極端に増やした場合、液相線温度も極端に上がってしまう。そして、これらに他の元素を添加しても、そのような特性を変えることはできない。したがって、従来から、Pbフリーはんだ合金では、300℃でも溶融しない、はんだとして使用可能なものはないと考えられている。   However, various Pb-free solder alloys have been proposed so far, but there has been no high-temperature solder alloy mainly composed of Sn and having a solidus temperature of 260 ° C. or higher. For example, in a Sn—Ag solder alloy having a solidus temperature (eutectic temperature) of 221 ° C., increasing Ag increases the liquidus temperature but does not raise the solidus temperature. In a Sn—Sb solder alloy having a solidus temperature of 227 ° C., when Sb is increased excessively in order to increase the solidus temperature, the liquidus temperature also rises extremely. And even if other elements are added to these, such characteristics cannot be changed. Therefore, conventionally, it is considered that there is no Pb-free solder alloy that does not melt even at 300 ° C. and can be used as solder.

そこで、高温はんだ合金を使用しない接合技術が検討されてきた。この高温はんだ合金を使用しない接合技術として検討されたのは、Snが主成分の鉛フリーはんだと比較して溶融温度の高い金属間化合物を用いて接合する方法である。その中でも特に、Snへの拡散が早く、比較的低温で金属間化合物が形成されるAgを用いたAgとSnの金属間化合物(Ag3Sn)で接合する方法が有望である。   Therefore, a joining technique that does not use a high-temperature solder alloy has been studied. As a joining technique that does not use this high-temperature solder alloy, a method of joining using an intermetallic compound having a higher melting temperature than lead-free solder containing Sn as a main component has been studied. Among them, a method of joining with an intermetallic compound of Ag and Sn (Ag3Sn) using Ag, which diffuses quickly into Sn and forms an intermetallic compound at a relatively low temperature, is promising.

例えば、特許文献1には、Pbフリーで温度階層接続の高温側のはんだ接続に用いることのできる複合はんだが記載されている。特許文献1の複合はんだは、Cuからなる金属網が2枚のはんだ箔によって挟まれて圧着された構成からなり、このように、金属網とはんだ箔とを重ねて圧延することにより、はんだ箔のSnが金属網の隙間に入り込み、加熱後はCuとSnの金属間化合物(Cu3Sn、Cu6Sn5)が形成され、高耐熱化が図れる事が示されている。また、特許文献1には、Cu以外にAg網も同様に有力候補であり、高融点の金属間化合物であるAg3Sn化合物では、280℃でも溶けない連結接続が可能となることが示されている。同様に硬く、かつ融点の低い合金系として、Cu−Sn系(例えばCu6Sn5)も、同様な対応が可能であると示されている。   For example, Patent Document 1 describes a composite solder that is Pb-free and can be used for solder connection on the high temperature side of the temperature hierarchy connection. The composite solder of Patent Document 1 has a configuration in which a metal mesh made of Cu is sandwiched between two solder foils and is crimped. Thus, by rolling and rolling the metal mesh and the solder foil, the solder foil is obtained. It has been shown that Sn enters a gap between metal meshes, and after heating, an intermetallic compound of Cu and Sn (Cu3Sn, Cu6Sn5) is formed, and high heat resistance can be achieved. Further, Patent Document 1 shows that Ag network is also a promising candidate in addition to Cu, and Ag3Sn compound, which is a high-melting intermetallic compound, can be connected without melting at 280 ° C. . Similarly, a Cu—Sn system (for example, Cu 6 Sn 5) as an alloy system that is similarly hard and has a low melting point is shown to be able to cope with the same problem.

他に、特許文献2には、チップ(半導体素子)とダイを接合するための接合シートが記載されている。特許文献2の接合シートは、溝加工のあるAgシートやAgワイヤを縦横に編んだメッシュ状シートであり、このAgシートの表面は厚さ0.3〜2.0μmのSnめっきが施され、加圧、加熱する事で、加熱時にAgシートのコアから次々に溶解や拡散によってAgが供給される。このため、特許文献2の接合シートは、最終的に形成されるAg−Sn層の融点を470℃以上に高めることができ、耐熱性の高い接合部とすることができ、また、溝空間のあるAgシートが柔らかくて熱歪みを吸収し、信頼性を向上させると示されている。   In addition, Patent Document 2 describes a bonding sheet for bonding a chip (semiconductor element) and a die. The joining sheet of Patent Document 2 is a mesh sheet in which grooved Ag sheets and Ag wires are knitted longitudinally and laterally, and the surface of the Ag sheet is subjected to Sn plating with a thickness of 0.3 to 2.0 μm, By pressurizing and heating, Ag is supplied one after another from the core of the Ag sheet by heating and dissolution. For this reason, the joining sheet of patent document 2 can raise melting | fusing point of the Ag-Sn layer finally formed to 470 degreeC or more, can be set as a joint part with high heat resistance, and groove | channel space. It has been shown that some Ag sheets are soft and absorb thermal strain, improving reliability.

特開2004−174522号公報(0024段〜0053段、0069段、図1、図8)JP 2004-174522 A (0024 to 0053 stages, 0069 stages, FIGS. 1 and 8) 特開2012−004594号公報(0058段〜0060段、図13、図14)JP 2012-004594 A (0058 to 0060 stages, FIGS. 13 and 14)

しかしながら、特許文献1の複合はんだにおいて、Ag網を使用した場合は、Snが溶融したときにAg網がある箇所のみ、AgがSnと拡散し、高融点のAg3Snが形成され、空間的に四方がこのAg3Snで囲まれてしまい、Snが溶融した際に、一部は空気を巻き込んで溶融するため、少なからずボイドが内部に存在することになる。また、Ag3Snが形成されるときに体積収縮が起こるため、ボイドを完全に無くすのは困難である。この溶融Sn中のボイドは四方が高融点のAg3Snで囲まれてしまうと、壁に囲まれたように動けなくなってしまうため、例え真空中で回路基板と半導体素子等とを接合していても、ボイドが抜けきらず、ボイドの多い接合部が形成されてしまう。特許文献2についても同様で、四方が高融点のAg3Snで囲まれてしまうと、ボイドが抜けるルートが確保されないため、ボイドが多く発生しやすい。   However, in the composite solder of Patent Document 1, when an Ag net is used, Ag diffuses with Sn only at a portion where the Ag net is present when Sn is melted to form Ag3Sn having a high melting point, spatially in four directions. Is surrounded by this Ag3Sn, and when Sn is melted, a part of it is melted by entraining air, so there are not a few voids inside. Moreover, since volume shrinkage occurs when Ag3Sn is formed, it is difficult to completely eliminate voids. If voids in this molten Sn are surrounded by Ag3Sn, which has a high melting point, it will not move as if surrounded by walls, so even if the circuit board is bonded to a semiconductor element or the like in a vacuum, , The voids are not completely removed, and a joined portion with many voids is formed. The same applies to Patent Document 2. If the four sides are surrounded by Ag3Sn having a high melting point, a route through which voids are not secured is likely to occur, and many voids are likely to occur.

この他、回路基板と半導体素子等との接合部に高融点の金属間化合物を形成するために、Ag網ではなく、Ag粒を微細に分散させる方法なども考えられるが、一旦Ag粒が均一に分布したとしても、溶融時には、Snが少なからず流動するため、Ag粒が移動し、接合部が不均一になりやすい。そうすると、接合部の一部はAg3Snが形成されるが、接合部の一部ではSnのみの箇所が出てしまい、接合部の耐熱性の確保が難しい。   In addition, in order to form an intermetallic compound having a high melting point at the junction between the circuit board and the semiconductor element, a method of finely dispersing Ag particles instead of an Ag net is conceivable. Even when distributed, Sn flows not a little at the time of melting, so the Ag grains move and the joint is likely to be non-uniform. If it does so, Ag3Sn will be formed in a part of junction part, but the location only of Sn will come out in a part of junction part, and it is difficult to ensure the heat resistance of a junction part.

本発明は、上記のような問題点を解決するためになされたものであり、接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物を形成することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to form a high-melting intermetallic compound with few voids at a joint where the objects to be joined are joined. .

本発明の半導体装置は、実装基板に形成された第1のAg層と、半導体素子に形成された第2のAg層との間に挟持された合金層を備え、合金層は第1のAg層及び第2のAg層のAg成分と、Snによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤが当該合金層の外周側から延伸して配置されたことを特徴とする。   A semiconductor device of the present invention includes an alloy layer sandwiched between a first Ag layer formed on a mounting substrate and a second Ag layer formed on a semiconductor element, and the alloy layer is a first Ag layer. The Ag component of the second layer and the second Ag layer, and an Ag3Sn intermetallic compound formed of Sn, wherein a plurality of wires containing Ag are arranged extending from the outer peripheral side of the alloy layer And

本発明の半導体装置によれば、Ag3Snの金属間化合物を有する合金層にAgを含んだ複数のワイヤが接続された構造を備えたので、合金層13が形成される際に少なからず発生するボイドが抜けるルートがワイヤ5間に確保されており、接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物を形成することができる。   According to the semiconductor device of the present invention, since a plurality of Ag-containing wires are connected to an alloy layer having an Ag3Sn intermetallic compound, a void is generated when the alloy layer 13 is formed. The route through which the wire is removed is ensured between the wires 5, and a high melting point intermetallic compound with few voids can be formed at the joint where the objects to be joined are joined.

本発明の実施の形態1による半導体装置の断面図及び上面図である。It is sectional drawing and the top view of the semiconductor device by Embodiment 1 of this invention. 本発明の合金層を説明する図である。It is a figure explaining the alloy layer of this invention. 金属間化合物Ag3Snの基本特性を示す図である。It is a figure which shows the basic characteristic of intermetallic compound Ag3Sn. 本発明の実施の形態1による半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device by Embodiment 1 of this invention. 本発明の実施の形態1による半導体素子とワイヤの位置を説明する図である。It is a figure explaining the position of the semiconductor element and wire by Embodiment 1 of this invention. 本発明の実施の形態1による半導体素子とワイヤの位置を説明する図である。It is a figure explaining the position of the semiconductor element and wire by Embodiment 1 of this invention. 比較例による半導体素子とワイヤの位置を説明する図である。It is a figure explaining the position of the semiconductor element and wire by a comparative example. 比較例による半導体素子とワイヤの位置を説明する図である。It is a figure explaining the position of the semiconductor element and wire by a comparative example. 本発明の実施例に示す代表的な接合部の断面イメージおよび組成分析結果を示す図である。It is a figure which shows the cross-sectional image and composition analysis result of the typical junction part shown in the Example of this invention. 本発明の実施例及び比較例の特性を示す図である。It is a figure which shows the characteristic of the Example and comparative example of this invention. 本発明の実施例及び比較例の特性を示す図である。It is a figure which shows the characteristic of the Example and comparative example of this invention. 本発明の金属間化合物Ag3Snにおける温度及び時間毎の厚さを示す図である。It is a figure which shows the temperature and the thickness for every time in intermetallic compound Ag3Sn of this invention. 本発明の実施の形態2によるワイヤの配置を示す図である。It is a figure which shows arrangement | positioning of the wire by Embodiment 2 of this invention. 本発明の実施の形態2による半導体素子とワイヤの位置を説明する図である。It is a figure explaining the position of the semiconductor element and wire by Embodiment 2 of this invention. 本発明の実施の形態2による半導体装置の断面図である。It is sectional drawing of the semiconductor device by Embodiment 2 of this invention.

実施の形態1.
図1は、本発明の実施の形態1による半導体装置の断面図及び上面図である。図1(a)は半導体装置の断面図であり、図1(b)は半導体装置の上面図である。半導体装置30は、シリコン(Si)やシリコンカーバイド(SiC)等のワイドバンドギャップ半導体材料を基材とした半導体素子9に形成されたAg層10と回路基板12に形成されたAg層4との間に狭持された合金層13を備えており、合金層13は、Ag層4、Ag層10のAg成分とSnによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤ5が合金層13の外周側から延伸して配置されている。半導体素子9を実装する実装基板である回路基板12は、DBC(Direct Bonded Cupper)基板であり、絶縁材2と、絶縁材2の上側に形成された上電極1と、絶縁材2の下側に形成された下電極3を備える。合金層13は、金属間化合物であり、例えばAg3Snである。合金層13を形成するために、回路基板12のAg層4に複数のワイヤ5が配置されたワイヤ構造体20が形成されている。複数のワイヤ5は、同一の方向に、合金層13の外周側から延伸して配置されている。ワイヤ構造体20は、半導体素子9のX方向の幅c1、Z方向の幅c2よりも広い範囲に形成される。ワイヤ構造体20のX方向の幅b3、Z方向の幅b2である。図1(b)では、複数のワイヤ5のうち、7本のワイヤ5a、5b、5c、5d、5e、5f、5gを明示的に記載した。複数のワイヤ5を配置するピッチは、b1である。なお、ワイヤの符号は、総括的に5を用い、区別して説明する場合に5a乃至5gを用いる。
Embodiment 1 FIG.
FIG. 1 is a sectional view and a top view of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view of a semiconductor device, and FIG. 1B is a top view of the semiconductor device. The semiconductor device 30 includes an Ag layer 10 formed on a semiconductor element 9 based on a wide band gap semiconductor material such as silicon (Si) or silicon carbide (SiC), and an Ag layer 4 formed on a circuit board 12. The alloy layer 13 includes an Ag layer 4 and an Ag 3 Sn intermetallic compound formed by the Ag component of the Ag layer 4 and the Ag layer 10 and Sn, and a plurality of Ag-containing compounds. The wire 5 is arranged extending from the outer peripheral side of the alloy layer 13. A circuit board 12 which is a mounting board on which the semiconductor element 9 is mounted is a DBC (Direct Bonded Copper) board, and includes an insulating material 2, an upper electrode 1 formed on the upper side of the insulating material 2, and a lower side of the insulating material 2. The lower electrode 3 is formed. The alloy layer 13 is an intermetallic compound, for example, Ag3Sn. In order to form the alloy layer 13, a wire structure 20 in which a plurality of wires 5 are arranged on the Ag layer 4 of the circuit board 12 is formed. The plurality of wires 5 are arranged extending from the outer peripheral side of the alloy layer 13 in the same direction. The wire structure 20 is formed in a range wider than the width c1 in the X direction and the width c2 in the Z direction of the semiconductor element 9. The wire structure 20 has a width b3 in the X direction and a width b2 in the Z direction. In FIG. 1B, seven wires 5 a, 5 b, 5 c, 5 d, 5 e, 5 f, and 5 g among the plurality of wires 5 are explicitly described. The pitch at which the plurality of wires 5 are arranged is b1. In addition, the code | symbol of a wire uses 5 generally, and uses 5a thru | or 5g in the case of distinguishing and explaining.

ワイヤ構造体20を構成する各ワイヤ5は、図1(a)、図1(b)における左側に屈曲部11を設けている。ワイヤ5は、半導体素子9の搭載位置から左外側に長さa2だけ離した位置にボールボンド6が形成され、半導体素子9の搭載位置から右外側に長さa3だけ離した位置にステッチボンド7が形成される。なお、屈曲部11は任意の高さが可能だが、この屈曲部11が最終的にループしたときに一番高い位置になる。長さa1は、半導体素子9のX方向の幅c1に長さa2及び長さa3を加えた長さである。ボールボンド6はワイヤ5のワイヤ径よりも大ききなり、ボールボンド6の左外側の端からステッチボンド7の右外側の端までの長さはb3である。   Each wire 5 constituting the wire structure 20 is provided with a bent portion 11 on the left side in FIGS. 1 (a) and 1 (b). The wire 5 is formed with a ball bond 6 at a position separated from the mounting position of the semiconductor element 9 by a length a2 on the left outer side, and a stitch bond 7 at a position separated from the mounting position of the semiconductor element 9 by a length a3 on the right outer side. Is formed. The bent portion 11 can have an arbitrary height, but is the highest position when the bent portion 11 finally loops. The length a1 is a length obtained by adding the length a2 and the length a3 to the width c1 of the semiconductor element 9 in the X direction. The ball bond 6 is larger than the wire diameter of the wire 5, and the length from the left outer end of the ball bond 6 to the right outer end of the stitch bond 7 is b3.

次に、半導体素子9と回路基板12とを接合する接合部に合金層13を形成するにあたり、本発明の接合方法だと、合金層13において金属間化合物Ag3Snが形成され、かつSnが残存しないことを理論的に証明する。接合部の内部にSnが残存しないようにするには、形成条件の最適値があるにもかかわらず、特許文献1、2にはAg3Snが形成されるとだけしか示されておらず、接合部の内部にSnが残存しないことが、理論的に証明されていない。すなわち、特許文献1、2で示されている数値限定の範囲では、Snが残存していないことを証明する根拠が不足している。   Next, when forming the alloy layer 13 at the joint where the semiconductor element 9 and the circuit board 12 are joined, the intermetallic compound Ag3Sn is formed in the alloy layer 13 and no Sn remains in the joining method of the present invention. Prove that theoretically. In order to prevent Sn from remaining inside the joint, Patent Documents 1 and 2 only show that Ag3Sn is formed in spite of the optimum value of the formation conditions. It has not been theoretically proved that Sn does not remain in the interior of the substrate. That is, in the range of numerical limitation shown in Patent Documents 1 and 2, there is a lack of evidence to prove that Sn does not remain.

図2は本発明の合金層を説明する図であり、図3は金属間化合物Ag3Snの基本特性を示す図である。最初にAg、Sn、Ag3Snの基本的な物性について図3を用いて説明する。図3において、Ag列はAg3SnのAgにおける数値であり、Sn列はAg3SnのSnにおける数値であり、合計列はAg3Snにおける数値である。Ag3Snは、AgとSnとの構成比が原子%(at%)で3:1であるので、Ag75at%:Sn25at%となる。これを、質量%(wt%)にするため、Agの原子量を108g/mol、Snの原子量を119g/molとして計算すると、Ag73wt%:Sn27wt%となる。さらに、これを、体積%(vol%)にするため、Agの密度を10.5g/cm3、Snの密度を7.4g/cm3として計算すると、Ag66vol%:Sn34vol%となる。つまり、Agの周りにSnが無限にあっても、Ag3Snになるのは、Agの体積の約半分(34/66=0.52≒0.5)で、それ以上のSnは拡散しないで残ってしまう。別の見方をすると、AgがAg3Snになると、Agの体積の約0.5倍しか増大しない(すなわち、約1.5倍になる)という事になる。   FIG. 2 is a diagram illustrating the alloy layer of the present invention, and FIG. 3 is a diagram illustrating the basic characteristics of the intermetallic compound Ag3Sn. First, basic physical properties of Ag, Sn, and Ag3Sn will be described with reference to FIG. In FIG. 3, the Ag column is a numerical value in Ag of Ag3Sn, the Sn column is a numerical value in Sn of Ag3Sn, and the total column is a numerical value in Ag3Sn. Since Ag3Sn has a composition ratio of Ag and Sn of 3: 1 in atomic% (at%), it becomes Ag75at%: Sn25at%. In order to make this mass% (wt%), when the atomic weight of Ag is 108 g / mol and the atomic weight of Sn is 119 g / mol, it is Ag73 wt%: Sn27 wt%. Furthermore, in order to make this into volume% (vol%), when calculating the density of Ag as 10.5 g / cm3 and the density of Sn as 7.4 g / cm3, it becomes Ag66vol%: Sn34vol%. In other words, even if Sn is infinite around Ag, Ag3Sn is about half of the volume of Ag (34/66 = 0.52≈0.5), and Sn beyond that remains undiffused. End up. From another point of view, when Ag becomes Ag3Sn, it increases only about 0.5 times the volume of Ag (ie, about 1.5 times).

本発明の半導体素子9と回路基板12とを接合する接合部における簡略的なモデルを用いて、接合部の内部にSnが残存しないことを説明する。Agからなるワイヤ(適宜、Agワイヤと称する)5c、5dがSn層8の内部に配置され、このSn層8の上側にAg層10が配置され、Sn層8の下側にAg層4が配置されている。このモデルは、本発明の被接合材(半導体素子9、上電極1)にAgめっきを施し、Agワイヤが面内に一方向のみに張られていると共に、はんだ溶融時に流れないようにボンディングされており、その上からSnを溶融させて、Ag3Sn(融点470℃程度)を形成する構成を、簡略的に表している。ワイヤ直径xのAgワイヤ5c、5dが内包されたSn層8の上下に厚さzのAg層10、4があり、Agワイヤ5c、5dがあるピッチyの間隔で並んでいる。図2における点aは、Agワイヤ5cの円とAg層10との接点であり、点cは、Agワイヤ5cの円とAg層4との接点である。図2における点bは、Agワイヤ5dの円とAg層10との接点であり、点dは、Agワイヤ5dの円とAg層4との接点である。   It will be described that Sn does not remain inside the joint using a simple model at the joint where the semiconductor element 9 and the circuit board 12 of the present invention are joined. Ag wires (referred to as Ag wires as appropriate) 5c and 5d are disposed inside the Sn layer 8, an Ag layer 10 is disposed above the Sn layer 8, and an Ag layer 4 is disposed below the Sn layer 8. Has been placed. In this model, the material to be joined (semiconductor element 9, upper electrode 1) of the present invention is subjected to Ag plating, and the Ag wire is stretched in only one direction in the surface and bonded so that it does not flow when the solder is melted. The structure in which Sn is melted from above to form Ag3Sn (melting point of about 470 ° C.) is simply shown. There are Ag layers 10 and 4 having a thickness z above and below the Sn layer 8 in which the Ag wires 5c and 5d having the wire diameter x are included, and the Ag wires 5c and 5d are arranged at a pitch y interval. A point a in FIG. 2 is a contact point between the circle of the Ag wire 5 c and the Ag layer 10, and a point c is a contact point between the circle of the Ag wire 5 c and the Ag layer 4. A point b in FIG. 2 is a contact point between the circle of the Ag wire 5 d and the Ag layer 10, and a point d is a contact point between the circle of the Ag wire 5 d and the Ag layer 4.

Agワイヤ5のピッチは、ワイヤボンド装置によって、ある程度制限されてしまい、ワイヤ径x(ワイヤ直径x)に対し、ピッチyはy=2.5x程度が限界である。ピッチyの装置上の限界値を式(1)とする。ピッチyは、式(2)の条件が必要である。これ以上ピッチを狭くすると、ワイヤボンド装置が隣接したワイヤに接触してしまう。例えば、φ12μmのAgワイヤであれば、ピッチ30μm、φ20μmであれば、ピッチ50μmである。
y=2.5x ・・・(1)
y≧2.5x ・・・(2)
The pitch of the Ag wire 5 is limited to some extent by the wire bonding apparatus, and the limit of the pitch y to the wire diameter x (wire diameter x) is about y = 2.5x. The limit value on the device for the pitch y is defined as equation (1). The pitch y needs the condition of the formula (2). If the pitch is further narrowed, the wire bonding apparatus comes into contact with adjacent wires. For example, if the wire is φ12 μm, the pitch is 30 μm, and if it is φ20 μm, the pitch is 50 μm.
y = 2.5x (1)
y ≧ 2.5x (2)

図2のように、点a、b、c、dで囲まれたSn層8の内部における領域A1に周辺のAgが拡散して、Ag3Snが形成される必要がある。上述のとおり、AgがSn層8に移動してAg3Snになると、Agの体積の約0.5倍しか増大しないという結果を考慮すると、Ag3Snにできる限界値は、以下の関係式が成り立つ。
Agの供給量×0.5≧abcdで囲まれた領域A1 ・・・(3)
As shown in FIG. 2, Ag3Sn needs to be formed by diffusing the surrounding Ag into the region A1 inside the Sn layer 8 surrounded by the points a, b, c, and d. As described above, when Ag moves to the Sn layer 8 and becomes Ag3Sn, considering the result that the volume of Ag increases only about 0.5 times, the limit value that can be made Ag3Sn has the following relational expression.
Ag supply amount × 0.5 ≧ area A1 surrounded by abcd (3)

この関係式(3)を、図2の断面において具体的に当てはめた計算式は、以下のように表せる。
0.5×(2yz+π(x/2))≧(xy−π(x/2)
・・・(4)
ここで、左辺における2yzは領域A2と領域A3の合計面積であり、左辺におけるπ(x/2)は半円領域A4と半円領域A5の合計面積である。右辺は領域A1の面積である。
A calculation formula in which this relational expression (3) is specifically applied to the cross section of FIG. 2 can be expressed as follows.
0.5 × (2yz + π (x / 2) 2 ) ≧ (xy−π (x / 2) 2 )
... (4)
Here, 2yz on the left side is the total area of the region A2 and the region A3, and π (x / 2) 2 on the left side is the total area of the semicircular region A4 and the semicircular region A5. The right side is the area of the region A1.

式(4)を変形すると、式(5)を経て式(6)になる。
yz+1/8πx ≧ xy−2/8πx ・・・(5)
yz+3/8πx ≧ xy ・・・(6)
When formula (4) is transformed, formula (6) is obtained via formula (5).
yz + 1 / 8πx 2 ≥ xy-2 / 8πx 2 (5)
yz + 3 / 8πx 2 ≧ xy (6)

ここで、上述のピッチyの装置上の限界値を示す式(1)を式(6)に適用すると、式(7)〜(10)を経て式(11)になる。
2.5xz+3/8πx ≧ 2.5x ・・・(7)
2.5z+3/8πx ≧ 2.5x ・・・(8)
2.5z ≧ (2.5−3/8π)x ・・・(9)
z ≧ ((2.5−3/8π)/2.5)x ・・・(10)
z ≧ 0.53x ・・・(11)
Here, when Expression (1) indicating the limit value on the device of the pitch y is applied to Expression (6), Expression (11) is obtained through Expressions (7) to (10).
2.5xz + 3 / 8πx 2 ≧ 2.5x 2 (7)
2.5z + 3 / 8πx ≧ 2.5x (8)
2.5z ≧ (2.5−3 / 8π) x (9)
z ≧ ((2.5−3 / 8π) /2.5) x (10)
z ≧ 0.53x (11)

式(11)に上述のピッチyの装置上の限界値を示す式(1)を適用すると、式(12)となる。
z≧0.21y ・・・(12)
When Expression (1) indicating the limit value of the above-described pitch y on the apparatus is applied to Expression (11), Expression (12) is obtained.
z ≧ 0.21y (12)

以上の結果をまとめると、Agワイヤ直径x、ピッチy、Ag層の厚さzには以下の3式が成り立つ。
y≧2.5x ・・・(2)
z≧0.53x ・・・(11)
z≧0.21y ・・・(12)
Summarizing the above results, the following three formulas are established for the Ag wire diameter x, the pitch y, and the thickness z of the Ag layer.
y ≧ 2.5x (2)
z ≧ 0.53x (11)
z ≧ 0.21y (12)

更に、必要なSnの量も計算できる。Snの供給方法として箔状のSn層8から供給することを考えると、Sn層8の必要な厚さtは以下のように計算される。
t≒(xy−π(x/2))/y ・・・(13)
式(13)に式(1)を適用して、yまたはxを消去すると、式(14)、式(15)のようになる。
t≒0.68x ・・・(14)
t≒0.27y ・・・(15)
In addition, the amount of Sn required can be calculated. Considering the supply method of Sn from the foil-like Sn layer 8, the required thickness t of the Sn layer 8 is calculated as follows.
t≈ (xy−π (x / 2) 2 ) / y (13)
Applying equation (1) to equation (13) and eliminating y or x results in equations (14) and (15).
t≈0.68x (14)
t≈0.27y (15)

実際には、Snは、外へ濡れ広がるので、上記式(14)、式(15)よりもやや厚めに供給する必要がある。   Actually, Sn spreads out to the outside, so it is necessary to supply it slightly thicker than the above formulas (14) and (15).

上記の結果をもとに、Agワイヤ径x、ピッチy、Sn層の厚さzを変えたサンプルを作製した。具体的なサンプル作製方法を、図1、図4を用いて説明する。   Based on the above results, samples with different Ag wire diameter x, pitch y, and Sn layer thickness z were prepared. A specific sample manufacturing method will be described with reference to FIGS.

まず、回路基板12として、市販の大きさ30mm×30mm、厚さ1.12mmのDBC基板を用意する。Cuからなる上電極1、Si3N4からなる絶縁材2、Cuからなる下電極3の厚さは、それぞれ0.4mm、0.32mm、0.4mmである。回路基板12へのAg層4としてAgめっきを6.5μm施した。DBC基板は、例えば電気化学工業株式会社から購入する事ができる。Agめっきは、例えば、株式会社太洋工作所で実施する事ができる。次に、Sn層8として、市販の大きさ100mm×100mm、厚さ9μmの純度99.5wt%のSn箔を用意した。Sn箔は、例えば福田金属箔粉工業株式会社から購入することができる。次に、半導体素子9として、大きさ7mm×7mm、厚さ0.25mmのSiC素子を用意する。SiC素子の裏面に、6.5μmのAgがメタライズされ、Ag層10が形成されている。このようなSiC素子は、例えば新日鉄住金株式会社から購入することが可能である。   First, as the circuit board 12, a commercially available DBC board having a size of 30 mm × 30 mm and a thickness of 1.12 mm is prepared. The thicknesses of the upper electrode 1 made of Cu, the insulating material 2 made of Si3N4, and the lower electrode 3 made of Cu are 0.4 mm, 0.32 mm, and 0.4 mm, respectively. As the Ag layer 4 on the circuit board 12, 6.5 μm of Ag plating was applied. The DBC substrate can be purchased from, for example, Electrochemical Industry Co., Ltd. Ag plating can be carried out, for example, at Taiyo Corporation. Next, as the Sn layer 8, a commercially available Sn foil having a size of 100 mm × 100 mm and a thickness of 9 μm and a purity of 99.5 wt% was prepared. Sn foil can be purchased from, for example, Fukuda Metal Foil Powder Co., Ltd. Next, a SiC element having a size of 7 mm × 7 mm and a thickness of 0.25 mm is prepared as the semiconductor element 9. On the back surface of the SiC element, 6.5 μm of Ag is metalized to form an Ag layer 10. Such a SiC element can be purchased from, for example, Nippon Steel & Sumikin Co., Ltd.

次に、φ12μm、長さ100m巻きの純度99.99wt%のAgのワイヤ5を用意した。Agワイヤは、例えば野毛電気工業から購入する事ができる。このAgワイヤを市販のワイヤボンダで上記の回路基板12上のAg層4にボンディングした。ワイヤボンダは、例えば、株式会社カイジョー製FB−910、株式会社新川製UTC−5000である。   Next, an Ag wire 5 having a purity of 99.99 wt% and having a diameter of 12 μm and a length of 100 m was prepared. Ag wire can be purchased from Noge Electric Industry, for example. The Ag wire was bonded to the Ag layer 4 on the circuit board 12 with a commercially available wire bonder. The wire bonder is, for example, FB-910 manufactured by Kaijo Co., Ltd. or UTC-5000 manufactured by Shinkawa Co., Ltd.

ワイヤボンディング(ワイヤ接続工程)について、詳細を説明する。最初に、ワイヤ5の先端に水素5%の窒素ガスを吹き付けて、放電でワイヤ径の1.5〜1.8倍程度で安定的に真球のボールが形成できる放電条件(放電電流、時間、ガス吹き付け量)でボールを作製し、回路基板12上のAg層4に超音波と、圧力をかけて、半導体素子9の搭載位置からa2=2mm外側に離した位置にボールボンド6を行う。このとき、真球が安定的に形成されず、偏芯を起こしてしまうと、ボンディングしたときに、圧力が均一に加わらないため、きちんとボンディングされないので、注意が必要である。また、偏芯している場合は、狙った位置にボンディングができず、ピッチが安定しないので、注意が必要である。   Details of wire bonding (wire connection process) will be described. First, a 5% hydrogen nitrogen gas is blown onto the tip of the wire 5, and discharge conditions (discharge current and time) that can stably form a true spherical ball at about 1.5 to 1.8 times the wire diameter by discharge. The ball bond 6 is produced at a position a2 = 2 mm away from the mounting position of the semiconductor element 9 by applying ultrasonic waves and pressure to the Ag layer 4 on the circuit board 12. . At this time, if the true sphere is not stably formed and the eccentricity occurs, the pressure is not uniformly applied when bonding is performed, so that the bonding is not performed properly. In addition, if it is eccentric, bonding cannot be performed at the target position and the pitch is not stable, so care must be taken.

次に、ワイヤ5を、屈曲部11を設けて、半導体素子9の素子サイズc1=7mmよりも長い、長さa1=10mmまで張って、超音波と、圧力をかけて、半導体素子9の素子搭載位置からa3=1mm離した位置にステッチボンド7をする。なお、屈曲部11は任意の高さが可能だが、この屈曲部11が最終的にループしたときに一番高い位置になるため、ループ高さd1を市販の装置では限界の50μmになるように調整する。また、素子搭載位置でのループ高さd2がd1の80%以下になるように調整する。このようにしたのは、素子搭載位置内に最大ループ高さの部分があると、この後の接合時に圧力をかけたときに、図7、図8のように、ワイヤ16が重なりながら、押し潰されるため、好ましくないからである。図7及び図8は、比較例による半導体素子とワイヤの位置を説明する図である。図7は半導体素子9がワイヤ16に接触する前の状態を示し、図8は半導体素子9がワイヤ16を押圧した状態を示している。   Next, the wire 5 is provided with a bent portion 11 and stretched to a length a1 = 10 mm which is longer than the element size c1 = 7 mm of the semiconductor element 9, and ultrasonic waves and pressure are applied to the element of the semiconductor element 9 A stitch bond 7 is made at a position a3 = 1 mm away from the mounting position. The bent portion 11 can have an arbitrary height, but when the bent portion 11 finally loops, it becomes the highest position, so that the loop height d1 is set to 50 μm, which is the limit in a commercially available device. adjust. Further, the loop height d2 at the element mounting position is adjusted to be 80% or less of d1. This is because, when there is a portion of the maximum loop height in the element mounting position, when pressure is applied during subsequent joining, the wire 16 is pushed while being overlapped as shown in FIGS. It is because it is crushed and is not preferable. 7 and 8 are diagrams for explaining the positions of semiconductor elements and wires according to a comparative example. FIG. 7 shows a state before the semiconductor element 9 contacts the wire 16, and FIG. 8 shows a state where the semiconductor element 9 presses the wire 16.

ワイヤが重ならないようにするには、最大ループ高さの部分を避けて、少なくとも最大ループ高さの80%下がった箇所であれば、図5、図6のように抑制できる事が実験的に確認された。図5及び図6は、本発明の実施の形態1による半導体素子とワイヤの位置を説明する図である。図5は半導体素子9がワイヤ5に接触する前の状態を示し、図6は半導体素子9がワイヤ5を押圧した状態を示している。   In order to prevent the wires from overlapping, it is experimentally possible to avoid the portion of the maximum loop height and to suppress it as shown in FIGS. 5 and 6 if it is at least 80% lower than the maximum loop height. confirmed. 5 and 6 are diagrams for explaining the positions of the semiconductor element and the wire according to the first embodiment of the present invention. FIG. 5 shows a state before the semiconductor element 9 contacts the wire 5, and FIG. 6 shows a state where the semiconductor element 9 presses the wire 5.

以上のワイヤ接続工程をピッチb1=30μmでY方向に素子サイズc2よりも長いb2の範囲まで繰り返し行う。すると、回路基板12上のAg層4上に半導体素子9の素子サイズ(チップ接合領域15)よりも広い領域(a1、b2の範囲)にAgワイヤが張り巡らされ、ワイヤ構造体20が形成できる(ワイヤ構造体形成工程)。回路基板12上のAg層4上にワイヤ構造体20が形成された構造体を、ワイヤ付回路基板21と呼ぶことにする。チップ接合領域15は、半導体素子9の実装面の面積と等しい領域である。   The above wire connection process is repeated at a pitch b1 = 30 μm to a range of b2 longer than the element size c2 in the Y direction. Then, an Ag wire is stretched over a region (a1, b2 range) wider than the element size (chip bonding region 15) of the semiconductor element 9 on the Ag layer 4 on the circuit board 12, and the wire structure 20 can be formed. (Wire structure formation process). A structure in which the wire structure 20 is formed on the Ag layer 4 on the circuit board 12 will be referred to as a circuit board with wire 21. The chip bonding area 15 is an area equal to the area of the mounting surface of the semiconductor element 9.

次に、Agのワイヤ5が張り巡らされたワイヤ付回路基板21におけるワイヤ5の最大ループ高さd1の80%以下の箇所に、Sn層8と、Ag層10が形成された半導体素子9とを順次載せた(半導体素子搭載工程)。その製造中間体をギ酸還元雰囲気中で、180℃、10分の熱処理を行い、各部材表面の酸化膜を除去した。次に真空引きをおこない、簡易的な加圧治具を用いて、1MPaで加圧を加えならが、300℃、10分の熱処理を行った(合金層形成工程)。   Next, the semiconductor element 9 in which the Sn layer 8 and the Ag layer 10 are formed at a position of 80% or less of the maximum loop height d1 of the wire 5 in the circuit board with wire 21 on which the Ag wire 5 is stretched. (Semiconductor element mounting process). The production intermediate was heat-treated at 180 ° C. for 10 minutes in a formic acid reducing atmosphere to remove the oxide film on the surface of each member. Next, vacuuming was performed, and a heat treatment was performed at 300 ° C. for 10 minutes (alloy layer forming step) while applying pressure at 1 MPa using a simple pressure jig.

加圧について、説明する。今回の場合、1MPaの圧力を加える。半導体素子9のサイズが7mm×7mmなので、接合面積が49mm2であり、ここに、1MPaつまり、49Nの荷重を加えるには、4.9kgf≒5kgの荷重を加えれば良い。この程度の荷重であれば、プレス機など大掛かりな装置は必要なく、ストッパーの付いたばね付の簡易治具で容易に実行が可能である。なお、例えば、ばねの設計、購入は東海バネ工業から可能である。そのばねを用いた加圧治具は、例えば岸田エンジニアリングで作製が可能である。   The pressurization will be described. In this case, a pressure of 1 MPa is applied. Since the size of the semiconductor element 9 is 7 mm × 7 mm, the bonding area is 49 mm 2. To apply a load of 1 MPa, that is, 49 N, a load of 4.9 kgf≈5 kg may be applied. With such a load, a large-scale device such as a press machine is not necessary, and it can be easily executed with a simple jig with a spring with a stopper. For example, the design and purchase of a spring can be made from Tokai Spring Industry. The pressurizing jig using the spring can be manufactured by, for example, Kishida Engineering.

次に接合が終了した製造中間体を冷却して、この製造中間体を取り出し、接合部断面を走査型電子顕微鏡(Scanning Electron Microscope、SEM)で観察した。その結果、接合部がAgおよびAg3Snのみで形成されており、Sn単独相がない事を確認した。代表的な接合部の断面イメージおよび組成分析結果を図9に示す。図9において、接合部の断面イメージ41、Ag元素分布42、Sn元素分布43を示した。接合部の断面イメージ41は、合金層13を含む接合部の断面SEMイメージにおける半導体素子9、合金層13、上電極1の境界を明確にしたものである。スケール45は、10μmの長さを示している。符号L1、L2、L3、L4は、Ag元素またはSn元素における4段階の検出レベル領域を示しており、検出量の少ない領域から多い領域の順番にL1〜L4になっている。Ag元素分布42において、L4領域はAg単独相であり、L3領域はAg3Snが形成されたAg3Sn相である。Ag単独相は、Sn元素分布43において、Sn元素が検出されないL1領域に該当する。Ag3Sn相は、Sn元素分布43において、L2領域に該当する。なお、Ag元素分布42において、上下のL1領域とL4領域の隙間に薄くL3領域が存在したが、図が複雑にならないように省略した。また、接合部を透過X線装置で観察し、透過X線画像を2値化して、ボイド率を算出したところ、目標のボイド率10%以下に対し、ボイド率は4%と良好であった。このように製造されたサンプルを実施例1とする。   Next, the production intermediate after joining was cooled, the production intermediate was taken out, and the cross section of the junction was observed with a scanning electron microscope (SEM). As a result, it was confirmed that the junction was formed only of Ag and Ag3Sn and there was no Sn single phase. FIG. 9 shows a cross-sectional image and a composition analysis result of a typical joint. In FIG. 9, a cross-sectional image 41, an Ag element distribution 42, and a Sn element distribution 43 of the joint are shown. The cross-sectional image 41 of the joint portion clarifies the boundaries of the semiconductor element 9, the alloy layer 13, and the upper electrode 1 in the cross-sectional SEM image of the joint portion including the alloy layer 13. The scale 45 has a length of 10 μm. Reference numerals L1, L2, L3, and L4 indicate four-level detection level regions in the Ag element or the Sn element, and are L1 to L4 in order from the region with the smallest detection amount to the region with the largest detection amount. In the Ag element distribution 42, the L4 region is an Ag single phase, and the L3 region is an Ag3Sn phase in which Ag3Sn is formed. The Ag single phase corresponds to the L1 region in which Sn element is not detected in the Sn element distribution 43. The Ag3Sn phase corresponds to the L2 region in the Sn element distribution 43. In the Ag element distribution 42, there is a thin L3 region in the gap between the upper and lower L1 regions and the L4 region, but this is omitted so as not to complicate the figure. Further, the joint portion was observed with a transmission X-ray apparatus, the transmission X-ray image was binarized, and the void ratio was calculated. The void ratio was as good as 4% against the target void ratio of 10% or less. . The sample thus manufactured is referred to as Example 1.

次に、上記と同じプロセスで、図10に示すように、Agのワイヤ5のワイヤ径(ワイヤ直径)xを12〜50μm、ピッチyを変更したサンプルを9個製造した。それぞれのサンプルを実施例2〜10とする。図10は、本発明の実施例及び比較例の特性を示す図である。実施例2〜10は、各ワイヤ径に対し、ピッチyが、式(1)から計算された2.5xとし、半導体素子9のAg層10、ワイヤ付回路基板21のAg層4が式(11)、(12)から計算された範囲内の厚さzとしたものである。実施例2〜10について、SEMで合金形成状態を観察し、透過X線画像からボイド率を算出した。その結果、図10に示すように、実施例2〜10は、合金形成状態は良好であり、ボイド率は4%以下であり、良好だった。   Next, as shown in FIG. 10, nine samples were manufactured by changing the wire diameter (wire diameter) x of the Ag wire 5 to 12 to 50 μm and the pitch y as shown in FIG. Each sample is referred to as Examples 2-10. FIG. 10 is a diagram showing the characteristics of Examples and Comparative Examples of the present invention. In Examples 2 to 10, for each wire diameter, the pitch y is 2.5x calculated from Equation (1), and the Ag layer 10 of the semiconductor element 9 and the Ag layer 4 of the circuit board 21 with wire are represented by the formula ( 11) and thickness z within the range calculated from (12). About Examples 2-10, the alloy formation state was observed with SEM and the void ratio was computed from the transmission X-ray image. As a result, as shown in FIG. 10, in Examples 2 to 10, the alloy formation state was good, and the void ratio was 4% or less, which was good.

図10には、各サンプルの製造条件と、検査結果である合金形成状態とボイド率が記載されている。ワイヤ引張方向は、1方向か2方向以上の多方向かを示している。必要めっき厚は、式(11)及び式(12)を満たすAg層4、10の厚さzである。実施のめっき厚zは、各サンプルのAg層4、10の厚さである。理論式の適合は、理論式である式(2)、式(11)、式(12)を満たす(OK表示)か否か(NG表示)を示している。必要Sn箔厚は、式(14)及び式(15)を満たすSn層8の厚さtである。実際のSn箔厚tは、各サンプルのSn層8の厚さである。合金形成は、接合部の合金層13が良好か否を示している。合金形成が良好な場合は、OKの表示をし、接合部がAgおよびAg3Snのみで形成されており、Sn単独相がない事を示している。合金形成が不良な場合は、NGの表示をしている。   FIG. 10 shows the manufacturing conditions of each sample, the alloy formation state and the void ratio, which are inspection results. The wire pulling direction indicates one direction or multiple directions including two or more directions. The required plating thickness is the thickness z of the Ag layers 4 and 10 that satisfy the expressions (11) and (12). The actual plating thickness z is the thickness of the Ag layers 4 and 10 of each sample. The conformity of the theoretical formula indicates whether the theoretical formulas (2), (11), and (12) are satisfied (OK display) or not (NG display). The necessary Sn foil thickness is the thickness t of the Sn layer 8 that satisfies the expressions (14) and (15). The actual Sn foil thickness t is the thickness of the Sn layer 8 of each sample. The alloy formation indicates whether or not the alloy layer 13 at the joint is good. When the alloy formation is good, OK is indicated, indicating that the joint is formed of only Ag and Ag3Sn and there is no Sn single phase. When the alloy formation is poor, NG is displayed.

図10の実施例1〜10に示したように、Sn層8の厚さが必要厚以上あり、かつ式(2)、式(11)、式(12)で示された条件を満たすことで、合金形成状態、ボイド率は全て良好であった。   As shown in Examples 1 to 10 in FIG. 10, the thickness of the Sn layer 8 is equal to or greater than the necessary thickness, and satisfying the conditions represented by the expressions (2), (11), and (12) The alloy formation state and void ratio were all good.

次に、図10に示した比較例1〜4について説明する。上記と同じプロセスで、Agのワイヤ5のワイヤ径xを12〜50μm、ピッチyを式(1)から計算された30〜125μmとしたサンプルを4個製造した。比較例1〜4は、各ワイヤ径に対し、ピッチyが、式(1)から計算された2.5xとし、半導体素子9のAg層10、ワイヤ付回路基板21のAg層4が式(11)、(12)から計算された範囲から外れた厚さzとしたものである。比較例1〜4について、SEMで合金形成状態を観察し、透過X線画像からボイド率を算出した。その結果、図10に示すように、比較例1〜4は、ボイド率は目標の10%以下と良好であったが、合金形成状態は、一部にSn単独相が残存していたため、不良(NG)であった。   Next, Comparative Examples 1 to 4 shown in FIG. 10 will be described. In the same process as described above, four samples were manufactured in which the wire diameter x of the Ag wire 5 was 12 to 50 μm and the pitch y was 30 to 125 μm calculated from the formula (1). In Comparative Examples 1 to 4, for each wire diameter, the pitch y is 2.5x calculated from Equation (1), and the Ag layer 10 of the semiconductor element 9 and the Ag layer 4 of the circuit board 21 with wire are 11) and thickness z deviating from the range calculated from (12). About Comparative Examples 1-4, the alloy formation state was observed by SEM and the void ratio was computed from the transmission X-ray image. As a result, as shown in FIG. 10, in Comparative Examples 1 to 4, the void ratio was as good as 10% or less of the target, but the alloy formation state was poor because the Sn single phase remained in part. (NG).

次に、図11に示す実施例11〜14について説明する。図11は、本発明の実施例及び比較例の特性を示す図である。上記と同じプロセスで、Agのワイヤ5のワイヤ径xが12〜50μm、ピッチyが式(2)を満たす40〜140μmとしたサンプルを4個製造した。実施例11〜14は、各ワイヤ径に対し、ピッチyが、式(2)を満たす2.5xより大きな値とし、半導体素子9のAg層10、ワイヤ付回路基板21のAg層4が式(11)、(12)から計算された範囲内の厚さzとしたものである。実施例11〜14について、SEMで合金形成状態を観察し、透過X線画像からボイド率を算出した。その結果、図11に示すように、実施例11〜14は、合金形成状態は良好であり、ボイド率は4%以下であり、良好だった。   Next, Examples 11 to 14 shown in FIG. 11 will be described. FIG. 11 is a diagram showing the characteristics of the examples and comparative examples of the present invention. In the same process as described above, four samples were manufactured in which the wire diameter x of the Ag wire 5 was 12 to 50 μm and the pitch y was 40 to 140 μm satisfying the formula (2). In Examples 11 to 14, for each wire diameter, the pitch y is set to a value larger than 2.5x satisfying the formula (2), and the Ag layer 10 of the semiconductor element 9 and the Ag layer 4 of the circuit board 21 with wire are formulas. The thickness z is within the range calculated from (11) and (12). About Examples 11-14, the alloy formation state was observed with SEM, and the void ratio was computed from the transmission X-ray image. As a result, as shown in FIG. 11, in Examples 11 to 14, the alloy formation state was good, and the void ratio was 4% or less, which was good.

次に、特許文献1、2に相当する比較例5、6について説明する。これまで本発明の特徴である一方向にAgのワイヤ5を張った状態で評価してきたが、今度は、2方向(X方向、Y方向)にAgのワイヤ5を張ったサンプルを作製した。まず、上記と同じプロセスで、実施例7と同じワイヤ径xを30μm、ピッチyを75μm、Ag層4、10の厚さzを16.5μmとし、X方向にワイヤ5を張った後、回路基板12を90℃回転させて、またその上に、ワイヤ同士が接触しないように任意に調整してワイヤ5をY方向にボンディングした。次にワイヤ5の最大ループ高さd1の80%以下の箇所に、Sn層8と、Ag層10が形成された半導体素子9とを順次載せた(半導体素子搭載工程)。この製造中間体を実施例1〜14と同じプロセスを実行して、比較例5、6を製造した。比較例5と比較例6の違いはSn層8の厚さであり、比較例5の場合は50μmであり、比較例6の場合は40μmである。   Next, Comparative Examples 5 and 6 corresponding to Patent Documents 1 and 2 will be described. Up to now, evaluation was performed with the Ag wire 5 stretched in one direction, which is a feature of the present invention. Now, a sample in which the Ag wire 5 was stretched in two directions (X direction and Y direction) was produced. First, in the same process as described above, the same wire diameter x as in Example 7 was set to 30 μm, the pitch y was set to 75 μm, the thickness z of the Ag layers 4 and 10 was set to 16.5 μm, and the wire 5 was stretched in the X direction. The substrate 5 was rotated by 90 ° C., and the wire 5 was bonded in the Y direction by arbitrarily adjusting the substrate 12 so that the wires did not contact each other. Next, the Sn layer 8 and the semiconductor element 9 on which the Ag layer 10 was formed were sequentially placed at a position of 80% or less of the maximum loop height d1 of the wire 5 (semiconductor element mounting step). This production intermediate was subjected to the same process as in Examples 1 to 14 to produce Comparative Examples 5 and 6. The difference between the comparative example 5 and the comparative example 6 is the thickness of the Sn layer 8, which is 50 μm in the comparative example 5 and 40 μm in the comparative example 6.

比較例5、6について、SEMで合金形成状態を観察し、透過X線画像からボイド率を算出した。その結果、Sn層8の厚さが50μmである比較例5では、Sn単独相が存在し、合金形成状態が不良であり、かつボイド率も15%であり、目標の10%以下という条件をクリアできなかった。Sn層8の厚さが40μmである比較例6では、合金形成状態は良好だが、Snの量が足らないこと、及びボイドが抜けきらないため、ボイド率は20%と悪化した。   About Comparative Examples 5 and 6, the alloy formation state was observed by SEM, and the void ratio was calculated from the transmission X-ray image. As a result, in Comparative Example 5 in which the thickness of the Sn layer 8 is 50 μm, the Sn single phase exists, the alloy formation state is poor, the void ratio is 15%, and the target condition is 10% or less. Could not clear. In Comparative Example 6 in which the thickness of the Sn layer 8 was 40 μm, the alloy formation state was good, but the amount of Sn was insufficient and the voids could not be completely removed, so the void ratio deteriorated to 20%.

実施の形態1の半導体装置30は、回路基板12と半導体素子9等との接合部、すなわち接合対象物間が接合された接合部において、300℃でも溶融しない、AgとSnとの金属間化合物Ag3Sn(融点470℃程度)を形成するので、高融点の合金層13を形成することができる。実施の形態1の半導体装置30は、回路基板12や半導体素子9等の接合対象物にAg層4、10を形成し、一方の接合対象物である回路基板12のAg層4に、複数のAgのワイヤ5が面内に一方向のみに張られており、接合時にAgのワイヤ5が流れないようにボンディングされたワイヤ構造体20が形成されている。実施の形態1の半導体装置30は、回路基板12上のAg層4上にワイヤ構造体20が形成されたワイヤ付回路基板21に、Snを溶融させて、金属間化合物Ag3Sn(融点470℃程度)とAgからなる合金層13を備えることを特徴とする。実施の形態1の半導体装置30は、回路基板12と半導体素子9等との接合部、すなわち接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物Ag3Snを形成することができる。   The semiconductor device 30 according to the first embodiment includes an intermetallic compound of Ag and Sn that does not melt even at 300 ° C. at a junction between the circuit board 12 and the semiconductor element 9 or the like, that is, a junction between the objects to be joined. Since Ag3Sn (melting point of about 470 ° C.) is formed, the high melting point alloy layer 13 can be formed. In the semiconductor device 30 according to the first embodiment, Ag layers 4 and 10 are formed on a bonding target such as the circuit board 12 and the semiconductor element 9, and a plurality of Ag layers 4 on the circuit board 12 that is one bonding target are formed on the Ag layer 4. The Ag wire 5 is stretched in only one direction in the plane, and a wire structure 20 is formed so that the Ag wire 5 does not flow during bonding. In the semiconductor device 30 according to the first embodiment, Sn is melted in a circuit board with wire 21 in which the wire structure 20 is formed on the Ag layer 4 on the circuit board 12, and the intermetallic compound Ag3Sn (melting point is about 470 ° C.). And an alloy layer 13 made of Ag. The semiconductor device 30 according to the first embodiment forms the high melting point intermetallic compound Ag3Sn with few voids at the junction between the circuit board 12 and the semiconductor element 9, etc., that is, at the junction where the objects to be joined are joined. Can do.

実施の形態1の半導体装置30は、Agのワイヤ5を一方向に張る事で、Snが溶融して金属間化合物Ag3Snが形成される際に、少なからず発生するボイドが抜けるルートが確保されるため、X方向及びY方向にAgのワイヤが張られたワイヤ網よりもボイドを低減する事が可能となる。また、Agのワイヤ5を使用する事で、回路基板12と半導体素子9等との接合部においてワイヤ5やAg層から十分な量のAgが供給されるので、金属間化合物Ag3Snが十分な厚さで形成でき、接合厚、すなわち合金層13の厚さを均一にする事ができる。実施の形態1の半導体装置30は、回路基板12と半導体素子9等との接合部において極端に接合厚が薄い箇所ができないため、接合部におけるクラックの発生を抑制する効果がある。   In the semiconductor device 30 according to the first embodiment, by stretching the Ag wire 5 in one direction, when the Sn melts and the intermetallic compound Ag3Sn is formed, a route through which the generated voids escape is secured. Therefore, it is possible to reduce voids compared to a wire network in which Ag wires are stretched in the X direction and the Y direction. Also, by using the Ag wire 5, a sufficient amount of Ag is supplied from the wire 5 or the Ag layer at the joint between the circuit board 12 and the semiconductor element 9, etc., so that the intermetallic compound Ag3Sn has a sufficient thickness. Thus, the junction thickness, that is, the thickness of the alloy layer 13 can be made uniform. The semiconductor device 30 according to the first embodiment has an effect of suppressing the occurrence of cracks in the joint portion because the joint portion between the circuit board 12 and the semiconductor element 9 and the like cannot have an extremely thin joint thickness.

なお、接合時の雰囲気は、ギ酸に限定されるものではなく、酢酸、クエン酸、トルエン酸、水素でも良い。Agワイヤ径(ワイヤ直径x)は、今回の試験では、12〜50μmとした。しかし、一般的なワイヤボンダは50μm程度が限界とされているが、50μmよりも大きいワイヤをボンディングできるようにカスタマイズできれば、Agワイヤ径は12〜50μmに限定されるものではない。しかしながら、ワイヤ径を50μmよりも大きくすると、必然的にピッチyが大きくなり、Ag3Snで覆う体積が増えるため、Ag層4、10もより厚くする必要があり、コストが増大するため、好ましくない。また、Ag3Snを形成するのに、温度を高く、時間を長くしなければならず、製造コスト増大、タクトタイムが長くなるため、好ましくない。逆に、Agワイヤ径が12μmよりも小さい場合は、伸線を安定的に行うのが難しく、伸線時、あるいは、ワイヤボンディング時に破断する可能性があるため好ましくない。したがって、Agワイヤ径は、12〜50μmが好ましい。   The atmosphere at the time of joining is not limited to formic acid, but may be acetic acid, citric acid, toluene acid, or hydrogen. The Ag wire diameter (wire diameter x) was 12 to 50 μm in this test. However, a general wire bonder is limited to about 50 μm, but the Ag wire diameter is not limited to 12 to 50 μm as long as the wire bonder can be customized to bond a wire larger than 50 μm. However, if the wire diameter is larger than 50 μm, the pitch y is inevitably increased, and the volume covered with Ag3Sn increases. Therefore, it is necessary to make the Ag layers 4 and 10 thicker and the cost increases, which is not preferable. Further, it is not preferable to form Ag3Sn because the temperature must be increased and the time must be increased, and the manufacturing cost increases and the tact time increases. On the contrary, when the Ag wire diameter is smaller than 12 μm, it is difficult to stably perform the wire drawing, and it is not preferable because there is a possibility of breaking at the time of wire drawing or wire bonding. Therefore, the Ag wire diameter is preferably 12 to 50 μm.

接合時の加圧力は、浮いたワイヤ5をきちんと押さえる事ができれば良く、0.1MPa以上で同様の効果が得られる。加圧力が0.1MPaよりも小さいと、きちんと荷重を加える事ができず、接合厚が安定しない。また、Agワイヤボンディング後であって、還元雰囲気中で接合する前に、既に一度1MPa程度の加圧力を加えておくと、接合時においてAgワイヤの形状がより安定するため、好ましい。   The pressurizing force at the time of joining is not limited as long as the floated wire 5 can be properly pressed, and the same effect can be obtained at 0.1 MPa or more. If the applied pressure is less than 0.1 MPa, the load cannot be applied properly, and the joining thickness is not stable. Moreover, it is preferable to apply a pressure of about 1 MPa once after the Ag wire bonding and before bonding in a reducing atmosphere because the shape of the Ag wire becomes more stable at the time of bonding.

接合時の温度および時間は、AgとSnが拡散し終えるまでの任意の条件である。Ag3Snの成長速度を実験でも求めた結果を図12に示す。図12は、本発明の金属間化合物Ag3Snにおける温度及び時間毎の厚みを示す図である。1mm厚で、10mm×10mmのAg板上に、300μm厚のSnペレットを載せて、ギ酸還元雰囲気下で温度及び時間における任意の条件で熱処理を行ったサンプルを作成した。その後にSEMで断面観察してAg3Snの厚さを調べると、図12のようになり、250℃、1分の熱処理条件のサンプルでは平均3.8μmもあった。   The temperature and time at the time of joining are arbitrary conditions until Ag and Sn are completely diffused. FIG. 12 shows the results of the experiment for determining the growth rate of Ag3Sn. FIG. 12 is a diagram showing the temperature and the thickness of each intermetallic compound Ag3Sn according to the present invention. A 1 μm thick, 300 mm thick Sn pellet was placed on a 10 mm × 10 mm Ag plate, and a sample that was heat-treated in a formic acid reducing atmosphere at any temperature and time conditions was prepared. Thereafter, cross-sectional observation with an SEM was conducted to examine the thickness of Ag3Sn. As shown in FIG. 12, samples with a heat treatment condition of 250 ° C. for 1 minute had an average of 3.8 μm.

参考までに、1mm厚で、10mm×10mmのCu板上に300μm厚のSnペレットを載せて、ギ酸還元雰囲気下で任意の条件で熱処理を行い、その後にSEMで断面観察してCuとSnの合金層の厚さを調べると、0.7μm程度であり、Agの方が5〜6倍拡散が早い事が確認されている。   For reference, a 1 mm thick, 300 mm thick Sn pellet is placed on a 10 mm × 10 mm Cu plate, heat-treated under any conditions in a formic acid reducing atmosphere, and then cross-sectional observed with an SEM, Cu and Sn When the thickness of the alloy layer is examined, it is about 0.7 μm, and it is confirmed that the diffusion of Ag is 5 to 6 times faster.

箔状のSn層8は今回、Sn100%を用いたがこれに限定されるものではない。例えば、Sn内にAg、Cu、Sb、Bi、In,Zn、Mg、Si、P、Ga、Ni、Co、Geのうち少なくとも1種類以上含まれていても良い。   The foil-like Sn layer 8 is made of Sn 100% this time, but is not limited to this. For example, Sn may contain at least one of Ag, Cu, Sb, Bi, In, Zn, Mg, Si, P, Ga, Ni, Co, and Ge.

ワイヤ5の材質はAgが好ましいが、Ag以外にもNi、Cu、Fe、Auでも同様の効果が得られる。ワイヤ5の材質がAg以外の場合には、Ag層4、Ag層10の材質は、該当するワイヤ5の材質を用いる。また、ワイヤ5のAg内に、Pd、Ni、Cu、Fe、Au、Pt、Al、Sn、Sb,Ti、Pのうち少なくとも1種類以上添加されていても良い。また、接合部は半導体素子9と回路基板12と間の接合に限定されるものではなく、回路基板12とその下部に配置する放熱板や、半導体素子9とリードフレームとの接合部等に用いても良い。   The material of the wire 5 is preferably Ag, but the same effect can be obtained with Ni, Cu, Fe, or Au other than Ag. When the material of the wire 5 is other than Ag, the material of the corresponding wire 5 is used as the material of the Ag layer 4 and the Ag layer 10. In addition, at least one of Pd, Ni, Cu, Fe, Au, Pt, Al, Sn, Sb, Ti, and P may be added to the Ag of the wire 5. Further, the joining portion is not limited to joining between the semiconductor element 9 and the circuit board 12, but is used for a heat sink disposed in the circuit board 12 and the lower part thereof, a joining part between the semiconductor element 9 and the lead frame, or the like. May be.

半導体素子9は、シリコンウエハを基材とした一般的な素子でもよいが、本発明においてはシリコンカーバイド(SiC)や窒化ガリウム(GaN)系材料、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料を適用できる。半導体素子9のデバイス種類としては、特に限定する必要はないが、IGBT(Insulated Gate Bipolar Transistor)やMOSFET(Metal Oxide Semiconductor Field-Effect-Transistor)のようなスイッチング素子、やダイオードのような整流素子を搭載することができる。例えば、スイッチング素子や整流素子として機能する半導体素子9に、シリコンカーバイド(SiC)や窒化ガリウム(GaN)系材料又はダイヤモンドを用いた場合、従来から用いられてきたシリコン(Si)で形成された素子よりも電力損失が低いため、パワーモジュールの高効率化が可能となる。また、耐電圧性が高く、許容電流密度も高いため、パワーモジュールの小型化が可能となる。さらにワイドバンドギャップ半導体素子は、耐熱性が高いので、高温動作が可能であり、放熱フィンの小型化や、水冷部の空冷化も可能となるので、放熱フィンを備えたパワーモジュールの一層の小型化が可能になる。   The semiconductor element 9 may be a general element based on a silicon wafer, but in the present invention, the band gap is wider than silicon such as silicon carbide (SiC), gallium nitride (GaN) -based material, or diamond. A so-called wide band gap semiconductor material can be applied. The device type of the semiconductor element 9 is not particularly limited, but switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors), and rectifying elements such as diodes may be used. Can be installed. For example, when silicon carbide (SiC), gallium nitride (GaN) -based material, or diamond is used for the semiconductor element 9 functioning as a switching element or a rectifying element, an element formed of silicon (Si) that has been conventionally used Since the power loss is lower than that, the efficiency of the power module can be increased. Further, since the withstand voltage is high and the allowable current density is high, the power module can be downsized. In addition, wide bandgap semiconductor elements have high heat resistance, enabling high-temperature operation, and reducing the size of the radiating fins and air cooling of the water-cooled part. This further reduces the size of power modules equipped with radiating fins. Can be realized.

以上のように、実施の形態1の半導体装置30によれば、実装基板(回路基板12)に形成された第1のAg層4と、半導体素子9に形成された第2のAg層10との間に挟持された合金層13を備え、合金層13は、第1のAg層及び第2のAg層のAg成分と、Snによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤ5が当該合金層13の外周側から延伸して配置されたことを特徴とするので、すなわち、Ag3Snの金属間化合物を有する合金層13にAgを含んだ複数のワイヤ5が接続された構造を備えたので、合金層13が形成される際に少なからず発生するボイドが抜けるルートがワイヤ5間に確保されており、接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物を形成することができる。   As described above, according to the semiconductor device 30 of the first embodiment, the first Ag layer 4 formed on the mounting substrate (circuit substrate 12), the second Ag layer 10 formed on the semiconductor element 9, and The alloy layer 13 includes an Ag component of the first Ag layer and the second Ag layer, and an Ag3Sn intermetallic compound formed of Sn, and includes Ag. Since the plurality of wires 5 are arranged extending from the outer peripheral side of the alloy layer 13, that is, the plurality of wires 5 containing Ag are connected to the alloy layer 13 having an intermetallic compound of Ag 3 Sn. Since the structure is provided, a route through which voids generated at least when the alloy layer 13 is formed is secured between the wires 5, and there are few voids at the joint where the objects to be joined are joined. High melting point intermetallic compound It can be formed.

また、実施の形態1の半導体装置30の製造方法によれば、実装基板(回路基板12)に形成された第1のAg層4に、Agを含んだ複数のワイヤ5が平行に又は放射状に配置されたワイヤ構造体20を形成するワイヤ構造体形成工程と、ワイヤ構造体20の外形面積よりも実装面の面積が小さくて、実装面に第2のAg層10が形成された半導体素子9を、ワイヤ構造体20に、Sn層8を介在させて搭載する半導体素子搭載工程と、半導体素子搭載工程の後に、熱処理を行い、実装基板(回路基板12)と半導体素子9とが接合された接合部に、Ag3Snの金属間化合物を有する合金層13を形成する合金層形成工程と、を含むことを特徴とするので、合金層形成工程の際に少なからず発生するボイドが抜けるルートが確保できるため、接合対象物間が接合された接合部において、ボイドが少ない高融点の金属間化合物を形成することができる。   Further, according to the method of manufacturing the semiconductor device 30 of the first embodiment, the plurality of wires 5 containing Ag are parallel or radially formed on the first Ag layer 4 formed on the mounting substrate (circuit substrate 12). A wire structure forming step for forming the arranged wire structure 20, and a semiconductor element 9 in which the area of the mounting surface is smaller than the outer area of the wire structure 20, and the second Ag layer 10 is formed on the mounting surface Are mounted on the wire structure 20 with the Sn layer 8 interposed therebetween, and heat treatment is performed after the semiconductor element mounting step to bond the mounting substrate (circuit substrate 12) and the semiconductor element 9 together. And an alloy layer forming step of forming an alloy layer 13 having an Ag3Sn intermetallic compound at the joint. Therefore, it is possible to ensure a route through which voids generated at the time of the alloy layer forming step escape. For In joints between the bonding target is bonded, it can form an intermetallic compound of voids less refractory.

実施の形態2.
Agのワイヤ5の配置形状は、実施の形態1で示した配置形状に限らず、例えば図13のように放射状に配置させた配置形状でも良い。図13は、本発明の実施の形態2によるワイヤの配置を示す図である。図13に示したワイヤ構造体20は、4つのワイヤ5a1、5a2、5a3、5a4で区切られた領域が同じ形状である例である。便宜上、ワイヤ5a1〜ワイヤ5a2を第1領域と呼び、ワイヤ5a2〜ワイヤ5a3を第2領域と呼び、ワイヤ5a3〜ワイヤ5a4を第3領域と呼び、ワイヤ5a4〜ワイヤ5a1を第4領域と呼ぶことにする。
Embodiment 2. FIG.
The arrangement shape of the Ag wires 5 is not limited to the arrangement shape shown in the first embodiment, and may be an arrangement shape arranged radially as shown in FIG. 13, for example. FIG. 13 is a diagram showing an arrangement of wires according to the second embodiment of the present invention. The wire structure 20 illustrated in FIG. 13 is an example in which regions divided by four wires 5a1, 5a2, 5a3, and 5a4 have the same shape. For convenience, the wires 5a1 to 5a2 are referred to as a first region, the wires 5a2 to 5a3 are referred to as a second region, the wires 5a3 to 5a4 are referred to as a third region, and the wires 5a4 to 5a1 are referred to as a fourth region. To.

ワイヤ5a1、ワイヤ5a3は同一直線状に配置され、ワイヤ5a2、ワイヤ5a4は同一直線状に配置される。ワイヤ5a2は、ワイヤ5a1及びワイヤ5a3に垂直に配置され、ワイヤ5a4も、ワイヤ5a1及びワイヤ5a3に垂直に配置される。第1領域にワイヤ5b1がワイヤ5a1及びワイヤ5a2との角度が等しくなるように配置される。同様に、第2領域にワイヤ5b2がワイヤ5a2及びワイヤ5a3との角度が等しくなるように配置され、第3領域にワイヤ5b3がワイヤ5a3及びワイヤ5a4との角度が等しくなるように配置され、第4領域にワイヤ5b4がワイヤ5a4及びワイヤ5a1との角度が等しくなるように配置される。   The wires 5a1 and 5a3 are arranged in the same straight line, and the wires 5a2 and 5a4 are arranged in the same straight line. The wire 5a2 is arranged perpendicular to the wires 5a1 and 5a3, and the wire 5a4 is also arranged perpendicular to the wires 5a1 and 5a3. The wire 5b1 is arranged in the first region so that the angles of the wire 5a1 and the wire 5a2 are equal. Similarly, the wire 5b2 is arranged in the second region so that the angles of the wires 5a2 and 5a3 are equal, and the wire 5b3 is arranged in the third region so that the angles of the wires 5a3 and 5a4 are equal, The wires 5b4 are arranged in the four regions so that the angles of the wires 5a4 and 5a1 are equal.

その他のワイヤの配置を、第1領域を例に説明する。ワイヤ5c1がワイヤ5a1及びワイヤ5b1との角度が等しくなるように配置される。同様に、ワイヤ5c2がワイヤ5b1及びワイヤ5a2との角度が等しくなるように配置される。ワイヤ5d1がワイヤ5a1及びワイヤ5c1との間に配置され、ワイヤ5d2がワイヤ5c2及びワイヤ5a2との間に配置される。ワイヤ5e1がワイヤ5c1及びワイヤ5b1との間に配置され、ワイヤ5e2がワイヤ5b1及びワイヤ5c2との間に配置される。図13に示したワイヤ構造体20は、32本のワイヤ5による外周形状が丸みを帯びた四角形の形状になっている。   The arrangement of other wires will be described using the first region as an example. The wire 5c1 is arranged so that the angles of the wire 5a1 and the wire 5b1 are equal. Similarly, the wire 5c2 is disposed so that the angles of the wire 5b1 and the wire 5a2 are equal. The wire 5d1 is disposed between the wire 5a1 and the wire 5c1, and the wire 5d2 is disposed between the wire 5c2 and the wire 5a2. The wire 5e1 is disposed between the wire 5c1 and the wire 5b1, and the wire 5e2 is disposed between the wire 5b1 and the wire 5c2. The wire structure 20 shown in FIG. 13 has a rounded quadrangular shape in which the outer peripheral shape of the 32 wires 5 is rounded.

図14は本発明の実施の形態2による半導体素子とワイヤの位置を説明する図であり、図15は本発明の実施の形態2による半導体装置の断面図である。図14及び図15は、ワイヤ5a1及びワイヤ5a3を切断した場合の断面を示している。図14は半導体素子9がワイヤ付回路基板21のワイヤ5に接触する前の状態を示している。なお、図14、及び図15において、ワイヤ5a1及びワイヤ5a3以外の他のワイヤ5は省略した。実施の形態2の半導体装置30は、ワイヤ構造体形成工程のワイヤ接続工程でワイヤ5が外側から中心側に向かってワイヤボンディングすることが異なるが、他の工程は同じである。半導体素子搭載工程では、半導体素子9は、実施の形態1と同様に、素子搭載位置でのワイヤ5のループ高さd2がd1の80%以下になるような位置に搭載される。半導体装置30において、複数のワイヤ5が、合金層13の外周側から放射状に延伸して配置されている。   FIG. 14 is a diagram for explaining the positions of the semiconductor elements and wires according to the second embodiment of the present invention, and FIG. 15 is a sectional view of the semiconductor device according to the second embodiment of the present invention. 14 and 15 show cross sections when the wire 5a1 and the wire 5a3 are cut. FIG. 14 shows a state before the semiconductor element 9 contacts the wire 5 of the circuit board 21 with wire. In FIGS. 14 and 15, the wires 5 other than the wires 5a1 and 5a3 are omitted. In the semiconductor device 30 of the second embodiment, the wire 5 is wire-bonded from the outside toward the center in the wire connection process of the wire structure forming process, but the other processes are the same. In the semiconductor element mounting step, the semiconductor element 9 is mounted at a position where the loop height d2 of the wire 5 at the element mounting position is 80% or less of d1 as in the first embodiment. In the semiconductor device 30, a plurality of wires 5 are arranged radially extending from the outer peripheral side of the alloy layer 13.

実施の形態2のワイヤ構造体20では、Snが溶融して金属間化合物Ag3Snが形成される際に、少なからず発生するボイドが、中心から外周側に抜けるようになっている。
る。図13に示すようにしても、Snが溶融して金属間化合物Ag3Snが形成される際に、少なからず発生するボイドの抜けるルートが確保されているため、実施の形態1と同様に、ボイドが少なく、良好な接合が得られる。なお、図13〜図15では、ステッチボンド7がワイヤ構造体20のほぼ中央にある例を示したが、これに限定されることはなく、ステッチボンド7がワイヤ構造体20の内側にあればよい。
In the wire structure 20 according to the second embodiment, when Sn is melted to form the intermetallic compound Ag3Sn, not a little void is generated from the center to the outer peripheral side.
The Even in the case shown in FIG. 13, when Sn melts to form the intermetallic compound Ag3Sn, a route through which a void that occurs at least is removed is secured. Less and good bonding can be obtained. 13 to 15 show an example in which the stitch bond 7 is substantially at the center of the wire structure 20, the present invention is not limited to this, and if the stitch bond 7 is inside the wire structure 20. Good.

なお、本発明は、その発明の範囲内において、各実施の形態を組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be combined with each other within the scope of the invention, and each embodiment can be modified or omitted as appropriate.

4…Ag層、5、5a、5b、5c、5d、5e、5f、5g…ワイヤ、
5a1、5a2、5a3、5a4、5b1、5b2、5b3、5b4、
5c1、5c2、5d1、5d2、5e1、5e2…ワイヤ、8…Sn層、
9…半導体素子、10…Ag層、11…屈曲部、12…回路基板、
13…合金層、20…ワイヤ構造体、30…半導体装置。
4 ... Ag layer 5, 5a, 5b, 5c, 5d, 5e, 5f, 5g ... wire,
5a1, 5a2, 5a3, 5a4, 5b1, 5b2, 5b3, 5b4,
5c1, 5c2, 5d1, 5d2, 5e1, 5e2 ... wire, 8 ... Sn layer,
DESCRIPTION OF SYMBOLS 9 ... Semiconductor element, 10 ... Ag layer, 11 ... Bending part, 12 ... Circuit board,
13 ... alloy layer, 20 ... wire structure, 30 ... semiconductor device.

以上の結果をまとめると、Agワイヤ直径x、ピッチy、Ag層の厚さzには以下の3式が成り立つ。
y=2.5x ・・・(1)
z≧0.53x ・・・(11)
z≧0.21y ・・・(12)
Summarizing the above results, the following three formulas are established for the Ag wire diameter x, the pitch y, and the thickness z of the Ag layer.
y = 2.5x (1)
z ≧ 0.53x (11)
z ≧ 0.21y (12)

ワイヤボンディング(ワイヤ接続工程)について、詳細を説明する。最初に、ワイヤ5の先端に水素5%の窒素ガスを吹き付けて、放電でワイヤ径の1.5〜1.8倍程度で安定的に真球のボールが形成できる放電条件(放電電流、時間、ガス吹き付け量)でボールを作製し、回路基板12上のAg層4に超音波と、圧力をかけて、半導体素子9の搭載位置からa2=2mm外側に離した位置にボールボンド6の形成を行う。このとき、真球が安定的に形成されず、偏芯を起こしてしまうと、ボンディングしたときに、圧力が均一に加わらないため、きちんとボンディングされないので、注意が必要である。また、偏芯している場合は、狙った位置にボンディングができず、ピッチが安定しないので、注意が必要である。 Details of wire bonding (wire connection process) will be described. First, a 5% hydrogen nitrogen gas is blown onto the tip of the wire 5, and discharge conditions (discharge current and time) that can stably form a true spherical ball at about 1.5 to 1.8 times the wire diameter by discharge. The ball bond 6 is formed at a position spaced a2 = 2 mm away from the mounting position of the semiconductor element 9 by applying ultrasonic waves and pressure to the Ag layer 4 on the circuit board 12. I do. At this time, if the true sphere is not stably formed and the eccentricity occurs, the pressure is not uniformly applied when bonding is performed, so that the bonding is not performed properly. In addition, if it is eccentric, bonding cannot be performed at the target position and the pitch is not stable, so care must be taken.

次に、ワイヤ5を、屈曲部11を設けて、半導体素子9の素子サイズc1=7mmよりも長い、長さa1=10mmまで張って、超音波と、圧力をかけて、半導体素子9の素子搭載位置からa3=1mm離した位置にステッチボンド7の形成をする。なお、屈曲部11は任意の高さが可能だが、この屈曲部11が最終的にループしたときに一番高い位置になるため、ループ高さd1を市販の装置では限界の50μmになるように調整する。また、素子搭載位置でのループ高さd2がd1の80%以下になるように調整する。このようにしたのは、素子搭載位置内に最大ループ高さの部分があると、この後の接合時に圧力をかけたときに、図7、図8のように、ワイヤ16が重なりながら、押し潰されるため、好ましくないからである。図7及び図8は、比較例による半導体素子とワイヤの位置を説明する図である。図7は半導体素子9がワイヤ16に接触する前の状態を示し、図8は半導体素子9がワイヤ16を押圧した状態を示している。 Next, the wire 5 is provided with a bent portion 11 and stretched to a length a1 = 10 mm which is longer than the element size c1 = 7 mm of the semiconductor element 9, and ultrasonic waves and pressure are applied to the element of the semiconductor element 9 A stitch bond 7 is formed at a position a3 = 1 mm away from the mounting position. The bent portion 11 can have an arbitrary height, but when the bent portion 11 finally loops, it becomes the highest position, so that the loop height d1 is set to 50 μm, which is the limit in a commercially available device. adjust. Further, the loop height d2 at the element mounting position is adjusted to be 80% or less of d1. This is because, when there is a portion of the maximum loop height in the element mounting position, when pressure is applied during subsequent joining, the wire 16 is pushed while being overlapped as shown in FIGS. It is because it is crushed and is not preferable. 7 and 8 are diagrams for explaining the positions of semiconductor elements and wires according to a comparative example. FIG. 7 shows a state before the semiconductor element 9 contacts the wire 16, and FIG. 8 shows a state where the semiconductor element 9 presses the wire 16.

図10には、各サンプルの製造条件と、検査結果である合金形成状態とボイド率が記載されている。ワイヤ引張方向は、1方向か2方向以上の多方向かを示している。必要めっき厚は、式(11)及び式(12)を満たすAg層4、10の厚さzである。実施のめっき厚zは、各サンプルのAg層4、10の厚さである。理論式の適合は、理論式である式(1)、式(11)、式(12)を満たす(OK表示)か否か(NG表示)を示している。必要Sn箔厚は、式(14)及び式(15)を満たすSn層8の厚さtである。実際のSn箔厚tは、各サンプルのSn層8の厚さである。合金形成は、接合部の合金層13が良好か否を示している。合金形成が良好な場合は、OKの表示をし、接合部がAgおよびAg3Snのみで形成されており、Sn単独相がない事を示している。合金形成が不良な場合は、NGの表示をしている。 FIG. 10 shows the manufacturing conditions of each sample, the alloy formation state and the void ratio, which are inspection results. The wire pulling direction indicates one direction or multiple directions including two or more directions. The required plating thickness is the thickness z of the Ag layers 4 and 10 that satisfy the expressions (11) and (12). The actual plating thickness z is the thickness of the Ag layers 4 and 10 of each sample. The conformity of the theoretical formula indicates whether or not the theoretical formulas (1) , (11), and (12) are satisfied (OK display) or not (NG display). The necessary Sn foil thickness is the thickness t of the Sn layer 8 that satisfies the expressions (14) and (15). The actual Sn foil thickness t is the thickness of the Sn layer 8 of each sample. The alloy formation indicates whether or not the alloy layer 13 at the joint is good. When the alloy formation is good, OK is indicated, indicating that the joint is formed of only Ag and Ag3Sn and there is no Sn single phase. When the alloy formation is poor, NG is displayed.

図10の実施例1〜10に示したように、Sn層8の厚さが必要厚以上あり、かつ式(1)、式(11)、式(12)で示された条件を満たすことで、合金形成状態、ボイド率は全て良好であった。 As shown in Examples 1 to 10 in FIG. 10, the Sn layer 8 has a thickness greater than the required thickness and satisfies the conditions represented by the expressions (1) , (11), and (12). The alloy formation state and void ratio were all good.

実施の形態2のワイヤ構造体20では、Snが溶融して金属間化合物Ag3Snが形成される際に、少なからず発生するボイドが、中心から外周側に抜けるようになっている。図13に示すようにしても、Snが溶融して金属間化合物Ag3Snが形成される際に、少なからず発生するボイドの抜けるルートが確保されているため、実施の形態1と同様に、ボイドが少なく、良好な接合が得られる。なお、図13〜図15では、ステッチボンド7がワイヤ構造体20のほぼ中央にある例を示したが、これに限定されることはなく、ステッチボンド7がワイヤ構造体20の内側にあればよい。 In the wire structure 20 according to the second embodiment, when Sn is melted to form the intermetallic compound Ag3Sn, not a little void is generated from the center to the outer peripheral side . Even in the case shown in FIG. 13, when Sn melts to form the intermetallic compound Ag3Sn, a route through which a void that occurs at least is removed is secured. Less and good bonding can be obtained. 13 to 15 show an example in which the stitch bond 7 is substantially at the center of the wire structure 20, the present invention is not limited to this, and if the stitch bond 7 is inside the wire structure 20. Good.

Claims (22)

  1. 半導体素子が実装基板に接合された半導体装置であって、
    前記実装基板に形成された第1のAg層と、前記半導体素子に形成された第2のAg層との間に挟持された合金層を備え、
    前記合金層は、
    第1のAg層及び第2のAg層のAg成分と、Snによって形成されたAg3Snの金属間化合物を有し、Agを含んだ複数のワイヤが当該合金層の外周側から延伸して配置されたことを特徴とする半導体装置。
    A semiconductor device in which a semiconductor element is bonded to a mounting substrate,
    An alloy layer sandwiched between a first Ag layer formed on the mounting substrate and a second Ag layer formed on the semiconductor element;
    The alloy layer is
    It has an Ag component of the first Ag layer and the second Ag layer, and an Ag3Sn intermetallic compound formed of Sn, and a plurality of wires containing Ag are arranged extending from the outer peripheral side of the alloy layer. A semiconductor device characterized by the above.
  2. 前記ワイヤは、同一の方向に延伸して配置されたことを特徴とする請求項1記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the wires are arranged extending in the same direction.
  3. 前記ワイヤは、前記合金層の外周側から放射状に延伸して配置されたことを特徴とする請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein the wires are radially extended from an outer peripheral side of the alloy layer.
  4. 前記ワイヤの材質は、Ag以外に、Pd、Ni、Cu、Fe、Au、Pt、Al、Sn、Sb,Ti、Pのうち少なくとも1種類以上添加されていることを特徴とする請求項1から3のいずれか1項に記載の半導体装置。   The material of the wire is added with at least one of Pd, Ni, Cu, Fe, Au, Pt, Al, Sn, Sb, Ti, and P in addition to Ag. 4. The semiconductor device according to any one of items 3.
  5. 前記半導体素子は、ワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element is made of a wide band gap semiconductor material.
  6. 前記ワイドバンドギャップ半導体材料は、シリコンカーバイド、窒化ガリウム系材料、またはダイヤモンドのうちのいずれかであることを特徴とする請求項5記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the wide band gap semiconductor material is one of silicon carbide, gallium nitride-based material, and diamond.
  7. 半導体素子が実装基板に接合された半導体装置を製造する半導体装置の製造方法であって、
    前記実装基板に形成された第1のAg層に、Agを含んだ複数のワイヤが平行に又は放射状に配置されたワイヤ構造体を形成するワイヤ構造体形成工程と、
    前記ワイヤ構造体の外形面積よりも実装面の面積が小さくて、前記実装面に第2のAg層が形成された前記半導体素子を、前記ワイヤ構造体に、Sn層を介在させて搭載する半導体素子搭載工程と、
    前記半導体素子搭載工程の後に、熱処理を行い、前記実装基板と前記半導体素子とが接合された接合部に、Ag3Snの金属間化合物を有する合金層を形成する合金層形成工程と、を含むことを特徴とする半導体装置の製造方法。
    A semiconductor device manufacturing method for manufacturing a semiconductor device in which a semiconductor element is bonded to a mounting substrate,
    A wire structure forming step of forming a wire structure in which a plurality of wires containing Ag are arranged in parallel or radially on the first Ag layer formed on the mounting substrate;
    A semiconductor in which the area of the mounting surface is smaller than the outer area of the wire structure and the semiconductor element having the second Ag layer formed on the mounting surface is mounted on the wire structure with an Sn layer interposed Element mounting process;
    And an alloy layer forming step of forming an alloy layer having an Ag3Sn intermetallic compound at a joint portion where the mounting substrate and the semiconductor element are joined after the semiconductor element mounting step. A method of manufacturing a semiconductor device.
  8. 前記ワイヤ構造体形成工程において、前記ワイヤ構造体は、外周側に当該ワイヤ構造体の最大高さとなる屈曲部を有するように形成され、
    前記半導体素子搭載工程において、前記半導体素子は、前記ワイヤ構造体における最大高さの80%よりも低い領域に搭載されることを特徴とする請求項7記載の半導体装置の製造方法。
    In the wire structure forming step, the wire structure is formed to have a bent portion that is the maximum height of the wire structure on the outer peripheral side,
    8. The method of manufacturing a semiconductor device according to claim 7, wherein, in the semiconductor element mounting step, the semiconductor element is mounted in a region lower than 80% of the maximum height of the wire structure.
  9. 前記ワイヤ構造体形成工程は、前記ワイヤを互いに平行になるように前記第1のAg層に接続するワイヤ接続工程を含むことを特徴とする請求項7または8に記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 7, wherein the wire structure forming step includes a wire connecting step of connecting the wires to the first Ag layer so as to be parallel to each other.
  10. 前記ワイヤ構造体形成工程は、前記ワイヤを前記ワイヤ構造体の外側から内側に延伸させながら前記第1のAg層に接続するワイヤ接続工程を含むことを特徴とする請求項7または8に記載の半導体装置の製造方法。   The wire structure forming step includes a wire connection step of connecting the first Ag layer while extending the wire from the outside to the inside of the wire structure. A method for manufacturing a semiconductor device.
  11. 請求項9記載の半導体装置の製造方法において、
    前記第1のAg層及び前記第2のAg層の厚さをzとし、前記ワイヤのワイヤ直径をxとし、前記ワイヤが配置されるピッチをyとした場合に、
    y≧2.5x、z≧0.53x、z≧0.21y
    を満たすことを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to claim 9,
    When the thickness of the first Ag layer and the second Ag layer is z, the wire diameter of the wire is x, and the pitch at which the wires are arranged is y,
    y ≧ 2.5x, z ≧ 0.53x, z ≧ 0.21y
    The manufacturing method of the semiconductor device characterized by satisfying these.
  12. 請求項11記載の半導体装置の製造方法において、
    前記Sn層の厚さをtとした場合に、
    t≧0.68x、t≧0.27y
    を満たすことを特徴とする半導体装置の製造方法。
    The method of manufacturing a semiconductor device according to claim 11.
    When the thickness of the Sn layer is t,
    t ≧ 0.68x, t ≧ 0.27y
    The manufacturing method of the semiconductor device characterized by satisfying these.
  13. 請求項7から12のいずれか1項に記載の半導体装置の製造方法において、
    前記ワイヤのワイヤ直径が、12μm以上で50μm以下であることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 12,
    The method of manufacturing a semiconductor device, wherein the wire has a wire diameter of 12 μm or more and 50 μm or less.
  14. 請求項7から12のいずれか1項に記載の半導体装置の製造方法において、
    前記第1のAg層及び前記第2のAg層の厚さが、6.3μm以上で29.4μm以下であることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 12,
    A method of manufacturing a semiconductor device, wherein the first Ag layer and the second Ag layer have a thickness of 6.3 μm or more and 29.4 μm or less.
  15. 請求項9、11、12のいずれか1項に記載の半導体装置の製造方法において、
    前記ワイヤが配置されるピッチが、30μm以上で140μm以下であることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 9, 11, and 12,
    A method of manufacturing a semiconductor device, wherein a pitch at which the wires are arranged is 30 μm or more and 140 μm or less.
  16. 請求項12記載の半導体装置の製造方法において、
    前記Sn層の厚さが、9μm以上で37μm以下であることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to claim 12,
    A method of manufacturing a semiconductor device, wherein the Sn layer has a thickness of 9 μm to 37 μm.
  17. 請求項7から16のいずれか1項に記載の半導体装置の製造方法において、
    前記合金層形成工程が実行される雰囲気が、ギ酸、酢酸、クエン酸、トルエン酸、水素のいずれかであることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 16,
    An atmosphere in which the alloy layer forming step is performed is any one of formic acid, acetic acid, citric acid, toluene acid, and hydrogen.
  18. 請求項7から16のいずれか1項に記載の半導体装置の製造方法において、
    前記合金層形成工程において、前記半導体素子が前記実装基板の側に押される加圧力は、0.1MPa以上であることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 16,
    In the alloy layer forming step, a pressing force by which the semiconductor element is pressed toward the mounting substrate is 0.1 MPa or more.
  19. 請求項7から16のいずれか1項に記載の半導体装置の製造方法において、
    前記Sn層は、Sn以外に、Ag、Cu、Sb、Bi、In,Zn、Mg、Si、P、Ga、Ni、Co、Geのうち少なくとも1種類以上含まれていることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 16,
    In addition to Sn, the Sn layer contains at least one of Ag, Cu, Sb, Bi, In, Zn, Mg, Si, P, Ga, Ni, Co, and Ge. Device manufacturing method.
  20. 請求項7から16のいずれか1項に記載の半導体装置の製造方法において、
    前記ワイヤの材質は、Ag以外に、Pd、Ni、Cu、Fe、Au、Pt、Al、Sn、Sb,Ti、Pのうち少なくとも1種類以上添加されていることを特徴とする半導体装置の製造方法。
    In the manufacturing method of the semiconductor device according to any one of claims 7 to 16,
    The wire is made of at least one of Pd, Ni, Cu, Fe, Au, Pt, Al, Sn, Sb, Ti, and P in addition to Ag. Method.
  21. 前記半導体素子は、ワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項7から20のいずれか1項に記載の半導体装置の製造方法。   21. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor element is made of a wide band gap semiconductor material.
  22. 前記ワイドバンドギャップ半導体材料は、シリコンカーバイド、窒化ガリウム系材料、またはダイヤモンドのうちのいずれかであることを特徴とする請求項21記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 21, wherein the wide band gap semiconductor material is any one of silicon carbide, a gallium nitride-based material, and diamond.
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