JP5951568B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5951568B2 JP5951568B2 JP2013178713A JP2013178713A JP5951568B2 JP 5951568 B2 JP5951568 B2 JP 5951568B2 JP 2013178713 A JP2013178713 A JP 2013178713A JP 2013178713 A JP2013178713 A JP 2013178713A JP 5951568 B2 JP5951568 B2 JP 5951568B2
- Authority
- JP
- Japan
- Prior art keywords
- carbon nanotube
- cnt
- groove
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4462—Carbon or carbon-containing materials, e.g. graphene
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/0554—Manufacture or treatment of conductive parts of the interconnections of nanotubes or nanowires
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/754—Dendrimer, i.e. serially branching or "tree-like" structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Carbon And Carbon Compounds (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013178713A JP5951568B2 (ja) | 2013-08-29 | 2013-08-29 | 半導体装置及びその製造方法 |
| TW103107900A TWI541970B (zh) | 2013-08-29 | 2014-03-07 | 半導體裝置及其製造方法 |
| US14/202,683 US8981561B1 (en) | 2013-08-29 | 2014-03-10 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013178713A JP5951568B2 (ja) | 2013-08-29 | 2013-08-29 | 半導体装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015050209A JP2015050209A (ja) | 2015-03-16 |
| JP2015050209A5 JP2015050209A5 (https=) | 2015-10-01 |
| JP5951568B2 true JP5951568B2 (ja) | 2016-07-13 |
Family
ID=52582071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013178713A Active JP5951568B2 (ja) | 2013-08-29 | 2013-08-29 | 半導体装置及びその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8981561B1 (https=) |
| JP (1) | JP5951568B2 (https=) |
| TW (1) | TWI541970B (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6129772B2 (ja) * | 2014-03-14 | 2017-05-17 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
| JP6330415B2 (ja) * | 2014-03-27 | 2018-05-30 | 富士通株式会社 | 半導体装置の製造方法 |
| JP6181224B1 (ja) | 2016-03-04 | 2017-08-16 | 株式会社東芝 | グラフェン配線構造とその作製方法 |
| JP6717056B2 (ja) * | 2016-05-30 | 2020-07-01 | 株式会社Ihi | 可飽和吸収素子の製造方法及び部材 |
| KR102350640B1 (ko) * | 2019-07-29 | 2022-01-14 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 제조 방법 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3953276B2 (ja) * | 2000-02-04 | 2007-08-08 | 株式会社アルバック | グラファイトナノファイバー、電子放出源及びその作製方法、該電子放出源を有する表示素子、並びにリチウムイオン二次電池 |
| JP3634781B2 (ja) * | 2000-09-22 | 2005-03-30 | キヤノン株式会社 | 電子放出装置、電子源、画像形成装置及びテレビジョン放送表示装置 |
| JP3768908B2 (ja) * | 2001-03-27 | 2006-04-19 | キヤノン株式会社 | 電子放出素子、電子源、画像形成装置 |
| JP3768937B2 (ja) * | 2001-09-10 | 2006-04-19 | キヤノン株式会社 | 電子放出素子、電子源及び画像表示装置の製造方法 |
| US20100244262A1 (en) * | 2003-06-30 | 2010-09-30 | Fujitsu Limited | Deposition method and a deposition apparatus of fine particles, a forming method and a forming apparatus of carbon nanotubes, and a semiconductor device and a manufacturing method of the same |
| JP3944155B2 (ja) * | 2003-12-01 | 2007-07-11 | キヤノン株式会社 | 電子放出素子、電子源及び画像表示装置の製造方法 |
| US7135773B2 (en) * | 2004-02-26 | 2006-11-14 | International Business Machines Corporation | Integrated circuit chip utilizing carbon nanotube composite interconnection vias |
| JP4167212B2 (ja) * | 2004-10-05 | 2008-10-15 | 富士通株式会社 | カーボンナノチューブ構造体、半導体装置、および半導体パッケージ |
| JP4596878B2 (ja) * | 2004-10-14 | 2010-12-15 | キヤノン株式会社 | 構造体、電子放出素子、2次電池、電子源、画像表示装置、情報表示再生装置及びそれらの製造方法 |
| DE102007050843A1 (de) * | 2006-10-26 | 2008-05-21 | Samsung Electronics Co., Ltd., Suwon | Integrierte Schaltung mit Kohlenstoffnanoröhren und Verfahren zu deren Herstellung unter Verwendung von geschützten Katalysatorschichten |
| FR2910706B1 (fr) * | 2006-12-21 | 2009-03-20 | Commissariat Energie Atomique | Element d'interconnexion a base de nanotubes de carbone |
| JP5181512B2 (ja) * | 2007-03-30 | 2013-04-10 | 富士通セミコンダクター株式会社 | 電子デバイスの製造方法 |
| KR100827524B1 (ko) * | 2007-04-06 | 2008-05-06 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| WO2010023720A1 (ja) * | 2008-08-25 | 2010-03-04 | 株式会社 東芝 | 構造体、電子装置及び構造体の形成方法 |
| US8518542B2 (en) * | 2009-05-26 | 2013-08-27 | Life Technology Research Institute, Inc. | Carbon film and carbon film structure |
| JP2011061026A (ja) * | 2009-09-10 | 2011-03-24 | Toshiba Corp | カーボンナノチューブ配線及びその製造方法 |
| JP2011204769A (ja) | 2010-03-24 | 2011-10-13 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP2011238726A (ja) * | 2010-05-10 | 2011-11-24 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP2012038888A (ja) * | 2010-08-06 | 2012-02-23 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP5468496B2 (ja) * | 2010-08-25 | 2014-04-09 | 株式会社東芝 | 半導体基板の製造方法 |
| US20130072077A1 (en) * | 2011-09-21 | 2013-03-21 | Massachusetts Institute Of Technology | Systems and methods for growth of nanostructures on substrates, including substrates comprising fibers |
| JP5591784B2 (ja) * | 2011-11-25 | 2014-09-17 | 株式会社東芝 | 配線及び半導体装置 |
-
2013
- 2013-08-29 JP JP2013178713A patent/JP5951568B2/ja active Active
-
2014
- 2014-03-07 TW TW103107900A patent/TWI541970B/zh active
- 2014-03-10 US US14/202,683 patent/US8981561B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW201508891A (zh) | 2015-03-01 |
| TWI541970B (zh) | 2016-07-11 |
| US20150061131A1 (en) | 2015-03-05 |
| JP2015050209A (ja) | 2015-03-16 |
| US8981561B1 (en) | 2015-03-17 |
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