JP5875687B2 - ソースゲートを含む装置および方法 - Google Patents

ソースゲートを含む装置および方法 Download PDF

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JP5875687B2
JP5875687B2 JP2014526130A JP2014526130A JP5875687B2 JP 5875687 B2 JP5875687 B2 JP 5875687B2 JP 2014526130 A JP2014526130 A JP 2014526130A JP 2014526130 A JP2014526130 A JP 2014526130A JP 5875687 B2 JP5875687 B2 JP 5875687B2
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source
strings
gate
select gate
biasing
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JP2014529889A (ja
JP2014529889A5 (https=
Inventor
合田　晃
晃 合田
アフメド，シャフカトー
ハスナット，カーレッド
ケー． パラート，クリシュナ
ケー． パラート，クリシュナ
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マイクロン テクノロジー， インク．
マイクロン テクノロジー， インク．
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2014526130A 2011-08-15 2012-08-14 ソースゲートを含む装置および方法 Active JP5875687B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/210,194 US8797806B2 (en) 2011-08-15 2011-08-15 Apparatus and methods including source gates
US13/210,194 2011-08-15
PCT/US2012/050783 WO2013025710A1 (en) 2011-08-15 2012-08-14 Apparatus and methods including source gates

Publications (3)

Publication Number Publication Date
JP2014529889A JP2014529889A (ja) 2014-11-13
JP2014529889A5 JP2014529889A5 (https=) 2015-08-27
JP5875687B2 true JP5875687B2 (ja) 2016-03-02

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US (8) US8797806B2 (https=)
EP (2) EP2745295B1 (https=)
JP (1) JP5875687B2 (https=)
KR (2) KR102212154B1 (https=)
CN (1) CN103782344B (https=)
WO (1) WO2013025710A1 (https=)

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EP3706127A1 (en) 2020-09-09
US9378839B2 (en) 2016-06-28
US20160343438A1 (en) 2016-11-24
US12148474B2 (en) 2024-11-19
KR20180064571A (ko) 2018-06-14
KR20140059233A (ko) 2014-05-15
KR101866236B1 (ko) 2018-06-12
JP2014529889A (ja) 2014-11-13
EP2745295A4 (en) 2016-02-24
CN103782344A (zh) 2014-05-07
WO2013025710A1 (en) 2013-02-21
US20130044549A1 (en) 2013-02-21
US20220189552A1 (en) 2022-06-16
US10783967B2 (en) 2020-09-22
US9779816B2 (en) 2017-10-03
US20180122481A1 (en) 2018-05-03
US20140340963A1 (en) 2014-11-20
EP2745295B1 (en) 2020-04-22
US20250124982A1 (en) 2025-04-17
US8797806B2 (en) 2014-08-05
US20210174874A1 (en) 2021-06-10
US20190279715A1 (en) 2019-09-12
US11211126B2 (en) 2021-12-28
KR102212154B1 (ko) 2021-02-05
EP2745295A1 (en) 2014-06-25
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