JP5845143B2 - エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ - Google Patents
エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ Download PDFInfo
- Publication number
- JP5845143B2 JP5845143B2 JP2012146636A JP2012146636A JP5845143B2 JP 5845143 B2 JP5845143 B2 JP 5845143B2 JP 2012146636 A JP2012146636 A JP 2012146636A JP 2012146636 A JP2012146636 A JP 2012146636A JP 5845143 B2 JP5845143 B2 JP 5845143B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- epitaxial
- manufacturing
- single crystal
- crystal ingot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012146636A JP5845143B2 (ja) | 2012-06-29 | 2012-06-29 | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
| US13/925,267 US9425264B2 (en) | 2012-06-29 | 2013-06-24 | Method for growing an epitaxial film on a phosphorous-doped silicon wafer |
| KR1020130072869A KR101473784B1 (ko) | 2012-06-29 | 2013-06-25 | 에피택셜 실리콘 웨이퍼의 제조 방법 및, 에피택셜 실리콘 웨이퍼 |
| US14/850,194 US9755022B2 (en) | 2012-06-29 | 2015-09-10 | Epitaxial silicon wafer having reduced stacking faults |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012146636A JP5845143B2 (ja) | 2012-06-29 | 2012-06-29 | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014011293A JP2014011293A (ja) | 2014-01-20 |
| JP2014011293A5 JP2014011293A5 (enExample) | 2015-04-23 |
| JP5845143B2 true JP5845143B2 (ja) | 2016-01-20 |
Family
ID=49777243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012146636A Active JP5845143B2 (ja) | 2012-06-29 | 2012-06-29 | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US9425264B2 (enExample) |
| JP (1) | JP5845143B2 (enExample) |
| KR (1) | KR101473784B1 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12046469B2 (en) | 2020-02-19 | 2024-07-23 | Globalwafers Japan Co., Ltd. | Manufacturing method for semiconductor silicon wafer |
| US12308228B2 (en) | 2020-02-19 | 2025-05-20 | Globalwafers Japan Co., Ltd. | Manufacturing method for semiconductor silicon wafer |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10233562B2 (en) | 2013-04-24 | 2019-03-19 | Sumco Techxiv Corporation | Method for producing single crystal, and method for producing silicon wafer |
| CN106797207B (zh) * | 2014-12-17 | 2021-04-20 | 株式会社村田制作所 | 压电振子以及压电振动装置 |
| JP6477210B2 (ja) | 2015-04-30 | 2019-03-06 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
| JP6369388B2 (ja) * | 2015-05-13 | 2018-08-08 | 信越半導体株式会社 | シリコン単結晶基板の評価方法 |
| JP6432879B2 (ja) * | 2015-11-13 | 2018-12-05 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
| JP6447960B2 (ja) * | 2016-04-01 | 2019-01-09 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
| JP6372709B2 (ja) * | 2016-04-20 | 2018-08-15 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
| JP6598140B2 (ja) * | 2016-05-19 | 2019-10-30 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
| CN110603350B (zh) | 2017-04-06 | 2021-07-16 | 胜高股份有限公司 | 外延硅晶片的制造方法及外延硅晶片 |
| JP6897764B2 (ja) | 2017-04-25 | 2021-07-07 | 株式会社Sumco | シリコン単結晶の製造方法、および、エピタキシャルシリコンウェーハの製造方法 |
| CN108878310B (zh) * | 2017-05-12 | 2022-01-25 | 无锡华润安盛科技有限公司 | 芯片切割系统及其控制电路 |
| CN109509704B (zh) * | 2017-09-15 | 2024-08-09 | 胜高股份有限公司 | 外延硅晶片的制备方法 |
| JP6835006B2 (ja) * | 2018-02-16 | 2021-02-24 | 株式会社Sumco | エピタキシャルシリコンウェーハにおける積層欠陥の発生予測方法及びエピタキシャルシリコンウェーハの製造方法 |
| JP6713493B2 (ja) * | 2018-02-26 | 2020-06-24 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ |
| JP7491705B2 (ja) * | 2020-02-19 | 2024-05-28 | グローバルウェーハズ・ジャパン株式会社 | 半導体シリコンウェーハの製造方法 |
| EP4154320A1 (en) * | 2020-07-02 | 2023-03-29 | Atomera Incorporated | Method for making a semiconductor device using superlattices with different non-semiconductor thermal stabilities |
| CN112426527B (zh) * | 2020-11-30 | 2021-09-28 | 南京大学 | 一种具有抗肿瘤功能的二维红磷纳米材料 |
| JP7757916B2 (ja) * | 2021-11-04 | 2025-10-22 | 株式会社Sumco | シリコンウェーハおよびエピタキシャルシリコンウェーハ |
| JP7757917B2 (ja) * | 2021-11-04 | 2025-10-22 | 株式会社Sumco | シリコンウェーハおよびエピタキシャルシリコンウェーハ |
| JP7775800B2 (ja) * | 2022-09-08 | 2025-11-26 | 株式会社Sumco | シリコンウェーハおよびエピタキシャルシリコンウェーハ |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2790009B2 (ja) | 1992-12-11 | 1998-08-27 | 信越半導体株式会社 | シリコンエピタキシャル層の成長方法および成長装置 |
| JP3824675B2 (ja) | 1995-03-03 | 2006-09-20 | 有限会社デジタル・ウェーブ | 結晶製造装置 |
| EP0798765A3 (en) * | 1996-03-28 | 1998-08-05 | Shin-Etsu Handotai Company Limited | Method of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface |
| JP3407629B2 (ja) * | 1997-12-17 | 2003-05-19 | 信越半導体株式会社 | シリコン単結晶ウエーハの熱処理方法ならびにシリコン単結晶ウエーハ |
| JP4470231B2 (ja) * | 1999-03-31 | 2010-06-02 | 株式会社Sumco | 半導体シリコンウェーハの製造方法 |
| US6444027B1 (en) * | 2000-05-08 | 2002-09-03 | Memc Electronic Materials, Inc. | Modified susceptor for use in chemical vapor deposition process |
| US6663709B2 (en) * | 2001-06-26 | 2003-12-16 | Memc Electronic Materials, Inc. | Crystal puller and method for growing monocrystalline silicon ingots |
| JP4089809B2 (ja) | 2002-03-13 | 2008-05-28 | Sumco Techxiv株式会社 | 半導体ウェーハのエッジ部の酸化膜除去装置 |
| EP1576207A2 (en) | 2002-05-07 | 2005-09-21 | Microfabrica Inc. | Methods of and apparatus for molding structures |
| KR100603588B1 (ko) | 2004-06-09 | 2006-07-24 | 주식회사 하이닉스반도체 | 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법 |
| JP4815801B2 (ja) * | 2004-12-28 | 2011-11-16 | 信越半導体株式会社 | シリコンウエーハの研磨方法および製造方法および円板状ワークの研磨装置ならびにシリコンウエーハ |
| KR100827038B1 (ko) | 2006-12-21 | 2008-05-02 | 주식회사 실트론 | 헤이즈가 없는 실리콘 에피택셜 웨이퍼의 제조 방법 |
| JP5012554B2 (ja) | 2008-02-19 | 2012-08-29 | 株式会社Sumco | エピタキシャルウェーハの製造方法 |
| US8101508B2 (en) | 2008-03-05 | 2012-01-24 | Sumco Corporation | Silicon substrate and manufacturing method thereof |
| JP5347288B2 (ja) * | 2008-03-17 | 2013-11-20 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
| JP2010153631A (ja) * | 2008-12-25 | 2010-07-08 | Sumco Techxiv株式会社 | エピタキシャルシリコンウェーハとその製造方法 |
| DE102009010556B4 (de) | 2009-02-25 | 2013-11-07 | Siltronic Ag | Verfahren zur Herstellung von epitaxierten Siliciumscheiben |
| JP5463693B2 (ja) | 2009-03-03 | 2014-04-09 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
| JP5609025B2 (ja) | 2009-06-29 | 2014-10-22 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
| JP5246065B2 (ja) * | 2009-06-29 | 2013-07-24 | 株式会社Sumco | エピタキシャルシリコンウェーハとその製造方法 |
| JP2011029440A (ja) | 2009-07-27 | 2011-02-10 | Renesas Electronics Corp | 半導体装置の製造方法および条件出力システム |
| JP5445075B2 (ja) | 2009-11-27 | 2014-03-19 | 株式会社Sumco | エピタキシャルウェーハの製造方法 |
| JP6009237B2 (ja) | 2012-06-18 | 2016-10-19 | Sumco Techxiv株式会社 | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
-
2012
- 2012-06-29 JP JP2012146636A patent/JP5845143B2/ja active Active
-
2013
- 2013-06-24 US US13/925,267 patent/US9425264B2/en active Active
- 2013-06-25 KR KR1020130072869A patent/KR101473784B1/ko active Active
-
2015
- 2015-09-10 US US14/850,194 patent/US9755022B2/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12046469B2 (en) | 2020-02-19 | 2024-07-23 | Globalwafers Japan Co., Ltd. | Manufacturing method for semiconductor silicon wafer |
| US12308228B2 (en) | 2020-02-19 | 2025-05-20 | Globalwafers Japan Co., Ltd. | Manufacturing method for semiconductor silicon wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| US9425264B2 (en) | 2016-08-23 |
| KR101473784B1 (ko) | 2014-12-17 |
| JP2014011293A (ja) | 2014-01-20 |
| US20150380493A1 (en) | 2015-12-31 |
| US9755022B2 (en) | 2017-09-05 |
| US20140001605A1 (en) | 2014-01-02 |
| KR20140002509A (ko) | 2014-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5845143B2 (ja) | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ | |
| CN107533959B (zh) | 外延硅晶片的制造方法 | |
| JP5890587B2 (ja) | 単結晶の製造方法およびシリコンウェーハの製造方法 | |
| JP2014011293A5 (enExample) | ||
| JP5892232B1 (ja) | 単結晶の製造方法およびシリコンウェーハの製造方法 | |
| JP5533869B2 (ja) | エピタキシャルシリコンウェーハとその製造方法 | |
| JP2025146998A (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
| WO2021166895A1 (ja) | 半導体シリコンウェーハの製造方法 | |
| JP4510997B2 (ja) | シリコン半導体基板およびその製造方法 | |
| JP7757917B2 (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
| CN109509704B (zh) | 外延硅晶片的制备方法 | |
| JP7775800B2 (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
| JP2025157587A (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
| JP2023070019A (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
| KR20250016376A (ko) | 실리콘 웨이퍼 및 에피택셜 실리콘 웨이퍼 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150305 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150305 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20150305 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20150501 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150609 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150729 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151027 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151120 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5845143 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |