JP5759285B2 - ストリング選択線及びビット線の改善されたコンタクトレイアウトを有する3次元メモリアレイ - Google Patents
ストリング選択線及びビット線の改善されたコンタクトレイアウトを有する3次元メモリアレイ Download PDFInfo
- Publication number
- JP5759285B2 JP5759285B2 JP2011140819A JP2011140819A JP5759285B2 JP 5759285 B2 JP5759285 B2 JP 5759285B2 JP 2011140819 A JP2011140819 A JP 2011140819A JP 2011140819 A JP2011140819 A JP 2011140819A JP 5759285 B2 JP5759285 B2 JP 5759285B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor material
- stacks
- conductive
- memory
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims description 156
- 239000000463 material Substances 0.000 claims description 227
- 239000004065 semiconductor Substances 0.000 claims description 207
- 238000003860 storage Methods 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011810 insulating material Substances 0.000 claims description 16
- 230000000903 blocking effect Effects 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 149
- 238000000034 method Methods 0.000 description 50
- 230000008569 process Effects 0.000 description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 35
- 238000010586 diagram Methods 0.000 description 31
- 108091006146 Channels Proteins 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 17
- 230000006870 function Effects 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 239000007943 implant Substances 0.000 description 13
- 229910021332 silicide Inorganic materials 0.000 description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 13
- 235000012239 silicon dioxide Nutrition 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 13
- 238000000151 deposition Methods 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000001459 lithography Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 239000002131 composite material Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 238000005755 formation reaction Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002070 nanowire Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002071 nanotube Substances 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 241001279686 Allium moly Species 0.000 description 1
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
11,12,13,14 半導体材料帯片
15 メモリ材料の層
16,17 導電線
18,19 シリサイドの層
20 トレンチ
21,22,23,24 絶縁材料
25,26 活性領域
30,31,32,33,34,35 モリセル
40,41,42,43,44,45 メモリセル
51,52,53,54,55,56 半導体材料帯片
60,61 導電線
60−1,60−2,60−3 拡張部
WLn 第1のワード線
WLn+1 第2のワード線
BLn,BLn+1,BLn+2 ビット線
Claims (10)
- 集積回路基板と、
第1のビット線コンタクト及び第2のビット線コンタクトを有する複数のビット線コンタクトと、
前記集積回路基板から延びるとともに、当該集積回路基板上に配置されて、絶縁材料により分離された、第1の平面に沿って延在する第1の半導体材料帯片、及び、当該第1の平面と略並行な第2の平面に沿って延在する第2の半導体材料帯片を、各々が有する第1のスタックと第2のスタックとを含む複数の半導体材料帯片スタックと、
2つの前記第1の半導体材料帯片と前記第1のビット線コンタクトとにそれぞれ接続するとともに、当該第1の半導体材料帯片の端部に位置付けられて、前記集積回路基板と略並行に延在する第1段と、2つの前記第2の半導体材料帯片と前記第2のビット線コンタクトとにそれぞれ接続するとともに、当該第2の半導体材料帯片の端部に位置付けられて、前記集積回路基板と略並行に延在する第2段とを含む階段構造と、
界面領域の3次元アレイが、前記半導体材料帯片の表面との間の交点に確立されるように、前記複数のスタックの上に直交して配列され、前記スタックに共形の表面を有する複数の導電線と、
前記複数の半導体材料帯片及び前記複数の導電線を介してアクセス可能なメモリセルの3次元アレイを確立する、前記界面領域の記憶素子と、
を備えるメモリデバイス。 - 前記複数のスタックの前記半導体材料帯片及び前記複数の導電線に、前記メモリセルにアクセスするために結合された復号化回路を含むことを特徴とする請求項1に記載のメモリデバイス。
- 前記記憶素子は、アンチヒューズ又は電荷蓄積構造又は埋込みチャネル電荷蓄積トランジスタを含むことを特徴とする請求項1に記載のメモリデバイス。
- 前記複数のスタックの前記複数の半導体材料帯片又は前記複数の導電線は、ドープされた半導体を含むことを特徴とする請求項1に記載のメモリデバイス。
- 前記記憶素子は、前記複数の導電線と前記複数のスタックとの間にメモリ材料の共通層の部分を含むことを特徴とする請求項1に記載のメモリデバイス。
- トンネル層と、電荷トラップ層と、阻止層を前記複数の導電線と前記複数のスタックとの間に含み、前記トンネル層と、前記電荷トラップ層と、前記阻止層を組み合わせて前記界面領域に前記記憶素子を形成することを特徴とする請求項1に記載のメモリデバイス。
- 前記複数のスタックの上に前記半導体材料帯片に並行して配置された複数のビット線を含み、前記複数のビット線のうちの異なるビット線が、前記複数のビット線コンタクト及び前記階段構造を介して前記複数のスタックのうちの異なる平面位置に電気的に接続されることを特徴とする請求項1に記載のメモリデバイス。
- 集積回路基板と、
絶縁材料によって複数の平面位置のうちの異なる平面位置に分離された少なくとも2つの半導体材料帯片を含み、前記半導体材料帯片が、相互接続される前記複数の平面位置のうちの同一平面位置を共有する、前記集積回路基板から延びる複数の半導体材料帯片スタックと、
界面領域の3次元アレイが、前記半導体材料帯片の表面との間の交点に確立されるように、前記複数のスタックの上に直交して配列され、前記スタックに共形の表面を有する第1の複数の導電線と、
前記複数の半導体材料帯片及び前記第1の複数の導電線を介してアクセス可能なメモリセルの3次元アレイを確立する、前記界面領域の記憶素子と、
それぞれが前記複数のスタックのうちの異なるスタックの上に設けられる複数の導電性共形構造と、
それぞれが前記複数の導電性共形構造のうちの異なる導電性共形構造に電気的に接続される、前記複数のスタックの上に前記半導体材料帯片に並行して配置された第2の複数の導電線と、
それぞれが前記第2の複数の導電線のうちの異なる導電線に接続された、前記第1の導電線の上に並行して配置された第3の複数の導電線と、
を備えるメモリデバイス。 - 集積回路基板から延びる複数の半導体材料帯片スタックと当該集積回路基板上の階段構造とを形成するステップであって、前記複数の半導体材料帯片スタックは、前記集積回路基板上に配置されるとともに、絶縁材料により分離された、第1の平面に沿って延在する第1の半導体材料帯片、及び、当該第1の平面と略並行な第2の平面に沿って延在する第2の半導体材料帯片を、各々が有する第1のスタックと第2のスタックとを含み、前記階段構造は、2つの前記第1の半導体材料帯片と前記第1のビット線コンタクトとにそれぞれ接続するとともに、当該第1の半導体材料帯片の端部に位置付けられて、前記集積回路基板と略並行に延在する第1段と、2つの前記第2の半導体材料帯片と前記第2のビット線コンタクトとにそれぞれ接続するとともに、当該第2の半導体材料帯片の端部に位置付けられて、前記集積回路基板と略並行に延在する第2段とを含んでなるステップと、
界面領域の3次元アレイが、前記半導体材料帯片の表面との間の交点に確立されるように、前記複数のスタックの上に直交して配列され、前記スタックに共形の表面を有する第1の複数の導電線を形成するステップと、
前記複数の半導体材料帯片及び前記第1の複数の導電線を介してアクセス可能なメモリセルの3次元アレイを確立する、前記界面領域の記憶素子を形成するステップと、
を含むメモリデバイスを製造する方法。 - 絶縁材料によって複数の平面位置のうちの異なる平面位置に分離された少なくとも2つの半導体材料帯片を含み、前記半導体材料帯片が、階段構造によって複数のビット線コンタクトのうちの同一ビット線コンタクトに接続される前記複数の平面位置のうちの同一平面位置を共有して、前記階段構造の段が前記半導体材料帯片の端部に位置するようになっている、前記集積回路基板から延びる複数の半導体材料帯片スタックを形成するステップと、
界面領域の3次元アレイが、前記半導体材料帯片の表面との間の交点に確立されるように、前記複数のスタックの上に直交して配列され、前記スタックに共形の表面を有する第1の複数の導電線を形成するステップと、
前記複数の半導体材料帯片及び前記第1の複数の導電線を介してアクセス可能なメモリセルの3次元アレイを確立する、前記界面領域の記憶素子を形成するステップと、
それぞれが前記複数のスタックのうちの異なるスタックの上に設けられる複数の導電性共形構造を形成するステップと、
それぞれが前記複数の導電性共形構造のうちの異なる導電性共形構造に電気的に接続された、前記複数のスタックの上に前記半導体材料帯片に並行して配置された第2の複数の導電線を形成するステップと、
それぞれが前記第2の複数の導電線のうちの異なる導電線に接続された、前記第1の導電線の上に並行して配置された第3の複数の導電線を形成するステップと、
を含むメモリデバイスを製造する方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US36162310P | 2010-07-06 | 2010-07-06 | |
US61/361,623 | 2010-07-06 | ||
US13/018,110 US8890233B2 (en) | 2010-07-06 | 2011-01-31 | 3D memory array with improved SSL and BL contact layout |
US13/018,110 | 2011-01-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012019211A JP2012019211A (ja) | 2012-01-26 |
JP5759285B2 true JP5759285B2 (ja) | 2015-08-05 |
Family
ID=45437980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011140819A Active JP5759285B2 (ja) | 2010-07-06 | 2011-06-24 | ストリング選択線及びビット線の改善されたコンタクトレイアウトを有する3次元メモリアレイ |
Country Status (3)
Country | Link |
---|---|
US (2) | US8890233B2 (ja) |
JP (1) | JP5759285B2 (ja) |
KR (1) | KR101719374B1 (ja) |
Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
JP5651415B2 (ja) | 2010-09-21 | 2015-01-14 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8486791B2 (en) | 2011-01-19 | 2013-07-16 | Macronix International Co., Ltd. | Mufti-layer single crystal 3D stackable memory |
KR20120137862A (ko) * | 2011-06-13 | 2012-12-24 | 삼성전자주식회사 | 3차원 더블 크로스 포인트 어레이를 갖는 반도체 메모리 소자 및 그 제조방법 |
US8951862B2 (en) * | 2012-01-10 | 2015-02-10 | Macronix International Co., Ltd. | Damascene word line |
EP2631947B1 (en) * | 2012-02-23 | 2014-12-31 | Macronix International Co., Ltd. | Damascene word line |
CN103295966B (zh) * | 2012-02-24 | 2016-01-27 | 旺宏电子股份有限公司 | 形成三维非易失存储单元阵列的方法 |
GB2502127A (en) * | 2012-05-17 | 2013-11-20 | Kymab Ltd | Multivalent antibodies and in vivo methods for their production |
JP6709051B2 (ja) * | 2012-03-31 | 2020-06-10 | ロンギチュード フラッシュ メモリー ソリューションズ リミテッド | 多層酸窒化物層を有する酸化物−窒化物−酸化物積層体 |
US8987098B2 (en) | 2012-06-19 | 2015-03-24 | Macronix International Co., Ltd. | Damascene word line |
US9093152B2 (en) * | 2012-10-26 | 2015-07-28 | Micron Technology, Inc. | Multiple data line memory and methods |
US9502349B2 (en) | 2014-01-17 | 2016-11-22 | Macronix International Co., Ltd. | Separated lower select line in 3D NAND architecture |
US9224474B2 (en) | 2013-01-09 | 2015-12-29 | Macronix International Co., Ltd. | P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals |
KR102059196B1 (ko) * | 2013-01-11 | 2019-12-24 | 에프아이오 세미컨덕터 테크놀로지스, 엘엘씨 | 3차원 반도체 장치 및 그 제조 방법 |
KR102025111B1 (ko) * | 2013-01-11 | 2019-09-25 | 삼성전자주식회사 | 전류 경로 선택 구조를 포함하는 3차원 반도체 장치 및 그 동작 방법 |
KR102024710B1 (ko) * | 2013-01-11 | 2019-09-24 | 삼성전자주식회사 | 3차원 반도체 장치의 스트링 선택 구조 |
US9171636B2 (en) | 2013-01-29 | 2015-10-27 | Macronix International Co. Ltd. | Hot carrier generation and programming in NAND flash |
US9111591B2 (en) | 2013-02-22 | 2015-08-18 | Micron Technology, Inc. | Interconnections for 3D memory |
KR102160290B1 (ko) | 2013-02-28 | 2020-09-25 | 삼성전자주식회사 | 불휘발성 메모리 및 불휘발성 메모리의 읽기 방법 |
US11222697B2 (en) | 2013-02-28 | 2022-01-11 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory |
US8976600B2 (en) | 2013-03-11 | 2015-03-10 | Macronix International Co., Ltd. | Word line driver circuit for selecting and deselecting word lines |
US9214351B2 (en) | 2013-03-12 | 2015-12-15 | Macronix International Co., Ltd. | Memory architecture of thin film 3D array |
US9123778B2 (en) | 2013-03-13 | 2015-09-01 | Macronix International Co., Ltd. | Damascene conductor for 3D array |
US9379126B2 (en) | 2013-03-14 | 2016-06-28 | Macronix International Co., Ltd. | Damascene conductor for a 3D device |
US9147493B2 (en) | 2013-06-17 | 2015-09-29 | Micron Technology, Inc. | Shielded vertically stacked data line architecture for memory |
US9117526B2 (en) | 2013-07-08 | 2015-08-25 | Macronix International Co., Ltd. | Substrate connection of three dimensional NAND for improving erase performance |
US9337210B2 (en) | 2013-08-12 | 2016-05-10 | Micron Technology, Inc. | Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors |
KR102066925B1 (ko) | 2013-08-30 | 2020-01-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9099538B2 (en) | 2013-09-17 | 2015-08-04 | Macronix International Co., Ltd. | Conductor with a plurality of vertical extensions for a 3D device |
US9508736B2 (en) * | 2013-10-17 | 2016-11-29 | Cypress Semiconductor Corporation | Three-dimensional charge trapping NAND cell with discrete charge trapping film |
TW201539454A (zh) * | 2013-12-05 | 2015-10-16 | Conversant Intellectual Property Man Inc | 具有電荷儲存節點隔離之三維非揮發性記憶體 |
US9373632B2 (en) | 2014-01-17 | 2016-06-21 | Macronix International Co., Ltd. | Twisted array design for high speed vertical channel 3D NAND memory |
US9679849B1 (en) | 2014-01-17 | 2017-06-13 | Macronix International Co., Ltd. | 3D NAND array with sides having undulating shapes |
US9263577B2 (en) | 2014-04-24 | 2016-02-16 | Micron Technology, Inc. | Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9721964B2 (en) | 2014-06-05 | 2017-08-01 | Macronix International Co., Ltd. | Low dielectric constant insulating material in 3D memory |
US9947665B2 (en) * | 2014-07-15 | 2018-04-17 | Macronix International Co., Ltd. | Semiconductor structure having dielectric layer and conductive strip |
US9589642B2 (en) | 2014-08-07 | 2017-03-07 | Macronix International Co., Ltd. | Level shifter and decoder for memory |
JP6266479B2 (ja) | 2014-09-12 | 2018-01-24 | 東芝メモリ株式会社 | メモリシステム |
US9159829B1 (en) | 2014-10-07 | 2015-10-13 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
US9589979B2 (en) * | 2014-11-19 | 2017-03-07 | Macronix International Co., Ltd. | Vertical and 3D memory devices and methods of manufacturing the same |
KR102275540B1 (ko) | 2014-12-18 | 2021-07-13 | 삼성전자주식회사 | 가변 저항 메모리 소자 |
US9741731B2 (en) * | 2014-12-22 | 2017-08-22 | Macronix International Co., Ltd. | Three dimensional stacked semiconductor structure |
CN105789209B (zh) * | 2014-12-23 | 2018-12-28 | 旺宏电子股份有限公司 | 三维叠层半导体结构及其制造方法 |
US9305929B1 (en) | 2015-02-17 | 2016-04-05 | Micron Technology, Inc. | Memory cells |
CN106158035B (zh) * | 2015-04-09 | 2019-09-27 | 旺宏电子股份有限公司 | 存储器装置 |
TWI569405B (zh) * | 2015-04-14 | 2017-02-01 | 旺宏電子股份有限公司 | 記憶體裝置及其應用 |
US9478259B1 (en) | 2015-05-05 | 2016-10-25 | Macronix International Co., Ltd. | 3D voltage switching transistors for 3D vertical gate memory array |
US10500285B2 (en) | 2015-05-15 | 2019-12-10 | Zhuhai Beihai Biotech Co., Ltd. | Docetaxel and human serum albumin complexes |
US9859007B2 (en) | 2015-06-17 | 2018-01-02 | Macronix International Co., Ltd. | Non-volatile memory device having multiple string select lines |
US10134982B2 (en) | 2015-07-24 | 2018-11-20 | Micron Technology, Inc. | Array of cross point memory cells |
US9853211B2 (en) * | 2015-07-24 | 2017-12-26 | Micron Technology, Inc. | Array of cross point memory cells individually comprising a select device and a programmable device |
US9911693B2 (en) * | 2015-08-28 | 2018-03-06 | Micron Technology, Inc. | Semiconductor devices including conductive lines and methods of forming the semiconductor devices |
US10121553B2 (en) | 2015-09-30 | 2018-11-06 | Sunrise Memory Corporation | Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays |
US9892800B2 (en) | 2015-09-30 | 2018-02-13 | Sunrise Memory Corporation | Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates |
US9899387B2 (en) | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9570550B1 (en) | 2016-01-05 | 2017-02-14 | International Business Machines Corporation | Stacked nanowire semiconductor device |
CN105529332B (zh) * | 2016-01-12 | 2018-12-11 | 清华大学 | 一种解码型垂直栅3d nand及其形成方法 |
CN105788632B (zh) * | 2016-02-26 | 2019-04-02 | 江苏时代全芯存储科技有限公司 | 记忆体电路 |
TWI582965B (zh) * | 2016-06-20 | 2017-05-11 | 旺宏電子股份有限公司 | 具縮小尺寸串列選擇線元件之三維半導體元件 |
US11419842B2 (en) | 2016-10-27 | 2022-08-23 | Zhuhai Beihai Biotech Co., Ltd. | Neutral pH compositions of Docetaxel and human serum albumin |
US10396145B2 (en) | 2017-01-12 | 2019-08-27 | Micron Technology, Inc. | Memory cells comprising ferroelectric material and including current leakage paths having different total resistances |
US10762939B2 (en) * | 2017-07-01 | 2020-09-01 | Intel Corporation | Computer memory |
US10490602B2 (en) * | 2017-09-21 | 2019-11-26 | Micron Technology, Inc. | Three dimensional memory arrays |
US20190206732A1 (en) * | 2017-12-29 | 2019-07-04 | Macronix International Co., Ltd. | Three-dimensional semiconductor device and method for manufacturing the same |
CN110010619B (zh) * | 2018-01-04 | 2021-01-05 | 旺宏电子股份有限公司 | 三维半导体元件及其制造方法 |
US10957392B2 (en) | 2018-01-17 | 2021-03-23 | Macronix International Co., Ltd. | 2D and 3D sum-of-products array for neuromorphic computing system |
TWI646664B (zh) * | 2018-03-13 | 2019-01-01 | 旺宏電子股份有限公司 | 半導體結構及其製造方法 |
US10748903B2 (en) * | 2018-04-19 | 2020-08-18 | Tc Lab, Inc. | Multi-layer random access memory and methods of manufacture |
JP7442459B2 (ja) * | 2018-04-24 | 2024-03-04 | アプライド マテリアルズ インコーポレイテッド | カーボンハードマスクのプラズマ強化化学気相堆積 |
US10840254B2 (en) | 2018-05-22 | 2020-11-17 | Macronix International Co., Ltd. | Pitch scalable 3D NAND |
US11138497B2 (en) | 2018-07-17 | 2021-10-05 | Macronix International Co., Ltd | In-memory computing devices for neural networks |
US10580791B1 (en) | 2018-08-21 | 2020-03-03 | Micron Technology, Inc. | Semiconductor device structures, semiconductor devices, and electronic systems |
US11636325B2 (en) | 2018-10-24 | 2023-04-25 | Macronix International Co., Ltd. | In-memory data pooling for machine learning |
US11562229B2 (en) | 2018-11-30 | 2023-01-24 | Macronix International Co., Ltd. | Convolution accelerator using in-memory computation |
US11934480B2 (en) | 2018-12-18 | 2024-03-19 | Macronix International Co., Ltd. | NAND block architecture for in-memory multiply-and-accumulate operations |
KR102554712B1 (ko) * | 2019-01-11 | 2023-07-14 | 삼성전자주식회사 | 반도체 소자 |
US11119674B2 (en) | 2019-02-19 | 2021-09-14 | Macronix International Co., Ltd. | Memory devices and methods for operating the same |
KR20200111551A (ko) | 2019-03-19 | 2020-09-29 | 삼성전자주식회사 | 수직형 메모리 장치 |
US11132176B2 (en) * | 2019-03-20 | 2021-09-28 | Macronix International Co., Ltd. | Non-volatile computing method in flash memory |
JP2020155714A (ja) * | 2019-03-22 | 2020-09-24 | キオクシア株式会社 | 半導体記憶装置 |
US11037947B2 (en) | 2019-04-15 | 2021-06-15 | Macronix International Co., Ltd. | Array of pillars located in a uniform pattern |
US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
WO2021048928A1 (ja) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | メモリデバイス |
US11508746B2 (en) | 2019-10-25 | 2022-11-22 | Micron Technology, Inc. | Semiconductor device having a stack of data lines with conductive structures on both sides thereof |
KR20210052660A (ko) | 2019-10-29 | 2021-05-11 | 삼성전자주식회사 | 3차원 반도체 메모리 소자 |
KR20210061071A (ko) | 2019-11-19 | 2021-05-27 | 삼성전자주식회사 | 메모리 장치 |
US11605588B2 (en) | 2019-12-20 | 2023-03-14 | Micron Technology, Inc. | Memory device including data lines on multiple device levels |
US11074975B1 (en) * | 2020-04-07 | 2021-07-27 | Macronix International Co., Ltd. | Non-volatile register and implementation of non-volatile register |
US11765892B2 (en) * | 2020-10-21 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional memory device and method of manufacture |
TWI784335B (zh) * | 2020-10-30 | 2022-11-21 | 台灣奈米碳素股份有限公司 | 三維半導體二極體裝置的製造方法 |
US11652148B2 (en) * | 2021-05-13 | 2023-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of selective film deposition and semiconductor feature made by the method |
US11825649B2 (en) * | 2021-09-01 | 2023-11-21 | Nanya Technology Corporation | Semiconductor device with programmable unit and method for fabricating the same |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034882A (en) | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
CN101179079B (zh) | 2000-08-14 | 2010-11-03 | 矩阵半导体公司 | 密集阵列和电荷存储器件及其制造方法 |
US7081377B2 (en) | 2002-06-27 | 2006-07-25 | Sandisk 3D Llc | Three-dimensional memory |
US6879505B2 (en) | 2003-03-31 | 2005-04-12 | Matrix Semiconductor, Inc. | Word line arrangement having multi-layer word line segments for three-dimensional memory array |
DE20321085U1 (de) | 2003-10-23 | 2005-12-29 | Commissariat à l'Energie Atomique | Phasenwechselspeicher, Phasenwechselspeicheranordnung, Phasenwechselspeicherzelle, 2D-Phasenwechselspeicherzellen-Array, 3D-Phasenwechselspeicherzellen-Array und Elektronikbaustein |
US6906940B1 (en) | 2004-02-12 | 2005-06-14 | Macronix International Co., Ltd. | Plane decoding method and device for three dimensional memories |
US7378702B2 (en) | 2004-06-21 | 2008-05-27 | Sang-Yun Lee | Vertical memory device structures |
KR100850508B1 (ko) * | 2006-08-04 | 2008-08-05 | 삼성전자주식회사 | 3차원적으로 배열된 메모리 셀 트랜지스터들을 구비하는낸드 플래시 메모리 장치 |
JP2008078404A (ja) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体メモリ及びその製造方法 |
KR101169396B1 (ko) | 2006-12-22 | 2012-07-30 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 동작 방법 |
JP2008192708A (ja) * | 2007-02-01 | 2008-08-21 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP5091526B2 (ja) * | 2007-04-06 | 2012-12-05 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
US7816727B2 (en) * | 2007-08-27 | 2010-10-19 | Macronix International Co., Ltd. | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS |
KR20090037690A (ko) | 2007-10-12 | 2009-04-16 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
KR20090079694A (ko) | 2008-01-18 | 2009-07-22 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
KR101539697B1 (ko) * | 2008-06-11 | 2015-07-27 | 삼성전자주식회사 | 수직형 필라를 활성영역으로 사용하는 3차원 메모리 장치,그 제조 방법 및 그 동작 방법 |
US7796437B2 (en) * | 2008-09-23 | 2010-09-14 | Sandisk 3D Llc | Voltage regulator with reduced sensitivity of output voltage to change in load current |
US8829646B2 (en) | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
KR101028993B1 (ko) * | 2009-06-30 | 2011-04-12 | 주식회사 하이닉스반도체 | 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법 |
KR101028994B1 (ko) * | 2009-09-07 | 2011-04-12 | 주식회사 하이닉스반도체 | 3차원 구조를 갖는 비휘발성 메모리 소자 및 그 제조 방법 |
-
2011
- 2011-01-31 US US13/018,110 patent/US8890233B2/en active Active
- 2011-06-24 JP JP2011140819A patent/JP5759285B2/ja active Active
- 2011-07-06 KR KR1020110066654A patent/KR101719374B1/ko active IP Right Grant
-
2014
- 2014-10-14 US US14/513,721 patent/US9024374B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8890233B2 (en) | 2014-11-18 |
KR101719374B1 (ko) | 2017-03-23 |
JP2012019211A (ja) | 2012-01-26 |
US20120007167A1 (en) | 2012-01-12 |
US20150054057A1 (en) | 2015-02-26 |
US9024374B2 (en) | 2015-05-05 |
KR20120004346A (ko) | 2012-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5759285B2 (ja) | ストリング選択線及びビット線の改善されたコンタクトレイアウトを有する3次元メモリアレイ | |
US8467219B2 (en) | Integrated circuit self aligned 3D memory array and manufacturing method | |
JP5977003B2 (ja) | メモリストリングにダイオードを有する3次元アレイのメモリアーキテクチャ | |
US8503213B2 (en) | Memory architecture of 3D array with alternating memory string orientation and string select structures | |
US8811077B2 (en) | Memory architecture of 3D array with improved uniformity of bit line capacitances | |
TWI462116B (zh) | 具有改良串列選擇線和位元線接觸佈局的三維記憶陣列 | |
TWI493545B (zh) | 三維nor型陣列之記憶體架構 | |
US9214471B2 (en) | Memory architecture of 3D array with diode in memory string | |
KR101975812B1 (ko) | 메모리 스트링 내에 다이오드를 구비하는 3차원 어레이의 메모리 구조 | |
US9721668B2 (en) | 3D non-volatile memory array with sub-block erase architecture | |
TWI490862B (zh) | 改良位元線電容單一性之3d陣列記憶體結構 | |
US20160260733A1 (en) | U-shaped vertical thin-channel memory | |
US20110286283A1 (en) | 3d two-bit-per-cell nand flash memory | |
US9324728B2 (en) | Three-dimensional vertical gate NAND flash memory including dual-polarity source pads |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140411 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141209 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141211 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150309 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150602 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150605 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5759285 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |