JP5720788B2 - 超接合半導体装置 - Google Patents
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Description
以下、本発明の実施の形態1にかかる超接合半導体装置について、SJ−MOSFETを例に詳細に説明する。図1は、本発明の実施の形態1にかかる超接合半導体装置の構成を示す断面図である。図3は、本発明の実施の形態1にかかる超接合半導体装置の構成を示す平面図である。図1は、図3のA−A’線における断面図である。図1,3において図2と共通の部分には同一の符号を付けている。図1,3に示す本発明の実施の形態1にかかる超接合半導体装置は、温度検出用素子を備えるSJ−MOSFET200である。このSJ−MOSFET200は、同一のn+半導体基板6上に、MOSゲート構造10が設けられた素子活性部1と、ダイオード3からなる温度検出用素子(以下、温度検出ダイオード3とする)が設けられた温度検出領域4とを備える。
図4は、本発明の実施の形態2にかかる超接合半導体装置の構成を示す平面図である。実施の形態2にかかるSJ−MOSFET300が実施の形態1にかかるSJ−MOSFET200とは異なる点は、温度検出領域4のストライプ状の平面パターンと素子活性部1のストライプ状の平面パターンとが直交している点である。図4に示すように、温度検出領域4内の微細SJセル141がnドリフト領域141b及びp仕切り領域141aが並ぶ方向と直交する方向に延びるストライプ状の平面パターンである点は、図3に示す微細SJセルと同様である。微細SJセル141の平面パターンのストライプの延びる方向が素子活性部1のメインSJセル13の平面パターンのストライプの延びる方向と直交する点が、図3に示す微細SJセルと異なる。図4に示す微細SJセルの構成とした場合においても、実施の形態1と同様の効果が得られる。微細SJセル141とメインSJセル13とのストライプ状の平面パターンを相互に直交させることにより、SJセルの繰り返しピッチの設計自由度が上がり、微細化が容易になるとともに、より高耐圧化が容易になる。
図5は、本発明の実施の形態3にかかる超接合半導体装置の構成を示す平面図である。実施の形態3にかかるSJ−MOSFET400が実施の形態1,2にかかるSJ−MOSFET200,300とは異なる点は、温度検出領域4内の微細SJセル151が格子状の平面パターンである点である。格子状の平面パターンとは、例えばnドリフト領域151b内に、矩形状の平面形状を有するp仕切り領域151aをマトリクス状に配置した平面パターンである。実施の形態3においても微細SJセル151は格子状の平面パターンの配列ピッチをメインSJセル13のストライプ状の平面パターンの配列ピッチより狭くすることにより、実施の形態1と同様の効果が得られる。
2 耐圧構造部
3 温度検出ダイオード
4 温度検出領域
5 絶縁膜
6 n+半導体基板
7 ドレイン電極
8 層間絶縁膜
10 MOSゲート構造
12 ドリフト層
13 メインSJセル
13a p仕切り領域
13b nドリフト領域
14 pベース領域
15 n+ソース領域
16 ゲート電極
17 ソース電極
131,141,151 微細SJセル
131a,141a,151a p仕切り領域
131b,141b,151b nドリフト領域
200,300,400 SJ−MOSFET
Claims (8)
- 第1導電型の高不純物濃度の半導体基板の一方の主面の垂直方向に配向する第1導電型半導体領域と第2導電型半導体領域とが、前記半導体基板の主面に平行な方向に所定のピッチで繰り返し交互に隣接する並列pn層をドリフト層として備え、前記第1導電型半導体領域にオン状態で電流を流し、オフ状態では前記並列pn層を空乏化して電圧を阻止する構成を有する超接合半導体装置であって、
主電流経路となる素子活性部と、
前記素子活性部内に設けられた、前記並列pn層の前記第1導電型半導体領域と前記第2導電型半導体領域とのピッチが前記所定のピッチよりも狭い温度検出領域と、
前記温度検出領域の前記並列pn層の表面に絶縁膜を介して設けられた第1導電型半導体層と、
前記温度検出領域の前記並列pn層の表面に絶縁膜を介して設けられ、前記第1導電型半導体層と接してpn接合を構成するように配置された第2導電型半導体層と、
前記第1導電型半導体層と前記第2導電型半導体層とを主たる半導体層とする温度検出用素子と、
を備えることを特徴とする超接合半導体装置。 - 前記素子活性部は絶縁ゲート構造を備え、
前記温度検出領域内の前記並列pn層の表面の前記絶縁膜が、前記絶縁ゲート構造を構成するゲート絶縁膜よりも厚いことを特徴とする請求項1に記載の超接合半導体装置。 - 前記素子活性部を囲むように前記素子活性部の外周に配置され、耐圧を保持する耐圧構造部をさらに備え、
前記温度検出領域内の前記並列pn層の表面の前記絶縁膜が、前記耐圧構造部の表面を保護するフィールド絶縁膜と同程度の厚さを有することを特徴とする請求項2に記載の超接合半導体装置。 - 前記温度検出領域内の前記並列pn層の平面パターンが、前記第1導電型半導体領域と前記第2導電型半導体領域とが並ぶ方向に直交する方向に延びるストライプ状であることを特徴とする請求項1に記載の超接合半導体装置。
- 前記素子活性部内の前記並列pn層の平面パターンが、前記第1導電型半導体領域と前記第2導電型半導体領域とが並ぶ方向に直交する方向に延びるストライプ状であり、
前記温度検出領域内の前記並列pn層のストライプ状の平面パターンが、前記素子活性部内の前記並列pn層のストライプ状の平面パターンに対して平行であることを特徴とする請求項4に記載の超接合半導体装置。 - 前記素子活性部内の前記並列pn層の平面パターンが、前記第1導電型半導体領域と前記第2導電型半導体領域とが並ぶ方向に直交する方向に延びるストライプ状であり、
前記温度検出領域内の前記並列pn層のストライプ状の平面パターンが、前記素子活性部内の前記並列pn層のストライプ状の平面パターンに対して直交していることを特徴とする請求項4に記載の超接合半導体装置。 - 前記温度検出領域内の前記並列pn層は、前記第1導電型半導体領域内に前記第2導電型半導体領域がマトリクス状に配置された平面パターンを有することを特徴とする請求項1に記載の超接合半導体装置。
- 前記温度検出用素子がポリシリコンであることを特徴とする請求項1〜7のいずれか一つに記載の超接合半導体装置。
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US (1) | US20140061644A1 (ja) |
EP (1) | EP2736072B1 (ja) |
JP (1) | JP5720788B2 (ja) |
CN (1) | CN103650141B (ja) |
TW (1) | TWI567975B (ja) |
WO (1) | WO2013015014A1 (ja) |
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US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
JP6197294B2 (ja) * | 2013-01-16 | 2017-09-20 | 富士電機株式会社 | 半導体素子 |
US9891640B2 (en) | 2013-06-14 | 2018-02-13 | Infineon Technologies Ag | Sensing element for semiconductor |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
JP6323556B2 (ja) | 2014-07-04 | 2018-05-16 | 富士電機株式会社 | 半導体装置 |
CN106575666B (zh) | 2014-08-19 | 2021-08-06 | 维西埃-硅化物公司 | 超结金属氧化物半导体场效应晶体管 |
JP6503202B2 (ja) * | 2015-03-12 | 2019-04-17 | エイブリック株式会社 | 半導体装置 |
US9881997B2 (en) * | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
JP6512025B2 (ja) | 2015-08-11 | 2019-05-15 | 富士電機株式会社 | 半導体素子及び半導体素子の製造方法 |
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WO2013015014A1 (ja) | 2013-01-31 |
EP2736072A4 (en) | 2015-02-25 |
TWI567975B (zh) | 2017-01-21 |
US20140061644A1 (en) | 2014-03-06 |
TW201316506A (zh) | 2013-04-16 |
CN103650141B (zh) | 2016-06-29 |
EP2736072A1 (en) | 2014-05-28 |
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