JP5710394B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5710394B2 JP5710394B2 JP2011137321A JP2011137321A JP5710394B2 JP 5710394 B2 JP5710394 B2 JP 5710394B2 JP 2011137321 A JP2011137321 A JP 2011137321A JP 2011137321 A JP2011137321 A JP 2011137321A JP 5710394 B2 JP5710394 B2 JP 5710394B2
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- Prior art keywords
- gate
- oxide semiconductor
- potential
- transistor
- insulating layer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/53—Structure wherein the resistive material being in a transistor, e.g. gate
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- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
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- Electrodes Of Semiconductors (AREA)
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Description
本実施の形態では、開示する発明の一態様に係る半導体装置の回路構成およびその動作の一例について、図1乃至図4を参照して説明する。本実施の形態では、トランジスタにn型トランジスタ(nチャネル型トランジスタ)を用いる場合について説明する。
本実施の形態では、実施の形態1に示した半導体装置の構成およびその作製方法の一例について、図5乃至図7を参照して説明する。
図5は、記憶素子として適用することができるトランジスタ150の一例を示している。図5(A)は、トランジスタ150の平面を示しており、図5(B)は、図5(A)におけるX1−X2で示した部位の断面を示している。図5(C)は、図5(B)における部位180の拡大図である。
次に、上記トランジスタ150の作製方法の一例について図6を参照して説明する。なお、特段の説明が無い限り、本明細書で言うフォトリソグラフィ工程には、レジストマスクの形成工程と、導電層または絶縁層のエッチング工程と、レジストマスクの剥離工程が含まれているものとする。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図8を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
101 制御ゲート
102 第1のゲート絶縁層
103 電極
104 記憶ゲート
105 第2のゲート絶縁層
106 半導体層
107a ソース電極
107b ドレイン電極
108 絶縁層
109 保護絶縁層
110 下地絶縁層
111 バックゲート
150 トランジスタ
160 トランジスタ
170 トランジスタ
180 部位
181 端部
200 メモリセル
201 第1の配線
202 第2の配線
203 第3の配線
204 第4の配線
210 トランジスタ
211 制御ゲート
212 記憶ゲート
300 容量素子
301 電極
302 酸化物半導体
303 絶縁体
304 電極
311 曲線
312 曲線
701 筐体
702 筐体
703 表示部
704 キーボード
711 本体
712 スタイラス
713 表示部
714 操作ボタン
715 外部インターフェイス
720 電子書籍
721 筐体
723 筐体
725 表示部
727 表示部
731 電源
733 操作キー
735 スピーカー
737 軸部
740 筐体
741 筐体
742 表示パネル
743 スピーカー
744 マイクロフォン
745 操作キー
746 ポインティングデバイス
747 カメラ用レンズ
748 外部接続端子
749 太陽電池セル
750 外部メモリスロット
761 本体
763 接眼部
764 操作スイッチ
765 表示部
766 バッテリー
767 表示部
770 テレビジョン装置
771 筐体
773 表示部
775 スタンド
780 リモコン操作機
1200 メモリセル
1210 トランジスタ
1211 制御ゲート
1212 記憶ゲート
1221 第1の駆動回路
1222 第2の駆動回路
1223 第3の駆動回路
1224 第4の駆動回路
Claims (5)
- 制御ゲートと記憶ゲートとを有するトランジスタを含むメモリセルと、
ワード線と、
データ線と、
読み出し信号線と、
ビット線と、を有し、
前記制御ゲートは前記ワード線と電気的に接続され、
前記記憶ゲートは前記データ線と電気的に接続され、
前記トランジスタのソースまたはドレインの一方は、前記読み出し信号線と電気的に接続され、
前記ソースまたは前記ドレインの他方は、前記ビット線と電気的に接続され、
前記記憶ゲートと前記データ線とは、直接接続され、
前記記憶ゲートは、酸化物半導体を有することを特徴とする半導体装置。 - 請求項1において、
前記酸化物半導体は、インジウムを含むことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記トランジスタは、チャネル形成領域を有する半導体を有し、
前記記憶ゲートは、前記制御ゲートと前記半導体との間に位置することを特徴とする半導体装置。 - 請求項3において、
前記記憶ゲートは、前記チャネル形成領域と重なることを特徴とする半導体装置。 - 請求項3又は4において、
前記記憶ゲートは、絶縁層を介して前記チャネル形成領域と重なり、
前記記憶ゲートは、前記絶縁層と接することを特徴とする半導体装置。
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JP2015144297A (ja) | 2015-08-06 |
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JP2012028756A (ja) | 2012-02-09 |
TW201517040A (zh) | 2015-05-01 |
US9583576B2 (en) | 2017-02-28 |
US20170194050A1 (en) | 2017-07-06 |
US20200286554A1 (en) | 2020-09-10 |
JP5923191B2 (ja) | 2016-05-24 |
TWI574265B (zh) | 2017-03-11 |
WO2011162104A1 (en) | 2011-12-29 |
TW201517039A (zh) | 2015-05-01 |
US11551751B2 (en) | 2023-01-10 |
US8630127B2 (en) | 2014-01-14 |
TWI480876B (zh) | 2015-04-11 |
US20140124778A1 (en) | 2014-05-08 |
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US9633722B2 (en) | 2017-04-25 |
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