JP5691259B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5691259B2 JP5691259B2 JP2010141744A JP2010141744A JP5691259B2 JP 5691259 B2 JP5691259 B2 JP 5691259B2 JP 2010141744 A JP2010141744 A JP 2010141744A JP 2010141744 A JP2010141744 A JP 2010141744A JP 5691259 B2 JP5691259 B2 JP 5691259B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 230000005684 electric field Effects 0.000 claims description 103
- 230000002093 peripheral effect Effects 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 33
- 230000015556 catabolic process Effects 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 21
- 239000010410 layer Substances 0.000 description 124
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 39
- 229910010271 silicon carbide Inorganic materials 0.000 description 39
- 239000011229 interlayer Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Description
ベース層のうちセル領域よりも外側の外周領域に位置する部分においてセル領域の部分と同じ不純物濃度かつ該セル領域の部分よりも厚さが薄くされた電界緩和層(3a)を構成し、外周領域に、セル領域および電界緩和層(3a)を囲み、かつ、電界緩和層(3a)の表面からドリフト層(2)に達する電界終端部(13)を備えることを特徴としている。
本発明の一実施形態について説明する。本実施形態では、セル領域に半導体素子としてnチャネルタイプの縦型パワーMOSFETを形成したSiC半導体装置について説明する。図1は、本実施形態にかかるSiC半導体装置の断面図である。以下、この図に基づいて本実施形態のSiC半導体装置の構造について説明する。
まず、例えば1×1019cm-3以上の不純物濃度とされたn+型基板1の表面上に、例えば1×1015〜5×1016cm-3の不純物濃度とされたn-型ドリフト層2と、例えば1×1016〜5×1018cm-3の不純物濃度とされたp型ベース層3とが順に積層された半導体基板4を用意する。n-型ドリフト層2およびp型ベース層3は、例えばn+型基板1の表面へのエピタキシャル成長によって形成することができる。また、半導体基板4の裏面にドレイン電極11を形成しておく。
p型ベース層3の表面にLTO(Low temperature Oxidation)等で構成された図示しないマスクを配置したのち、フォトリソグラフィ工程によってマスクのうちメサ構造を構成するための凹部12の形成予定領域を開口させる。そして、マスク上からRIE(Reactive Ion Etching)等によるエッチングを行い、凹部12を形成する。この後、マスクを除去する。
再びLTO等で構成された図示しないマスクを配置したのち、フォトリソグラフィ工程によってマスクのうち電界終端部13の形成予定領域を開口させる。そして、マスク上からRIE等によるエッチングを行い、凹部12内に溝部14を形成する。この後、マスクを除去する。
さらに、n+型ソース領域5の形成予定領域が開口したイオン注入用のマスクを配置したのち、例えば窒素等のn型不純物のイオン注入および活性化熱処理を行うことにより、セル領域におけるp型ベース層3の表層部の所定領域にn+型ソース領域5を形成する。そして、マスクを除去したのち、今度はトレンチ6の形成予定領域が開口するマスクを配置し、そのマスクを用いたエッチングを行うことにより、トレンチ6を形成する。その後、マスクを除去し、ゲート酸化等により、ゲート絶縁膜7を形成する。このとき、セル領域だけでなく外周領域も絶縁膜が形成されることになり、溝部14内に絶縁部材15の一部が形成される。
セル領域および外周領域全域にドープトPoly−Siを成膜したのち、エッチバックもしくは所望マスクを用いてパターニングすることで、ゲート電極8を形成する。続いて、セル領域および外周領域全域にLTO等の層間絶縁膜9をデポジションする。これにより、溝部14内が完全に埋め込まれる。したがって、絶縁部材15も構成され、電界終端部13が形成される。
層間絶縁膜9の表面にコンタクトホール9a等の形成予定領域が開口するマスクを配置したのち、このマスクを用いて層間絶縁膜9をパターニングし、コンタクトホール9a等を形成する。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して電界終端部13の構成を変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第3実施形態について説明する。本実施形態も、第1実施形態に対して電界終端部13の構成を変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第4実施形態について説明する。本実施形態は、第1実施形態に対して電界終端部13の構成を変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第5実施形態について説明する。本実施形態は、第4実施形態に対して電界終端部13の構成を変更したものであり、その他に関しては第4実施形態と同様であるため、第4実施形態と異なる部分についてのみ説明する。
上記各実施形態では、セル領域に備えられる半導体素子として縦型パワーMOSFETを例に挙げて説明したが、p型ベース領域3が備えられる構造のものであれば、他の構造の半導体素子であっても良い。例えば、n+型基板1の導電型をp型に反転させたIGBTや、p型ベース領域3をアノード、n-型ドリフト層2およびn+型基板1をカソードとするPNダイオード等に関しても、本発明を適用することができる。
2 n-型ドリフト層
3 p型ベース層
3a 電界緩和層
4 半導体基板
5 n+型ソース領域
6 トレンチ
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
9a コンタクトホール
10 ソース電極
11 ドレイン電極
12 凹部
13 電界終端部
14 溝部
15 絶縁部材
16 n+型層
17 ドープトPoly−Si
Claims (8)
- 基板(1)と、前記基板(1)の表面に形成された第1導電型のドリフト層(2)と、前記ドリフト層(2)の表面に形成された第2導電型のベース層(3)とを有する半導体基板(4)に対して、半導体素子が備えられるセル領域と該セル領域を囲む外周耐圧構造を構成する外周領域とを形成することで構成される半導体装置であって、
前記ベース層は、前記セル領域から前記外周領域にわたって、底面が同一平面とされており、前記ベース層のうち前記セル領域よりも外側の前記外周領域に位置する部分において前記セル領域の部分と同じ不純物濃度かつ該セル領域の部分よりも厚さが薄くされた電界緩和層(3a)を構成しており、前記外周領域には、前記セル領域および前記電界緩和層(3a)を囲み、かつ、前記電界緩和層(3a)の表面から前記ドリフト層(2)に達する電界終端部(13)が備えられていることを特徴とする半導体装置。 - 前記電界終端部(13)は、前記電界緩和層(3a)の表面から前記ドリフト層(2)に達する溝部(14)と、前記溝部(14)内に配置された絶縁部材(15)によって構成されていることを特徴とする請求項1に記載の半導体装置。
- 前記電界終端部(13)は、前記セル領域および前記電界緩和層(3a)を囲むように同心状に配置された複数の前記溝部(14)と、前記溝部(14)内に配置された複数の前記絶縁部材(15)によって構成されていることを特徴とする請求項2に記載の半導体装置。
- 前記電界終端部(13)は、前記電界緩和層(3a)の表面から前記ドリフト層(2)に達する第1導電型層(16)であることを特徴とする請求項1に記載の半導体装置。
- 前記外周領域には、前記ベース層(3)を表面から除去した凹部(12)が形成されることによってメサ構造が構成されており、
前記電界終端部(13)は、前記凹部(12)内に形成されていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記外周領域には、前記ベース層(3)を表面から除去した凹部(12)が形成されることによってメサ構造が構成されており、
前記電界終端部(13)は、前記凹部(12)の外周に形成されていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記凹部(12)における前記セル領域側の段差部から前記電界終端部(13)までの距離が1〜10000μmとされていることを特徴とする請求項5または6に記載の半導体装置。
- 前記ベース層(3)および前記電界緩和層(3a)は、不純物濃度が1×1016〜2.5×1017cm-3であることを特徴とする請求項1ないし7のいずれか1つに記載の半導体装置。
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DE102011077764A DE102011077764A1 (de) | 2010-06-22 | 2011-06-17 | Halbleitervorrichtung, die einen zellbereich und einen randbereich beinhaltet und eine struktur für hohe durchbruchspannung aufweist |
US13/164,246 US8492867B2 (en) | 2010-06-22 | 2011-06-20 | Semiconductor device including cell region and peripheral region having high breakdown voltage structure |
CN201110175094.2A CN102299180B (zh) | 2010-06-22 | 2011-06-22 | 包含单元区和具有高击穿电压结构的外围区的半导体器件 |
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