JP5679397B2 - 薄膜トランジスタ基板の製造方法 - Google Patents

薄膜トランジスタ基板の製造方法 Download PDF

Info

Publication number
JP5679397B2
JP5679397B2 JP2007265748A JP2007265748A JP5679397B2 JP 5679397 B2 JP5679397 B2 JP 5679397B2 JP 2007265748 A JP2007265748 A JP 2007265748A JP 2007265748 A JP2007265748 A JP 2007265748A JP 5679397 B2 JP5679397 B2 JP 5679397B2
Authority
JP
Japan
Prior art keywords
metal layer
photoresist pattern
film transistor
thin film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007265748A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008098642A5 (enExample
JP2008098642A (ja
Inventor
徳 重 李
徳 重 李
大 昊 宋
大 昊 宋
京 燮 金
京 燮 金
庸 懿 李
庸 懿 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of JP2008098642A publication Critical patent/JP2008098642A/ja
Publication of JP2008098642A5 publication Critical patent/JP2008098642A5/ja
Application granted granted Critical
Publication of JP5679397B2 publication Critical patent/JP5679397B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
JP2007265748A 2006-10-12 2007-10-11 薄膜トランジスタ基板の製造方法 Active JP5679397B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0099187 2006-10-12
KR1020060099187A KR101229277B1 (ko) 2006-10-12 2006-10-12 박막 트랜지스터 기판의 제조 방법

Publications (3)

Publication Number Publication Date
JP2008098642A JP2008098642A (ja) 2008-04-24
JP2008098642A5 JP2008098642A5 (enExample) 2011-10-27
JP5679397B2 true JP5679397B2 (ja) 2015-03-04

Family

ID=38941886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007265748A Active JP5679397B2 (ja) 2006-10-12 2007-10-11 薄膜トランジスタ基板の製造方法

Country Status (6)

Country Link
US (1) US7803673B2 (enExample)
EP (1) EP1912256A1 (enExample)
JP (1) JP5679397B2 (enExample)
KR (1) KR101229277B1 (enExample)
CN (1) CN101162710A (enExample)
TW (1) TWI423394B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070038610A (ko) * 2005-10-06 2007-04-11 삼성전자주식회사 표시 장치의 수리 장치 및 수리 방법
US8791001B2 (en) * 2008-09-08 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. N2 based plasma treatment and ash for HK metal gate protection
KR101042957B1 (ko) * 2010-03-19 2011-06-20 삼성모바일디스플레이주식회사 트랜지스터 기판, 및 이의 제조 방법
US8163620B2 (en) * 2010-04-21 2012-04-24 Institute of Microelectronics, Chinese Academy of Sciences Method for etching Mo-based metal gate stack with aluminium nitride barrier
US8329518B1 (en) * 2011-08-11 2012-12-11 Shenzhen China Star Optoelectronics Technology Co., Ltd. Methods for manufacturing thin film transistor array substrate and display panel
KR102245497B1 (ko) * 2014-08-08 2021-04-29 삼성디스플레이 주식회사 표시 기판 및 이의 제조 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472329B1 (en) * 1999-08-16 2002-10-29 Applied Komatsu Technology, Inc. Etching aluminum over refractory metal with successive plasmas
JP4683688B2 (ja) 2000-03-16 2011-05-18 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
TW490857B (en) 2001-02-05 2002-06-11 Samsung Electronics Co Ltd Thin film transistor array substrate for liquid crystal display and method of fabricating same
JP4603190B2 (ja) 2001-04-16 2010-12-22 株式会社日立製作所 液晶表示装置
JP4920140B2 (ja) * 2001-05-18 2012-04-18 ゲットナー・ファンデーション・エルエルシー 液晶表示装置及びその製造方法
JP4050503B2 (ja) * 2001-11-29 2008-02-20 株式会社日立製作所 表示装置
JP4221314B2 (ja) * 2004-02-10 2009-02-12 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタとそれを用いた液晶表示装置およびその薄膜トランジスタの製造方法
KR101090252B1 (ko) * 2004-09-24 2011-12-06 삼성전자주식회사 박막 트랜지스터 표시판 및 그의 제조 방법
KR101136026B1 (ko) * 2004-09-24 2012-04-18 주식회사 동진쎄미켐 포토레지스트용 박리제 및 상기 박리제를 이용한 박막트랜지스터 표시판의 제조 방법
KR20060081470A (ko) * 2005-01-07 2006-07-13 삼성전자주식회사 박막트랜지스터 기판과 그 제조방법
KR20060089526A (ko) * 2005-02-04 2006-08-09 삼성전자주식회사 박막 트랜지스터 표시판과 그 제조 방법

Also Published As

Publication number Publication date
US20080090342A1 (en) 2008-04-17
TW200828505A (en) 2008-07-01
CN101162710A (zh) 2008-04-16
KR101229277B1 (ko) 2013-02-04
TWI423394B (zh) 2014-01-11
KR20080033590A (ko) 2008-04-17
US7803673B2 (en) 2010-09-28
EP1912256A1 (en) 2008-04-16
JP2008098642A (ja) 2008-04-24

Similar Documents

Publication Publication Date Title
US8563980B2 (en) Array substrate and manufacturing method
US6207480B1 (en) Method of manufacturing a thin film transistor array panel for a liquid crystal display
KR100917654B1 (ko) 박막트랜지스터 액정 디스플레이 화소 구조 및 그 제조방법
KR101431136B1 (ko) 박막 트랜지스터 기판의 제조 방법
JP4994014B2 (ja) フラットパネルディスプレイに使用される薄膜トランジスタの製造方法
US7649581B2 (en) Array substrate of an LCD comprising first and second gate insulating layers and method of fabricating the same
KR20080012810A (ko) 박막 트랜지스터 ｌｃｄ 화소 유닛 및 그 제조방법
JP2008109102A (ja) 薄膜トランジスタ基板の製造方法
JP2004226975A (ja) 薄膜トランジスタ表示板及びその製造方法
JP5679397B2 (ja) 薄膜トランジスタ基板の製造方法
KR20040086946A (ko) 액정표시장치의 제조방법
CN108803168B (zh) 一种阵列基板及其制作方法、液晶显示装置
TWI424507B (zh) 薄膜電晶體陣列基板的製造方法
KR101432109B1 (ko) 박막 트랜지스터의 제조 방법
JP4578402B2 (ja) 薄膜トランジスタ基板及びその製造方法
KR101813719B1 (ko) 박막트랜지스터 어레이 기판의 제조 방법
US10007175B2 (en) Mask and method for manufacturing thin film transistor using the same
KR102035004B1 (ko) 액정표시장치용 어레이 기판 및 이의 제조방법
US20080188042A1 (en) Method of manufacturing thin film transistor panel
CN102830531B (zh) Tft阵列基板、制造方法及液晶显示装置
KR100848110B1 (ko) 액정 표시 장치용 박막 트랜지스터 기판 및 그 제조 방법
KR100930573B1 (ko) 박막트랜지스터 제조 방법 및 이를 이용한 표시 장치제조방법
JPH04357832A (ja) エッチング方法および薄膜トランジスタの製造方法
KR20080022829A (ko) 박막트랜지스터 기판의 제조방법
KR20080051483A (ko) 박막 트랜지스터 기판의 제조 방법

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101008

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101015

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110909

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20121213

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130520

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20131008

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140128

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20140204

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20140314

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141226

R150 Certificate of patent or registration of utility model

Ref document number: 5679397

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250