JP5656611B2 - 半導体装置及び固体撮像装置 - Google Patents

半導体装置及び固体撮像装置 Download PDF

Info

Publication number
JP5656611B2
JP5656611B2 JP2010283771A JP2010283771A JP5656611B2 JP 5656611 B2 JP5656611 B2 JP 5656611B2 JP 2010283771 A JP2010283771 A JP 2010283771A JP 2010283771 A JP2010283771 A JP 2010283771A JP 5656611 B2 JP5656611 B2 JP 5656611B2
Authority
JP
Japan
Prior art keywords
conductive member
wiring
pad
circuit
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010283771A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012134257A5 (enExample
JP2012134257A (ja
Inventor
小倉　正徳
正徳 小倉
秀央 小林
秀央 小林
享裕 黒田
享裕 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2010283771A priority Critical patent/JP5656611B2/ja
Priority to US13/316,308 priority patent/US8581361B2/en
Priority to CN201110420964.8A priority patent/CN102569253B/zh
Publication of JP2012134257A publication Critical patent/JP2012134257A/ja
Publication of JP2012134257A5 publication Critical patent/JP2012134257A5/ja
Application granted granted Critical
Publication of JP5656611B2 publication Critical patent/JP5656611B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06157—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with specially adapted redistribution layers [RDL]
    • H01L2224/06159—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with specially adapted redistribution layers [RDL] being disposed in different wiring levels, i.e. resurf layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06167—Random array, i.e. array with no symmetry with specially adapted redistribution layers [RDL]
    • H01L2224/06169—Random array, i.e. array with no symmetry with specially adapted redistribution layers [RDL] being disposed in different wiring levels, i.e. resurf layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Solid State Image Pick-Up Elements (AREA)
JP2010283771A 2010-12-20 2010-12-20 半導体装置及び固体撮像装置 Active JP5656611B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010283771A JP5656611B2 (ja) 2010-12-20 2010-12-20 半導体装置及び固体撮像装置
US13/316,308 US8581361B2 (en) 2010-12-20 2011-12-09 Semiconductor apparatus
CN201110420964.8A CN102569253B (zh) 2010-12-20 2011-12-15 半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010283771A JP5656611B2 (ja) 2010-12-20 2010-12-20 半導体装置及び固体撮像装置

Publications (3)

Publication Number Publication Date
JP2012134257A JP2012134257A (ja) 2012-07-12
JP2012134257A5 JP2012134257A5 (enExample) 2014-01-09
JP5656611B2 true JP5656611B2 (ja) 2015-01-21

Family

ID=46233250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010283771A Active JP5656611B2 (ja) 2010-12-20 2010-12-20 半導体装置及び固体撮像装置

Country Status (3)

Country Link
US (1) US8581361B2 (enExample)
JP (1) JP5656611B2 (enExample)
CN (1) CN102569253B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5746494B2 (ja) 2010-11-24 2015-07-08 ルネサスエレクトロニクス株式会社 半導体装置、液晶ディスプレイパネル及び携帯情報端末
JP2017084944A (ja) * 2015-10-27 2017-05-18 株式会社デンソー 半導体装置
JP6658047B2 (ja) 2016-02-12 2020-03-04 セイコーエプソン株式会社 画像読取装置及び半導体装置
JP2018152715A (ja) * 2017-03-13 2018-09-27 セイコーエプソン株式会社 画像読取装置及び半導体装置
US10811059B1 (en) * 2019-03-27 2020-10-20 Micron Technology, Inc. Routing for power signals including a redistribution layer
JP7362380B2 (ja) 2019-09-12 2023-10-17 キヤノン株式会社 配線基板及び半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3270874B2 (ja) * 1993-09-21 2002-04-02 ソニー株式会社 リニアセンサ
JP2004214594A (ja) * 2002-11-15 2004-07-29 Sharp Corp 半導体装置およびその製造方法
JP2005243907A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
KR100548582B1 (ko) * 2004-07-23 2006-02-02 주식회사 하이닉스반도체 반도체소자의 패드부
JP4714502B2 (ja) * 2005-04-26 2011-06-29 パナソニック株式会社 固体撮像装置
JP2007042718A (ja) * 2005-08-01 2007-02-15 Renesas Technology Corp 半導体装置
JP2007184311A (ja) * 2005-12-29 2007-07-19 Sony Corp 固体撮像装置およびその製造方法
JP4986114B2 (ja) * 2006-04-17 2012-07-25 ルネサスエレクトロニクス株式会社 半導体集積回路及び半導体集積回路の設計方法
JP2008078354A (ja) * 2006-09-21 2008-04-03 Renesas Technology Corp 半導体装置
JP5147234B2 (ja) * 2006-12-28 2013-02-20 パナソニック株式会社 半導体集積回路装置
JP5537016B2 (ja) * 2008-10-27 2014-07-02 株式会社東芝 半導体装置および半導体装置の製造方法
JP2010251595A (ja) * 2009-04-17 2010-11-04 Renesas Electronics Corp 半導体撮像装置

Also Published As

Publication number Publication date
US20120153367A1 (en) 2012-06-21
CN102569253A (zh) 2012-07-11
US8581361B2 (en) 2013-11-12
CN102569253B (zh) 2014-10-01
JP2012134257A (ja) 2012-07-12

Similar Documents

Publication Publication Date Title
JP6779825B2 (ja) 半導体装置および機器
US8937672B2 (en) Solid-state image sensor and camera
KR102574526B1 (ko) 반도체 장치
JP5656611B2 (ja) 半導体装置及び固体撮像装置
US11004760B2 (en) Chip structure operating method including heating elements to reduce temperature variation
US20180197850A1 (en) Semiconductor integrated circuit device
JP5970747B2 (ja) 半導体装置
US9595489B2 (en) Semiconductor package with bonding wires of reduced loop inductance
KR20100002113A (ko) 반도체장치 및 반도체 집적회로
CN111276500B (zh) 半导体装置
JP2011222807A (ja) 半導体装置
JP2008004736A (ja) 半導体パッケージ
US20190013347A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2006202866A (ja) 半導体装置
JP5604602B2 (ja) 半導体集積回路装置
KR102863704B1 (ko) 적층 반도체 칩을 포함하는 반도체 패키지
JP5916820B2 (ja) 半導体集積回路装置
JP4890827B2 (ja) 半導体装置
JP2020035940A (ja) 半導体装置
CN114503266B (zh) 拍摄元件及拍摄装置
JP2007165720A (ja) 半導体チップのｉ／ｏアレイ構造
WO2024004876A1 (ja) 半導体素子および積層構造体
JP2013031092A (ja) 固体撮像装置
JP2011258743A (ja) 半導体チップ及び半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131118

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20131118

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140807

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140902

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141008

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141028

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141125

R151 Written notification of patent or utility model registration

Ref document number: 5656611

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151