JP2007042718A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007042718A JP2007042718A JP2005222601A JP2005222601A JP2007042718A JP 2007042718 A JP2007042718 A JP 2007042718A JP 2005222601 A JP2005222601 A JP 2005222601A JP 2005222601 A JP2005222601 A JP 2005222601A JP 2007042718 A JP2007042718 A JP 2007042718A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- pad
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
【解決手段】I/Oセル14は、パッド2と、それに接続する出力バッファおよび入力バッファ、およびパッド2と同じ配線層を用いて形成された電源配線3と、パッド2と電源配線3との間に接続する保護素子であるクランプダイオード(アノード領域29およびカソード領域31)とを備える。クランプダイオードは、電源配線3により短い距離で接続可能なように、電源配線3の真下あるいはその近傍の領域にレイアウトされる。
【選択図】図22
Description
図1は、本発明の実施の形態1に係る半導体装置の構成を示す図である。当該半導体装置は、内部回路1とパッド2との間に、出力バッファ11、保護回路12および入力バッファ13から成る入出力回路10を備えている。内部回路1は、出力バッファ11に信号を出力すると共に入力バッファ13からの信号が入力される論理回路や、電源電圧を当該論理回路用のレベルに変換するレベルシフタなどを含んでいる。
図31は、本発明の実施の形態2に係る半導体装置の構成を示す図である。本実施の形態の半導体装置も、内部回路1とパッド2との間に、出力バッファ200、保護回路203および入力バッファ206から成る入出力回路10を備えている。
Claims (8)
- パッドを有する複数のセルと、
前記パッドと同じ配線層を用いて形成され前記複数のセルに跨って延在する電源配線とを備える半導体装置であって、
前記複数のセルは、
前記パッドへ信号を出力する出力バッファおよび前記パッドと前記電源配線との間に接続した保護素子を有する第1のセルを含み、
前記第1のセルにおいて、
前記電源配線と前記保護素子との平面視での距離は、前記電源配線と前記出力バッファとの平面視での距離よりも小さい
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1のセルにおいて、
前記保護素子は、前記電源配線の真下の領域に配設されている
ことを特徴とする半導体装置。 - 請求項1または請求項2記載の半導体装置であって、
前記第1のセルにおいて、
前記電源配線と前記保護素子との間の抵抗値が、前記電源配線と前記出力バッファとの間の抵抗値よりも小さい
ことを特徴とする半導体装置。 - 請求項1または請求項2記載の半導体装置であって、
前記複数のセルは、
前記パッドが前記電源配線に接続した第2のセルを含み、
前記第1のセルは、
前記パッドと前記出力バッファとの間に接続する保護抵抗をさらに備え、
前記第1のセルにおいて、
前記保護素子と前記第2のセルのパッドとの間の抵抗値が、前記保護抵抗の抵抗値よりも小さい
ことを特徴とする半導体装置。 - 請求項1から請求項4のいずれか記載の半導体装置であって、
前記複数のセルは、
前記パッドが前記電源配線よりも外側に配置されたものと、
前記パッドが前記電源配線よりも内側に配置されたものとを含む
ことを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記複数のセルのパッドは、電源配線を挟んで千鳥状に配設されている
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記電源配線は、
半導体チップの外周部を周回するように配設されている
ことを特徴とする半導体装置。 - パッドを有する複数のセルと、
前記パッドと同じ配線層を用いて形成され前記複数のセルに跨って延在する電源配線とを備える半導体装置であって、
前記複数のセルは、
前記パッドへ信号を出力する出力バッファおよび前記パッドと前記電源配線との間に接続した保護素子を有する第1のセルを含み、
前記第1のセルにおいて、
前記電源配線と前記保護素子との平面視での距離は、前記電源配線と前記出力バッファとの平面視での距離以下である
ことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005222601A JP2007042718A (ja) | 2005-08-01 | 2005-08-01 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005222601A JP2007042718A (ja) | 2005-08-01 | 2005-08-01 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007042718A true JP2007042718A (ja) | 2007-02-15 |
Family
ID=37800453
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005222601A Pending JP2007042718A (ja) | 2005-08-01 | 2005-08-01 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2007042718A (ja) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010041042A (ja) * | 2008-07-10 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
WO2010067481A1 (ja) * | 2008-12-10 | 2010-06-17 | パナソニック株式会社 | 半導体集積回路装置及びその設計方法 |
JP2010147282A (ja) * | 2008-12-19 | 2010-07-01 | Renesas Technology Corp | 半導体集積回路装置 |
JP2011171415A (ja) * | 2010-02-17 | 2011-09-01 | Seiko Epson Corp | 半導体集積回路 |
JP2011171680A (ja) * | 2010-02-22 | 2011-09-01 | Panasonic Corp | 半導体集積回路装置 |
WO2011145240A1 (ja) * | 2010-05-18 | 2011-11-24 | パナソニック株式会社 | 半導体装置 |
JP2012134257A (ja) * | 2010-12-20 | 2012-07-12 | Canon Inc | 半導体装置及び固体撮像装置 |
US8399928B2 (en) | 2010-05-18 | 2013-03-19 | Panasonic Corporation | Semiconductor device |
JP2014064044A (ja) * | 2014-01-07 | 2014-04-10 | Renesas Electronics Corp | 半導体集積回路装置 |
US8759941B2 (en) | 2008-12-10 | 2014-06-24 | Panasonic Corporation | Semiconductor integrated circuit device and method for designing the same |
JP2015008320A (ja) * | 2014-08-25 | 2015-01-15 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP7358998B2 (ja) | 2020-01-17 | 2023-10-11 | 富士電機株式会社 | 駆動装置 |
WO2024029040A1 (ja) * | 2022-08-04 | 2024-02-08 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002043428A (ja) * | 2000-07-24 | 2002-02-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JP2004111796A (ja) * | 2002-09-20 | 2004-04-08 | Hitachi Ltd | 半導体装置 |
-
2005
- 2005-08-01 JP JP2005222601A patent/JP2007042718A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002043428A (ja) * | 2000-07-24 | 2002-02-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JP2004111796A (ja) * | 2002-09-20 | 2004-04-08 | Hitachi Ltd | 半導体装置 |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010041042A (ja) * | 2008-07-10 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US8860081B2 (en) | 2008-07-10 | 2014-10-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
WO2010067481A1 (ja) * | 2008-12-10 | 2010-06-17 | パナソニック株式会社 | 半導体集積回路装置及びその設計方法 |
US8759941B2 (en) | 2008-12-10 | 2014-06-24 | Panasonic Corporation | Semiconductor integrated circuit device and method for designing the same |
JP2010147282A (ja) * | 2008-12-19 | 2010-07-01 | Renesas Technology Corp | 半導体集積回路装置 |
US9947651B2 (en) | 2008-12-19 | 2018-04-17 | Renesas Electronics Corporation | Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal |
TWI496225B (zh) * | 2008-12-19 | 2015-08-11 | Renesas Electronics Corp | Semiconductor integrated circuit device |
JP2011171415A (ja) * | 2010-02-17 | 2011-09-01 | Seiko Epson Corp | 半導体集積回路 |
JP2011171680A (ja) * | 2010-02-22 | 2011-09-01 | Panasonic Corp | 半導体集積回路装置 |
US8773825B2 (en) | 2010-02-22 | 2014-07-08 | Panasonic Corporation | Semiconductor integrated circuit device |
US8748987B2 (en) | 2010-05-18 | 2014-06-10 | Panasonic Corporation | Semiconductor device |
US8598668B2 (en) | 2010-05-18 | 2013-12-03 | Panasonic Corporation | Semiconductor device |
US8399928B2 (en) | 2010-05-18 | 2013-03-19 | Panasonic Corporation | Semiconductor device |
US8946824B2 (en) | 2010-05-18 | 2015-02-03 | Panasonic Corporation | Semiconductor device |
US9142539B2 (en) | 2010-05-18 | 2015-09-22 | Socionext Inc. | Semiconductor device |
WO2011145240A1 (ja) * | 2010-05-18 | 2011-11-24 | パナソニック株式会社 | 半導体装置 |
JP2012134257A (ja) * | 2010-12-20 | 2012-07-12 | Canon Inc | 半導体装置及び固体撮像装置 |
JP2014064044A (ja) * | 2014-01-07 | 2014-04-10 | Renesas Electronics Corp | 半導体集積回路装置 |
JP2015008320A (ja) * | 2014-08-25 | 2015-01-15 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP7358998B2 (ja) | 2020-01-17 | 2023-10-11 | 富士電機株式会社 | 駆動装置 |
WO2024029040A1 (ja) * | 2022-08-04 | 2024-02-08 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2007042718A (ja) | 半導体装置 | |
JP4995455B2 (ja) | 半導体装置 | |
JP5342154B2 (ja) | 半導体装置の製造方法 | |
US7183612B2 (en) | Semiconductor device having an electrostatic discharge protecting element | |
US8067789B2 (en) | Semiconductor integrated circuit device | |
JP2006303110A (ja) | 半導体装置 | |
JP5583266B2 (ja) | 半導体装置 | |
JP2007305693A (ja) | 半導体装置および電気ヒューズの切断方法 | |
JP3851893B2 (ja) | 半導体集積回路装置 | |
JP2010147282A (ja) | 半導体集積回路装置 | |
JPH1084083A (ja) | 静電気保護回路を備えた半導体装置 | |
JP4995364B2 (ja) | 半導体集積回路装置 | |
JP5054370B2 (ja) | 半導体チップ | |
JP4295370B2 (ja) | 半導体素子 | |
JP4974485B2 (ja) | 半導体集積回路装置 | |
JP2003324151A (ja) | 半導体集積回路装置、実装基板装置、及び実装基板装置の配線切断方法 | |
JP2002313947A (ja) | 半導体装置 | |
JP2003152163A (ja) | 半導体保護装置 | |
JP3607262B2 (ja) | 半導体装置の静電破壊防止保護回路 | |
JP4857834B2 (ja) | 入力保護回路 | |
US20230352430A1 (en) | Semiconductor device and method of manufacturing the same | |
JP7052972B2 (ja) | 半導体集積回路 | |
JP3319445B2 (ja) | 半導体装置 | |
KR100645069B1 (ko) | 정전기 방전 보호 소자 및 그 제조방법 | |
JP2008047642A (ja) | 静電気放電保護半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080708 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20080708 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100524 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110824 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110830 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120117 |