JP5623080B2 - チップ実装 - Google Patents

チップ実装 Download PDF

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Publication number
JP5623080B2
JP5623080B2 JP2009540834A JP2009540834A JP5623080B2 JP 5623080 B2 JP5623080 B2 JP 5623080B2 JP 2009540834 A JP2009540834 A JP 2009540834A JP 2009540834 A JP2009540834 A JP 2009540834A JP 5623080 B2 JP5623080 B2 JP 5623080B2
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JP
Japan
Prior art keywords
solder
chip
buffer layers
buffer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009540834A
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English (en)
Japanese (ja)
Other versions
JP2010514148A (ja
Inventor
サイモン、ジョナサン、ステイシー
Original Assignee
ケンブリッジシリコン ラジオ リミテッド
ケンブリッジ シリコン ラジオ リミテッド
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Application filed by ケンブリッジシリコン ラジオ リミテッド, ケンブリッジ シリコン ラジオ リミテッド filed Critical ケンブリッジシリコン ラジオ リミテッド
Publication of JP2010514148A publication Critical patent/JP2010514148A/ja
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2009540834A 2006-12-13 2007-11-26 チップ実装 Expired - Fee Related JP5623080B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0624888.4 2006-12-13
GB0624888A GB2444775B (en) 2006-12-13 2006-12-13 Chip mounting
PCT/GB2007/004500 WO2008071905A1 (en) 2006-12-13 2007-11-26 Chip mounting

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013273446A Division JP5806286B2 (ja) 2006-12-13 2013-12-27 チップ実装

Publications (2)

Publication Number Publication Date
JP2010514148A JP2010514148A (ja) 2010-04-30
JP5623080B2 true JP5623080B2 (ja) 2014-11-12

Family

ID=37712074

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2009540834A Expired - Fee Related JP5623080B2 (ja) 2006-12-13 2007-11-26 チップ実装
JP2013273446A Expired - Fee Related JP5806286B2 (ja) 2006-12-13 2013-12-27 チップ実装

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2013273446A Expired - Fee Related JP5806286B2 (ja) 2006-12-13 2013-12-27 チップ実装

Country Status (5)

Country Link
US (2) US9177885B2 (https=)
JP (2) JP5623080B2 (https=)
GB (1) GB2444775B (https=)
TW (1) TWI475621B (https=)
WO (1) WO2008071905A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2444775B (en) * 2006-12-13 2011-06-08 Cambridge Silicon Radio Ltd Chip mounting
GB2482894B (en) 2010-08-18 2014-11-12 Cambridge Silicon Radio Ltd Interconnection structure
US9935038B2 (en) 2012-04-11 2018-04-03 Taiwan Semiconductor Manufacturing Company Semiconductor device packages and methods
US11189538B2 (en) * 2018-09-28 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with polyimide packaging and manufacturing method

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW480636B (en) 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP4310647B2 (ja) * 1997-01-17 2009-08-12 セイコーエプソン株式会社 半導体装置及びその製造方法
JP3795628B2 (ja) * 1997-05-16 2006-07-12 シチズン時計株式会社 半導体チップを搭載する配線基板の製造方法
JP3417325B2 (ja) * 1999-01-26 2003-06-16 日立電線株式会社 半導体パッケージ
JP2000323628A (ja) * 1999-05-10 2000-11-24 Hitachi Ltd 半導体装置とその製造方法、およびこれを用いた電子機器
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP2001257282A (ja) * 2000-03-09 2001-09-21 Hitachi Chem Co Ltd 半導体装置の製造方法及び半導体装置
TWI248384B (en) * 2000-06-12 2006-02-01 Hitachi Ltd Electronic device
JP3640876B2 (ja) * 2000-09-19 2005-04-20 株式会社ルネサステクノロジ 半導体装置及び半導体装置の実装構造体
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
TW577152B (en) * 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
TW574752B (en) * 2000-12-25 2004-02-01 Hitachi Ltd Semiconductor module
US6518675B2 (en) * 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
US6433427B1 (en) 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
JP2003020404A (ja) * 2001-07-10 2003-01-24 Hitachi Ltd 耐熱性低弾性率材およびそれを用いた装置
TW517360B (en) * 2001-12-19 2003-01-11 Ind Tech Res Inst Enhanced type wafer level package structure and its manufacture method
US6805974B2 (en) * 2002-02-15 2004-10-19 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
JP2003298196A (ja) * 2002-04-03 2003-10-17 Japan Gore Tex Inc プリント配線板用誘電体フィルム、多層プリント基板および半導体装置
US6940177B2 (en) 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
US20040089470A1 (en) * 2002-11-12 2004-05-13 Nec Corporation Printed circuit board, semiconductor package, base insulating film, and manufacturing method for interconnect substrate
JP2004214561A (ja) * 2003-01-08 2004-07-29 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP4124173B2 (ja) * 2003-07-01 2008-07-23 日本電気株式会社 応力緩和構造とその形成方法、応力緩和シートとその製造方法、及び半導体装置並びに電子機器
KR100942400B1 (ko) * 2004-01-30 2010-02-17 이비덴 가부시키가이샤 다층 프린트 배선판 및 그 제조 방법
JP4446793B2 (ja) * 2004-04-28 2010-04-07 パナソニック株式会社 半導体装置およびその製造方法
JP4327657B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
KR100548581B1 (ko) * 2004-07-22 2006-02-02 주식회사 하이닉스반도체 웨이퍼 레벨 칩 스케일 패키지
CN100468674C (zh) * 2004-11-25 2009-03-11 日本电气株式会社 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
JP4471213B2 (ja) * 2004-12-28 2010-06-02 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
US7326638B2 (en) * 2005-01-19 2008-02-05 New Japan Radio Co., Ltd. Method for manufacturing semiconductor device
US7361990B2 (en) * 2005-03-17 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
GB2444775B (en) * 2006-12-13 2011-06-08 Cambridge Silicon Radio Ltd Chip mounting

Also Published As

Publication number Publication date
US9177885B2 (en) 2015-11-03
GB2444775B (en) 2011-06-08
TW200832577A (en) 2008-08-01
JP2010514148A (ja) 2010-04-30
JP2014112694A (ja) 2014-06-19
US20100013093A1 (en) 2010-01-21
GB0624888D0 (en) 2007-01-24
JP5806286B2 (ja) 2015-11-10
GB2444775A (en) 2008-06-18
WO2008071905B1 (en) 2008-08-21
US20160086907A1 (en) 2016-03-24
US9659894B2 (en) 2017-05-23
TWI475621B (zh) 2015-03-01
WO2008071905A1 (en) 2008-06-19

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