Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
  • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
  • H10W20/48—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/247—Dispositions of multiple bumps
  • H10W72/248—Top-view layouts, e.g. mirror arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present invention relates to a technique for electrically connecting a printed circuit board to a chip defining one or more electronic devices.
• WLCSP wafer-level chip scale packaging
• This technique is characterised in that: (a) there is no pre-assembly of the chip on a substrate before mounting onto the printed circuit board; and (b) the chip is ready for surface mounting on a printed circuit board as soon as it is singulated from the wafer.
• the area that the thus packaged chip occupies when mounted onto a printed circuit board is the size of the silicon die.
• FIG. 1 One such interconnection between a chip or integrated circuit 6 and a printed circuit board 2 is shown in Figure 1 , where the solder ball is designated by reference numeral 4. Also shown in Figure 1 are the common locations 5 where cracks have been found to develop when the assembly is subject to impact testing, such as drop testing.
• One aspect of the present invention provides a device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, wherein the chip is provided with one or more buffer layers between the substrate and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.
• Said one or more buffer layers may have a total thickness of more than 3 microns, more preferably - especially but not exclusively in the case of a single buffer layer - in the range of 4 to 8 microns. Said one or more buffer layers may have a total thickness of more than 10 microns, more preferably - especially but not exclusively in the case of multiple buffer layers - in the range of 13 to 20 microns.
• the chip may be provided with two of said buffer layers. There may then be a patterned conductive layer such as a redistribution layer sandwiched therebetween for electrically connecting said one or more solder elements to said one or more electronic devices.
• a patterned conductive layer such as a redistribution layer sandwiched therebetween for electrically connecting said one or more solder elements to said one or more electronic devices.
• only one of those buffer layers is uninterrupted between the entirety of each solder element and the substrate. That may be the one of the layers that lies between the patterned conductive layer and the substrate.
• the other buffer layer may be interrupted under each solder element to allow the solder element to connect to the patterned conductive layer.
• Each of said two buffer layers may have a thickness of more than 5 microns, more preferably in the range of about 6.5 microns to about 10 microns, and most preferably of about 7.5 microns.
• the two buffer layers may have the same composition, or may be different.
• the two buffer layers each have a Young's
• the or each buffer layer may be located between each solder element and the substrate, preferably lying uninterruptedly between each solder element and the substrate. Such an uninterrupted buffer layer may conveniently be sandwiched between a patterned conductive layer such as a redistribution layer and the substrate. That buffer layer may have a thickness of more than 5 microns, more preferably in the range of about 6.5 microns to about 10 microns, and most preferably of about 7.5 microns. Preferably the buffer layer has a Young's Modulus of about 2 GPa.
• the or each layer having a Young's modulus of about 2GPa could have a Young's modulus of 1.6 to 2.4GPa or from 1.7 to 2.3GPa or from 1.8 to 2.2GPa or from 1.9 to 2.1GPa.
• the device may comprise an array of said solder elements spaced at a pitch of 0.5mm or less, or at a pitch of 0.4mm or less.
• the one or more solder elements may be tin-based solder elements. They may have a composition including about 4% wt. silver, and about 0.5%wt. copper, although the invention is not limited to use with this composition and the advantages of the invention can be gained when other compositions are used.
• the solder elements may conveniently be solder balls or solder bumps.
• the substrate may be a semiconductor wafer.
• a chip including a substrate defining one or more electronic devices and one or more solder elements located within the area of the chip and electrically connected to said one or more electronic devices, wherein the chip is provided with one or more buffer layers having a Young's Modulus of 2.5GPa or less between the substrate and the solder elements.
• a device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, wherein the chip is provided with one or more buffer layers having a total thickness of more than 5 microns between the substrate and the solder elements.
• a device comprising a chip including a substrate defining one or more electronic devices and one or more solder elements located within the area of the chip and electrically connected to said one or more electronic devices, wherein the chip is provided with one or more buffer layers having a total thickness of more than 5 microns between the substrate and the solder elements.
• the total thickness of the buffer layer(s) may preferably be greater than 10 microns.
• the total thickness of the buffer layer(s) in the zone directly between the substrate and the parts of the solder elements that most closely approach the substrate may preferably be less than 10 microns, e.g. around 7 to 8 microns.
• a wireless communication device including a device or a chip as set out above. That may be a handheld-portable device such as a mobile phone.
• Figure 2 illustrates a first WLCSP technique
• Figure 3 illustrates the results of drop tests for embodiments of the present invention.
• Figure 4 illustrates a second WLCSP technique.
• a silicon wafer die 8 has a plurality of electronic devices defined therein. Aluminium pads 10 are then provided in contact with electrodes of the electronic devices. A passivation layer 12 is then provided over the entire area of the wafer die 8, and is then patterned to expose the aluminium pads 10. A first buffer layer 14 is then provided on the passivation layer 12 over the entire area of the wafer die 8, and is patterned to expose portions of the aluminium pads 10 exposed by the patterning of the passivation layer 12. A patterned conductive redistribution layer 16 is then provided on the first buffer layer 14 to provide lateral electrical connections between the locations of the aluminium pads 10 and the desired locations for the respective solder balls 22.
• a second buffer layer 18 is then provided over the redistribution layer 16, and is patterned to expose portions of the redistribution layer at locations where it is desired to make contact to a solder ball 22.
• Under-bump metallisation (UBM) 20 is carried out on the thus exposed locations of the redistribution layer 16. Solder balls 22 are then provided in contact with the under-bump metallisations 20.
• the thus processed/packaged wafer is then cut into chips and each chip is mounted onto a respective printed circuit board in the manner shown in Figure 1 with the solder balls 22 providing the electrical connections between the chip and the printed circuit board.
• the buffer layers 14, 18 have a Young's Modulus of 2.0 GPa and each have a thickness (t1 and t2) of 5 microns.
• the buffer layers 14, 18 also have the same Young's Modulus of 2.0GPa and each have a thickness (t1 and t2) of 7.5 microns.
• each of the buffer layers 14, 18 are provided by spin coating a polyimide precursor sold by HD Microsystems as HD-8820 at a spin speed of 1000-4000rprn and a spin time between 30 and 60 seconds. This is followed by hot plate baking at 123°C for 180 seconds. This is followed by selective exposure of those portions to be removed to reveal the aluminium pads (in the case of the first buffer layer 14) and the redistribution layer (in the case of the second buffer layer 18) at a fluence of 280-500mj/cm 2 , and development using 0.26N Tetra-Methyl Ammonium Hydroxide (TMAH) as a developer. The development step washes away the selectively irradiated portions of the buffer layer.
• TMAH Tetra-Methyl Ammonium Hydroxide
• each buffer layer is cured in a furnace in a nitrogen atmosphere at 32O 0 C.
• the temperature of the furnace is ramped to 320 0 C followed by a period of around 1 hour at 32O 0 C.
• Changing the final cure temperature and/or the length of time at which the buffer layer is maintained at the final cure temperature can be used to adjust the Young's Modulus of the resultant film.
• the thicknesses stated above are the thicknesses after curing.
• the polyimide precursor mentioned above comprises 30-40% polyamide, 45-55% gamma-butyrolactone, 1-10% propylene glycol monomethyl ether acetate, 1 to 5% organo silan compound(s) and 1 to 10% photoinitiator.
• Figure 3 illustrates the results of a drop test for the first (triangle marker) and second (diamond marker) embodiments. Comparison results of the same drop test for the same construction as the first embodiment but using buffer layers 14, 18 having a Young's Modulus of 3.5GPa (square marker) are also shown. The line to 3.5GPa and thickness of 7.5 microns is a modelled extrapolation. Figure 3 shows how the drop test characteristic life is improved for the first embodiment compared to devices produced in an identical fashion except that the buffer layers 14, 18 have a Young's Modulus of 3.5GPa. Figure 3 also shows how the second embodiment exhibits yet improved drop test performance compared to the first embodiment.
• solder balls were made from SAC405 (tin-based solder including 4%wt. silver and 0.5%wt. copper). It has been shown experimentally that this solder composition provides better results than other solder compositions in the first and second embodiments described above. However, other compositions may be used if desired.
• the solder balls had a pitch P of 0.4mm, but it is expected that the same improvements would be exhibited for different pitches, such as 0.5mm and 0.3mm.
• the buffer layer 14 is located directly between the solder ball 22 and the silicon wafer substrate 8. It is uninterrupted in the region where it underlies the solder ball 22.
• This physical arrangement of the components promotes the effectiveness of the buffer layer 14 in improving crack resistance.
• Such a physical arrangement can conveniently by achieved by using a redistribution layer as illustrated in figure 2 to allow a lateral offset between the solder pad 10 and the solder ball 22.
• connection techniques such as bump-on-IO
• a via then passes through the polymer layer 14 at a point laterally offset from the pad to connect the second redistribution layer to a redistribution layer analogous to layer 16.
• the solder ball can then be formed over the pad, with the buffer layer 14 lying between the solder ball and the pad.
• the pad instead of a second redistribution layer, the pad itself could be laterally extended. This arrangement is illustrated in figure 4, in which analogous components are numbered as in figure 2.
• the layer 18 could have a higher Young's modulus than layer 14. In some embodiments the layer 18 could be omitted or could not act as a buffer layer.
• the embodiments described above make use of solder balls. Instead of balls, solder bumps or other forms of discrete solder elements can be used.
• the buffer layer 14 could be homogeneous or could be formed of a stack of sublayers. Any one or more of those layers could have Young's Modulus of 2.5GPa or less.
• a Young's modulus of around 2.0GPa is especially advantageous for layer 14 because it provides beneficial results when the layer 14 has a thickness in the range from 5 to 10 microns, more preferably 7 to 8 microns. Outside that range it can become more difficult to form via holes through the layer 14 because the vias extend too far laterally or because it can be difficult to define a reliable contact through the via.
• the invention is especially suitable for use with chips that are to be incorporated into mobile devices, particularly handheld-portable devices such as mobile phones. Such devices are typically subject to considerable shocks and can particularly benefit from improved shock resistance.
• the chip conveniently implements mobile communication functionality, such as a radio transmitter and/or receiver.

Landscapes

• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Wire Bonding (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)

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• 2006
  • 2006-12-13 GB GB0624888A patent/GB2444775B/en active Active
• 2007
  • 2007-11-14 TW TW096143013A patent/TWI475621B/zh not_active IP Right Cessation
  • 2007-11-26 WO PCT/GB2007/004500 patent/WO2008071905A1/en not_active Ceased
  • 2007-11-26 US US12/518,262 patent/US9177885B2/en not_active Expired - Fee Related
  • 2007-11-26 JP JP2009540834A patent/JP5623080B2/ja not_active Expired - Fee Related
• 2013
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• 2015
  • 2015-08-27 US US14/837,426 patent/US9659894B2/en not_active Expired - Fee Related

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