TWI304616B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
TWI304616B
TWI304616B TW095128295A TW95128295A TWI304616B TW I304616 B TWI304616 B TW I304616B TW 095128295 A TW095128295 A TW 095128295A TW 95128295 A TW95128295 A TW 95128295A TW I304616 B TWI304616 B TW I304616B
Authority
TW
Taiwan
Prior art keywords
resin
semiconductor device
wiring
straight line
semiconductor substrate
Prior art date
Application number
TW095128295A
Other languages
Chinese (zh)
Other versions
TW200721314A (en
Inventor
Tatsuhiko Asakawa
Hiroki Kato
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200721314A publication Critical patent/TW200721314A/en
Application granted granted Critical
Publication of TWI304616B publication Critical patent/TWI304616B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1304616 九、發明說明: 【發明所屬之技術領域】 本發明關於半導體裝置及其製造方法。 【先前技術】 已知有在佈線基板上安裝半導體襞置(例如,參照特開平 2-272737號公報)之型式之電子模組。為了製造可靠性高的 電子模組,重要在於使佈線基板之佈線圖案與半導體裝置 之佈線電性連接。 本發明之目的在於提供安裝性高之半導體裝置及其製造 方法。 【發明内容】 (1)本發明之半導體裝置包含·· 半導體基板,其係具有電極; 樹脂突起,其係形成於上述半導體基板之形成有上述電 極之面上,構成沿著一直線延伸之形狀;及 佈線,其係與上述電極電性連接而成,形成於上述樹脂 突起上; 上述树如犬起具有沿著上述直線而愈離開上述樹脂突起 中央,高度愈低之傾斜區域; 上述佈'線以通過上述傾斜區域上之方式形《。依本發 明,可提供一種安裝性高之半導體裝置。 (2)在此半導體裝置中, 上述傾斜區域亦可以愈離開上述樹脂突起中央,寬度愈 窄之方式形成。 113449.doc 1304616 (3) 在此半導體裝置中, 上述半導體基板為半導體晶片; 上述樹脂突起亦可構成沿上述半導體基板之形成有上述 電極之面之一邊延伸之形狀。 (4) 在此半導體裝置中, 亦可使複數條上述佈線形成於一個上述樹脂突起上。 (5) 本發明之半導體裝置之製造方法包含: 準備具有電極之半導體基板之步驟; 在上述半導體基板之形成有上述電極之面上形成構成沿 一直線延伸之形狀之樹脂突起之步驟;及 將與上述電極電性連接之佈線形成於上述樹脂突起上之 步驟; 將上述樹脂突起以具有沿上述直線而愈離開上述樹脂突 起中央,高度愈低之傾斜區域之方式形成; 將上述佈線以通過上述傾斜區域上之方式形成。依本發 明,可製造一種安裝性優良之半導體裝置。 (6) 在此半導體裝置之製造方法中, 亦可將上述樹脂突起以上述傾斜區域愈離開上述樹脂突 起中央,寬度愈窄之方式形成。 (7) 在此半導體裝置之製造方法中, 形成上述樹脂突起之步驟亦可包含: 在上述半導體基板上將樹脂材料以沿一直線延伸且沿上 述直線而愈離開中央,寬度愈窄之方式設置之步驟;及 使上述樹脂材料硬化之步驟。 113449.doc 1304616 (8) 在此半導體裝置之製造方法中, 亦可將上述樹脂材料以構成一定厚度之方式設置; 使上述樹脂材料硬化收縮,而形成上述樹脂突起。 (9) 在此半導體裝置之製造方法中, 亦可將複數條上述佈線形成於一個上述樹脂突起上。 【實施方式】 以下,對於應用本發明之實施方式,參照圖式來說明之。 惟,本發明並不限於以下之實施方式。 以下,參照圖1(A)至圖1(C)來說明應用本發明之實施方 式之半導體裝置100。在此,圖i(A)係本發明之實施方式之 半導體裝置100之上視圖。此外,圖丨⑺)係圖“句之丨^ 線剖面圖’而圖UC)係圖1(A)之IC-IC線剖面圖。 本實施方式之半導體裝置如圖1(A)至圖1(c)所示,包含 半導體基板10。半導體基板1〇例如可為矽基板。半導體基 板10亦可為晶片狀(參照圖3)。亦即,半導體基板1〇亦可為 半導體晶片。或者,半導體基板丨〇亦可為晶圓狀(參照圖4)。 半導體基板10上亦可形成積體電路12(參照圖1(c))。積體電 路2之構^並無特別之限制,例如,亦可包含電晶體等之 主動元件、及電阻、線圈、電容等之被動元件。半導體基 板10為晶片狀時,半導體基板10之有積體電路12形成之面 (主動面)亦可為長方形。惟,半導體基板10之主動面亦可為 正方形。 半導體基板10如圖1(A)及圖1(C)所示,具有電極14。電 極14亦可電性連接於半導體基板1 〇之内部。電極14亦可與 113449.doc 1304616 積體電路12電性連接。或者,亦可在積體電路12中包含未 電f生連接之導電體而稱之為電極14。電極14亦可為半導體 基板之内部佈線之一部分。此時,電極14亦可為半導體基 板之内部佈線中與外部電性連接所用之部分。電極丨4亦可 以鋁或銅等之金屬來形成。電極14亦可沿著半導體基板1〇 之主動面之一邊排列。1304616 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor device and a method of manufacturing the same. [Prior Art] An electronic module of a type in which a semiconductor device is mounted on a wiring board (for example, see JP-A-2-272737) is known. In order to manufacture a highly reliable electronic module, it is important to electrically connect the wiring pattern of the wiring substrate to the wiring of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having high mountability and a method of manufacturing the same. SUMMARY OF THE INVENTION (1) A semiconductor device according to the present invention includes: a semiconductor substrate having an electrode; and a resin protrusion formed on a surface of the semiconductor substrate on which the electrode is formed to form a shape extending along a straight line; And a wiring electrically connected to the electrode and formed on the resin protrusion; wherein the tree has a sloped region which is further away from the center of the resin protrusion along the straight line and has a lower height; Shaped by the above-mentioned inclined area. According to the present invention, a highly mountable semiconductor device can be provided. (2) In the semiconductor device, the inclined region may be formed so as to be apart from the center of the resin protrusion and having a narrower width. (113) In the semiconductor device, the semiconductor substrate is a semiconductor wafer, and the resin protrusion may have a shape extending along one side of the surface of the semiconductor substrate on which the electrode is formed. (4) In the semiconductor device, a plurality of the wirings may be formed on one of the resin protrusions. (5) A method of manufacturing a semiconductor device according to the present invention, comprising: a step of preparing a semiconductor substrate having an electrode; a step of forming a resin protrusion constituting a shape extending in a straight line on a surface of the semiconductor substrate on which the electrode is formed; a step of electrically connecting the electrode to the resin protrusion; forming the resin protrusion so as to have an inclined region which is higher in height from the center of the resin protrusion along the straight line; and the wiring is passed through the tilt The way the area is formed. According to the present invention, a semiconductor device excellent in mountability can be manufactured. (6) In the method of manufacturing a semiconductor device, the resin protrusion may be formed such that the inclined region is apart from the center of the resin protrusion and the width is narrower. (7) In the method of manufacturing a semiconductor device, the step of forming the resin protrusion may include: disposing the resin material on the semiconductor substrate so as to extend along a straight line and further away from the center along the straight line, and the width is narrower. a step; and a step of hardening the above resin material. 113449.doc 1304616 (8) In the method of manufacturing a semiconductor device, the resin material may be provided to have a constant thickness; and the resin material may be hardened and shrunk to form the resin protrusion. (9) In the method of manufacturing a semiconductor device, a plurality of the wirings may be formed on one of the resin protrusions. [Embodiment] Hereinafter, an embodiment to which the present invention is applied will be described with reference to the drawings. However, the invention is not limited to the following embodiments. Hereinafter, a semiconductor device 100 to which an embodiment of the present invention is applied will be described with reference to Figs. 1(A) to 1(C). Here, Fig. i(A) is a top view of a semiconductor device 100 according to an embodiment of the present invention. In addition, Fig. 7(7) is a cross-sectional view of the IC-IC line of Fig. 1(A), and Fig. 1(A) to Fig. 1 As shown in (c), the semiconductor substrate 10 is included. The semiconductor substrate 1 may be, for example, a germanium substrate. The semiconductor substrate 10 may be in the form of a wafer (see FIG. 3). That is, the semiconductor substrate 1 may be a semiconductor wafer. The semiconductor substrate 丨〇 may be in the form of a wafer (see FIG. 4). The integrated circuit 12 may be formed on the semiconductor substrate 10 (see FIG. 1(c)). The configuration of the integrated circuit 2 is not particularly limited, for example, The active element such as a transistor or a passive element such as a resistor, a coil, or a capacitor may be included. When the semiconductor substrate 10 is in the form of a wafer, the surface (active surface) formed by the integrated circuit 12 of the semiconductor substrate 10 may be a rectangle. The active surface of the semiconductor substrate 10 may be square. The semiconductor substrate 10 has electrodes 14 as shown in Figs. 1(A) and 1(C). The electrodes 14 may be electrically connected to the inside of the semiconductor substrate 1 The electrode 14 can also be electrically connected to the 113449.doc 1304616 integrated circuit 12. Alternatively, The integrated circuit 12 includes an electrical conductor that is not electrically connected and is referred to as an electrode 14. The electrode 14 may also be a part of the internal wiring of the semiconductor substrate. In this case, the electrode 14 may also be internal and external to the semiconductor substrate. The electrode 丨 4 may be formed of a metal such as aluminum or copper, and the electrode 14 may be arranged along one side of the active surface of the semiconductor substrate 1 .

半導體基板10如圖1(B)及圖1(C)所示,亦可具有鈍化膜 16。鈍化膜16亦可以使電極14露出之方式形成。鈍化膜“ II 亦可具有使電極14露出之開口。鈍化膜例如可為Si〇2及SiN 等之無機絕緣膜。或者,鈍化膜16亦可為聚醯亞胺樹脂等 之有機絕緣膜。 本實施方式之半導體裝置如圖1(A)至圖1(c)所示,包含 在半導體晶片10上所形成之樹脂突起2〇。樹脂突起2〇形成 在半導體晶片10之有電極14形成之面上。樹脂突起2〇亦可 形成在鈍化膜16上。樹脂突起2〇之材料並無特別之限制, 亦適用已周知之任何材料。例如,樹脂突起2〇亦可以聚醯 • 亞胺樹脂、矽變性聚醯亞胺樹脂、環氧樹脂、矽變性環氧 树月日、苯環丁稀(BCB ; benz〇cycl〇butene)、聚苯并噁唑 (PBO ; polybenzoxaz〇ie)、苯酚樹脂樹脂等之樹脂形成。 樹脂突起20如圖1(A)所示為沿一直線以延伸之形狀。在 此直線21亦可為通過半導體基板1〇上之虛擬直線。半導體 基板1 0為半導體晶片時,樹脂突起2〇亦可為沿著半導體基 板10之-邊延伸之形狀。此外,半導體基板1〇之主動面為 長方形時,樹脂突起20亦可為沿著該長邊延伸之形狀。或 者,樹脂突起20亦可說成向一方向擴大之形狀。樹脂突起 H3449.doc 1304616 20表面亦可為曲面。樹脂突起2〇之剖面形狀如圖ye)所 示,亦可為半圓形。 樹脂突起20如圖1(A)及圖1(B)所示,具有沿直線21而愈 離樹脂突起20之中央時高度愈低之傾斜區域24。亦即,樹 月曰犬起20亦可為愈離该中央部時高度愈低之形狀。或者, 树月曰大起20可說成具有沿著一直線2 1 (連續地)變化高度之 構造,且愈離樹脂突起2〇之中央時高度愈低的形狀。一個 樹脂突起20亦可包含兩個傾斜區域24。此外,「樹脂突起2〇 之高度」亦可指以半導體基板1〇之有電極焊墊14形成之面 為基準的樹脂突起20之高度。 傾斜區域2 4亦可如圖丨(a )所示為愈離樹脂突起2 〇之中央 時寬度愈窄之形狀。亦即,樹脂突起2〇亦可為愈離該中央 部時寬度愈窄之形狀。或者,樹脂突起2〇可說成具有沿著 一直線21(連續地)變化寬度之構造,且愈離樹脂突起2〇之中 央時寬度愈窄的形狀。此外,此處所謂的「樹脂突起2〇之 寬度」亦可指樹脂突起20基端部的寬度。換言之,「樹脂突 起20之寬度」亦可指樹脂突起2〇之與半導體基板1〇相向之 面(底面)的寬度。惟,傾斜區域24亦可以寬度固定之方式形 成(未圖示)。 本實施方式之半導體裝置如圖i(A)至圖1(c)所示地包含 佈線30。佈線30電性連接於電極14。佈線3〇形成於(直至) 樹脂突起20上。此外,佈線3〇亦可以通過傾斜區域24上之 方式形成。此時,佈線3〇之與傾斜區域24重疊之部分亦可 以與直線21交又的方式延伸(參照圖1(A))。佈線3〇亦可以通 過樹脂突起20上端之方式形成。如圖1(A)及圖1(B)所示, 113449.doc •10- 1304616 亦可使複數條佈線30達到一個樹脂突起2〇上之方式形成。 惟,一個樹脂突起20上亦可僅形成一條佈線3〇(未圖示)。佈 線30之構造及材料並無特別之限制。例如,佈線亦可以 單層來形成。或者,佈線30亦可以複數層來形成。此時, 佈線30亦可包含:由鈦鎢或鈦所形成之第一層、及由金所 形成之第二層(未圖示)。 本實施方式之半導體裝置亦可具有上述構造。依此半導 體裝置100,可提供安裝性優良之半導體裝置。亦即,藉由 半導體裝置100,將可有效率地製造可靠性高之電子模組 1000(參照圖3)。以下說明該成效。 將半導體裝置100安裝於佈線基板之方法並無特別之限 制,然而,在此將參照圖2(A)至圖2(C)來說明一例。首先, 說明佈線基板40。佈線基板40亦可包含底基板42及佈線圖 案44。底基板42之材料並無特別之限制,不論為有機系或 無機系的材料均可,亦可為由此等之複合構造而成者。作 為底基板42,亦可利用由無機系材料所形成之基板。此外, 底基板42可為陶瓷基板或玻璃基板。底基板42為玻璃基板 時’佈線基板40亦可為電光學面板(液晶面板、電致發光面 板等)之一部分。佈線圖案44亦可由ITO(Indium Tin Oxide ; 銦錫氧)、Cr、A1等之金屬膜、金屬化合物、或此等之複合 膜所形成。此時,佈線圖案44亦可電性連接於驅動液晶之 電極(掃描電極、信號電極、對向電極等)。或者,底基板42 亦可為由聚乙烯對苯二酸甲酯(PET)所形成之基板或薄 膜。或者’作為底基板42亦可使用由聚醯亞胺樹脂所形成 113449.doc -11 - 1304616 之軟基板。作為軟基板,亦可使用FPC(FlexiMe Printed Circuit;軟性印刷電路)、TAB(Tape Aut〇mated B〇nding; 膠帶自動接合)技術所使用之膠帶。此時,佈線圖案44例如 可由銅(Cu)、鉻(Cr)、鈦(Τι)、鎳(Ni)、鈦鎢(τ“ w)中任何 一者層壓而成。並且,佈線圖案44包含電性連接部45。電 性連接部45為佈線圖案44中與其他構件電性連接用之部 分。此外,佈線圖案44亦可以其一部分通過底基板42内側 之方式形成。 以下,說明在佈線基板40上搭載半導體裝置1〇〇之步驟。 首先,如圖2(A)所示,將半導體裝置1〇〇配置於佈線基板 40,以使半導體裝置ι〇〇之佈線3〇(樹脂突起2〇)與佈線基板 40之佈線圖案44(電性連接部45)相向之方式對準。此時,可 在半導體裝置100與佈線基板4〇之間設置接著劑5〇。作為接 著劑50例如可利用薄膜狀之接著劑。或者,作為接著劑5〇, 亦可利用漿料狀之接著劑。接著劑5〇亦可為絕緣性之接著 劑。接著劑50亦可為樹脂系接著劑。之後,如圖2(B)所示 般地,擠壓半導體裝置1〇〇及佈線基板4〇,而使佈線3〇及佈 線圖案44(電性連接部45)接觸。在本步驟中,可藉由樹脂突 起2〇(佈線30)而使接著劑50流動(參照圖2(B))。此外,本步 驟亦可在加熱環境下進行。藉此,可提高接著劑50之流動 性。此外,在本步驟中,亦可藉由半導體基板1〇及佈線基 板40壓扁樹脂突起2〇,而使樹脂突起2〇彈性變形(參照圖 2(C))。如此一來’藉由樹脂突起2〇之彈性力,可壓住佈線 30之電性連接部45(佈線圖案44),因此,可製造電性連接可 113449.doc -12- 1304616 罪性同之電子模組。接著,亦可在將半導體裝置100搭載於 佈線基板40之步驟後,使接著劑50硬化,如圖2(c)所示般 地’形成接著層52。可藉由接著層52來維持半導體基板1〇 與佈線基板40之間之間隔。亦即,可藉由接著層52來維持 樹脂突起20彈性變形之狀態。例如,可藉由在壓扁樹脂突 起20之狀態(樹脂突起20彈性變形之狀態)下使接著劑5〇硬 化’而維持樹脂突起2〇彈性變形之狀態。 亦可藉由以上步驟而將半導體裝置1〇〇安裝於佈線基板 4〇。再者,亦可經由檢查步驟等來製造如圖3所示之電子模 組 1000 〇 如上述說明,在將半導體裝置100安裝於佈線基板40之步 驟中,預先在半導體裝置100與佈線基板4〇之間設置接著劑 50的情況中’將藉由樹脂突起2〇而使接著劑5〇流動。此時, 為了使半導體裝置100之佈線3〇與佈線圖案44(電性連接部 45)電性連接,重要在於以佈線3〇與電性連接部45之間不會 殘留接著劑50之方式進行半導體裝置之安裝步驟。換言 之’如在佈線基板40上安裝半導體裝置1〇〇之步驟中,能夠 有效率地由佈線30與電性連接部45之間排出接著劑50的 話,可有效率地製造可靠性高之電子模組。 然而,在接著劑50之流動阻抗高時,恐有因接著劑5〇而 使樹脂突起20受到大的施力之虞。特別,接著劑5〇向相互 阻礙流動之方向流動時,阻擋此之樹脂突起2〇所受之施力 會大,樹脂突起20之變形之可能性變高。樹脂突起2〇變形 時,佈線30與佈線圖案44(電性連接部45)之間會有接著劑5〇 113449.doc -13- 1304616 殘留’恐有對電子模組之可靠性造成影響之虞。 然而’如上所述,半導體裝置100之樹脂突起2〇具有傾斜 區域24 °亦即,樹脂突起20具有愈離其中央部時高度愈低 之部分。因此,利用半導體裝置1〇〇時,可使接著劑可使接 著劑50(僅)向離開樹脂突起2〇之中央部之方向流動。因此, 藉由樹脂突起20,能以不阻礙接著劑50之流動之方式(不相 互阻礙流動之方式)來使接著劑5 〇流動。如此一來,藉由樹 脂突起20,能夠由傾斜區域24(佈線3〇)與佈線基板4〇(電性 連接部45)之間,有效率且確實地使接著劑5〇排出。並且, 由於佈線30以通過傾斜區域24上之方式形成,因此,可使 佈線30與電性連接部45確實地電性連接。亦即,藉由半導 體裝置100’可有效率地製造可靠性高之電子模組。 此外,在傾斜區域24以愈離樹脂突起之中央部時寬度愈 窄之方式形成的情況中,可更有效率地使接著劑5〇排出。 因此,可提供安裝性更優良之半導體裝置。 此外,如先前之說明,樹脂突起20以愈離其中央部時高 度愈低之方式形成。換言之,樹脂突起2〇以愈靠中央部時 高度愈高之方式形成。因此,在將半導體裝置1〇〇安裝於平 坦之佈線基板的情況中’樹脂突起2〇愈靠中央部之區域所 受之施力會愈大而變形大。亦即,樹脂突起2〇具有愈靠近 中央部之區域愈容易受到破壞之形狀。然而,在傾斜區域 24以愈靠近樹脂突起20中央部之區域寬度愈寬之方式形成 的情況中,可提高該中央部之耐破壞性。因此,可提供可 靠性高之電子模組。 113449.doc -14· 1304616 以下,說明製造半導體裝置100之方法。圖4至圖5(B)係 為了說明製造半導體裝置100之方法之圖。 本實施方式之半導體裝置之製造方法可包含準備半導體 基板10。半導體基板1 〇如圖4所示亦可為晶圓狀。晶圓狀的 半導體基板10亦可包含複數個成為半導體裝置之區域u。 亦即,半導體基板丨〇亦可為複數個半導體晶片一體之構 造。惟,作為半導體基板亦可利用晶片狀之半導體基板丨〇。 本實施方式之半導體裝置之製造方法包含在半導體基板 1〇上形成樹脂突起20(參照圖1(A)至圖1(c))。樹脂突起2〇 形成於半導體基板10之有電極14形成之面上。樹脂突起20 形成為沿一直線2 1延伸之形狀。樹脂突起2〇以具有沿直線 2 1而愈離樹脂突起20中央時高度愈低之傾斜區域24之方式 形成。此外,亦可將樹脂突起2〇以傾斜區域24愈離樹脂突 起20中央時寬度愈窄之方式形成。 樹脂突起20形成之方法並無特別之限制。例如,樹脂突 起20亦可以在半導體基板1〇上設置樹脂材料22而其硬化之 方式來形成。此時,亦可將樹脂材料22如圖5(A)所示,以 沿一直線延伸且沿直線愈離中央時寬度愈窄之方式來設 置。亦即,亦可以平面形狀沿一直線延伸且沿直線愈離中 央時寬度愈窄之方式來設置樹脂材料22。此外,在此所言 之「樹脂材料22之寬度」可指樹脂材料22之基端部之寬度。 換言之,「樹脂材料22之寬度」亦可為樹脂材料22之與半導 體基板ίο相向之面(底面)之寬度。樹脂材料22亦可如圖5(B) 所示般地設置成固定厚度。此外,圖5(B)為圖5(A)之vb_vb 113449.doc -15- 1304616 線剖面圖。即使在樹脂材料22設定成固定厚度的情況中, 仍可藉由使其硬化收縮,以具有傾斜區域24之方式來形成 樹脂突起2〇(參照圖!⑽。依此方法,彳簡易且有效率地製 造樹脂突起20。惟,樹脂突起2〇形成之步驟並不限於此。 例如,亦可以模具成型方式來形成樹脂突起2〇。 本實施方式之半導體裝置之製造方法包含形成佈線3〇。 料30以與電極14電性連接之方式形成。佈線3〇形成至樹 脂突起20上。佈線3〇以通過傾斜區域24上之方式形成。亦 可以一個樹脂突起20上通過複數條佈線3〇之方式來進行本 步驟。佈線30形成之方法並無特別之限制,可適用已周知 之任何方法。 亦可藉由以上之步驟或進一步經由檢查步驟及切割步驟 來形成半導體裝置100(參照圖1(Α)至圖。如此一來, 可製造安裝性優良之半導體裝置。 以下參照圖式來說明應用本發明之實施方式之變形例的 半導體裝置。圖6(A)及圖6(B)係為了說明本變形例之半導 體裝置之圖。 圖6(A)及圖6(B)所示之半導體裝置包含樹脂突起6〇。樹 脂突起60如圖6(A)所示具有沿一直線61延伸之形狀。樹脂 突起60包含中央區域62。中央區域62亦可為沿著直線“而 高度不變化之形狀。亦即,中央區域62亦可為上端面沿著 直線61為平坦。此外,樹脂突起6〇包含傾斜區域64。傾斜 區域64配置於中央區域62之兩側。詳細而言,傾斜區域64 沿著直線6 1 ’配置在中央區域62之兩側。傾斜區域64為沿 113449.doc -16- 1304616 著直線61而愈離中央區域62時高度愈低之區域。此外,樹 脂突起60亦可為沿著直線61而寬度不變之形狀。亦即,傾 區域64為固^寬度。並且’中央區域62及傾斜區域64亦 可為相同寬度。然而,樹脂突起6〇亦可為沿著直線61而愈 離树知犬起60中央時寬度愈窄之形狀(參照圖1(A))。或而, 树月曰大起60為中央區域62寬度固定,傾斜區域以沿著直線 61而愈離樹脂突起6〇中央時寬度愈窄之形狀(未圖示)。 並且,如圖6(A)及圖6(B)所示,佈線30以通過樹脂突起 6〇上之方式形成。佈線3〇亦可以通過中央區域62之方式形 成。此外,佈線30亦可以通過傾斜區域64上之方式形成。 佈線3〇亦可以在樹脂突起6〇上與直線61交叉之方向延伸之 方式形成。然而,佈線30亦可避開中央區域62上而僅在佃 升區域64上形成。 藉由此半導體裝置,亦可由樹脂突起與佈線基板之間有 放率且確實地排出樹脂材料。為此,可提供可有效率地製 造可靠性高之電子模組的半導體裝置。 此外,本發明並不限於上述實施方式,可有各種變形。 例如,本發明包含與實施方式所說明之構造實質上相同之 構造(例如功能、方法及結果相同之構造,&目的及成效相 同之構造)。此外,本發明包含置換以實施方式說明之構造 中非本質部分之構造。再者,本發明包含可發揮與以實施 方式所說明之構造相同作用成效之構造或達成相同目的之 構造。此外,本發明包含在以實施方式所說明之構造中附 加周知技術之構造。 H3449.doc -17- 1304616 【圖式簡單說明】 圖1(A)至圖1(C)係為了說明本發明之實施方式之半導體 裝置之圖。 圖2(A)至圖2(C)係為了說明本發明之實施方式之半導體 装置之圖。 圖3係安裝有本發明之實施方式之半導體裝置之電子模 組之圖。 圖4係為了說明本發明之實施方式之半導體裝置之製造 方法之圖 圖5(A)及圖5(B)係為了說明本發明之實施方式之半導體 裝置之製造方法之圖。 圖6(A)及圖6(B)係為了說明本發明之實施方式之變形例 之半導體裝置之圖 【主要元件符號說明】 10 半導體基板 11 區域 12 積體電路 14 電極 16 鈍化膜 20 樹脂突起 21 直線 22 樹脂材料 24 傾斜區域 30 佈線 113449.doc -18- 1304616 40 佈線基板 42 底基板 44 佈線圖案 45 電性連接部 50 接著劑 52 接著層 60 樹脂突起 61 直線 62 中央區域 64 傾斜區域 100 半導體裝置 113449.docThe semiconductor substrate 10 may have a passivation film 16 as shown in Figs. 1(B) and 1(C). The passivation film 16 can also be formed in such a manner that the electrode 14 is exposed. The passivation film "II" may have an opening for exposing the electrode 14. The passivation film may be, for example, an inorganic insulating film such as Si〇2 or SiN. Alternatively, the passivation film 16 may be an organic insulating film such as a polyimide resin. As shown in Figs. 1(A) to 1(c), the semiconductor device of the embodiment includes a resin bump 2 formed on the semiconductor wafer 10. The resin bump 2 is formed on the surface of the semiconductor wafer 10 where the electrode 14 is formed. The resin protrusions 2 can also be formed on the passivation film 16. The material of the resin protrusions 2 is not particularly limited, and any of the well-known materials can be applied. For example, the resin protrusions 2 can also be polymerized with an imide resin.矽-denatured polyimine resin, epoxy resin, ruthenium-denatured epoxy tree, phenylcyclobutylene (BCB; benz〇cycl〇butene), polybenzoxazole (PBO; polybenzoxaz〇ie), phenol resin The resin protrusion 20 is formed in a shape extending along a straight line as shown in Fig. 1(A), and the line 21 may be a virtual straight line passing through the semiconductor substrate 1. When the semiconductor substrate 10 is a semiconductor wafer, The resin protrusion 2〇 can also be along the semi-conductive Further, when the active surface of the semiconductor substrate 1 is rectangular, the resin protrusions 20 may have a shape extending along the long sides. Alternatively, the resin protrusions 20 may be enlarged in one direction. The shape of the resin protrusion H3449.doc 1304616 20 may also be a curved surface. The cross-sectional shape of the resin protrusion 2〇 is shown in Fig. ye), and may also be semicircular. The resin protrusion 20 is as shown in Fig. 1(A) and Fig. 1 ( As shown in B), the inclined region 24 having a lower height as it goes away from the center of the resin projection 20 along the straight line 21, that is, the tree moon dog 20 can also be a shape having a lower height from the center portion. Alternatively, the tree-shaped ridge 20 may be said to have a configuration in which the height is changed along the straight line 2 1 (continuously), and the height is lower as it is away from the center of the resin protrusion 2 。. One resin protrusion 20 may also include two Further, the "height of the resin protrusions 2" may be the height of the resin protrusions 20 based on the surface of the semiconductor substrate 1 on which the electrode pads 14 are formed. The inclined region 2 4 may also have a shape in which the width becomes narrower as it goes from the center of the resin protrusion 2 所示 as shown in Fig. (a). That is, the resin protrusion 2〇 may have a shape in which the width becomes narrower as it goes away from the center portion. Alternatively, the resin protrusions 2'' can be said to have a structure in which the width is changed (continuously) along a straight line 21, and the shape becomes narrower as the width of the resin protrusions 2''''''' Here, the "width of the resin projection 2" as used herein may also mean the width of the base end portion of the resin projection 20. In other words, the "width of the resin projection 20" may also refer to the width of the surface (bottom surface) of the resin projection 2 that faces the semiconductor substrate 1A. However, the inclined region 24 can also be formed in a fixed width (not shown). The semiconductor device of the present embodiment includes the wiring 30 as shown in Figs. i(A) to 1(c). The wiring 30 is electrically connected to the electrode 14. The wiring 3 is formed on (up to) the resin protrusions 20. Further, the wiring 3〇 can also be formed by the inclined region 24. At this time, the portion of the wiring 3 which overlaps with the inclined region 24 may extend so as to intersect the straight line 21 (see Fig. 1(A)). The wiring 3 can also be formed by the upper end of the resin projection 20. As shown in Fig. 1(A) and Fig. 1(B), 113449.doc •10-1304616 can also be formed in such a manner that a plurality of wirings 30 reach one of the resin projections 2''. However, only one wiring 3 (not shown) may be formed on one of the resin protrusions 20. The construction and material of the wiring 30 are not particularly limited. For example, the wiring can also be formed in a single layer. Alternatively, the wiring 30 may be formed in a plurality of layers. At this time, the wiring 30 may further include a first layer formed of titanium tungsten or titanium and a second layer (not shown) formed of gold. The semiconductor device of the present embodiment may have the above configuration. According to this semiconductor device 100, a semiconductor device excellent in mountability can be provided. In other words, the semiconductor device 100 can efficiently manufacture the highly reliable electronic module 1000 (see Fig. 3). The results are described below. The method of mounting the semiconductor device 100 on the wiring board is not particularly limited. However, an example will be described with reference to Figs. 2(A) to 2(C). First, the wiring substrate 40 will be described. The wiring board 40 may also include a base substrate 42 and a wiring pattern 44. The material of the base substrate 42 is not particularly limited, and may be any organic or inorganic material, or may be a composite structure of the above. As the base substrate 42, a substrate formed of an inorganic material can also be used. Further, the base substrate 42 may be a ceramic substrate or a glass substrate. When the base substrate 42 is a glass substrate, the wiring substrate 40 may be a part of an electro-optical panel (such as a liquid crystal panel or an electroluminescence panel). The wiring pattern 44 may be formed of a metal film of ITO (Indium Tin Oxide), Cr, A1 or the like, a metal compound, or a composite film thereof. At this time, the wiring pattern 44 may be electrically connected to an electrode (scanning electrode, signal electrode, counter electrode, or the like) that drives the liquid crystal. Alternatively, the base substrate 42 may be a substrate or a film formed of polyethylene terephthalate (PET). Alternatively, as the base substrate 42, a soft substrate formed of a polyimide film of 113449.doc -11 - 1304616 may be used. As the flexible substrate, an adhesive tape used in FPC (FlexiMe Printed Circuit) or TAB (Tape Aut〇mated B〇nding) technology can also be used. At this time, the wiring pattern 44 may be laminated, for example, of any one of copper (Cu), chromium (Cr), titanium (ITO), nickel (Ni), and titanium tungsten (τ"w). The electrical connection portion 45 is a portion for electrically connecting the other members to the wiring pattern 44. Further, the wiring pattern 44 may be formed so that a part thereof passes through the inner side of the base substrate 42. Hereinafter, the wiring substrate will be described. The step of mounting the semiconductor device 1 is performed on 40. First, as shown in FIG. 2(A), the semiconductor device 1 is placed on the wiring substrate 40 so that the wiring of the semiconductor device is 〇 (resin protrusion 2 〇 The wiring pattern 44 (electrical connection portion 45) of the wiring substrate 40 is aligned so as to be opposed to each other. In this case, an adhesive 5 is provided between the semiconductor device 100 and the wiring substrate 4A. A film-like adhesive agent may be used. Alternatively, a paste-like adhesive may be used as the adhesive agent 5. The adhesive agent may be an insulating adhesive. The adhesive 50 may be a resin-based adhesive. As shown in FIG. 2(B), the semiconductor device 1 is extruded. And the wiring board 4〇, and the wiring 3〇 and the wiring pattern 44 (electrical connection part 45) are contacted. In this step, the adhesive 50 can be made to flow by the resin protrusion 2 (wiring 30) (refer FIG. (B)) Further, this step can also be carried out in a heating environment, whereby the fluidity of the adhesive 50 can be improved. Further, in this step, the semiconductor substrate 1 and the wiring substrate 40 can be crushed. The resin projection 2 is elastically deformed by the resin projection 2 (see Fig. 2(C)). Thus, by the elastic force of the resin projection 2, the electrical connection portion 45 of the wiring 30 can be pressed (wiring pattern) 44) Therefore, an electronic module capable of electrically connecting 113449.doc -12-1304616 can be manufactured. Next, after the step of mounting the semiconductor device 100 on the wiring substrate 40, the adhesive 50 can be cured. The bonding layer 52 is formed as shown in Fig. 2(c). The interval between the semiconductor substrate 1A and the wiring substrate 40 can be maintained by the bonding layer 52. That is, the resin bump can be maintained by the bonding layer 52. 20 state of elastic deformation, for example, by the state of flattening the resin protrusion 20 (resin In the state in which the adhesive is elastically deformed, the adhesive 5 is hardened to maintain the state in which the resin projections 2 are elastically deformed. The semiconductor device 1 can be attached to the wiring substrate 4 by the above steps. The electronic module 1000 shown in FIG. 3 can be manufactured through an inspection step or the like. As described above, in the step of mounting the semiconductor device 100 on the wiring substrate 40, the semiconductor device 100 and the wiring substrate 4 are disposed in advance. In the case of the agent 50, the adhesive 5 〇 is caused to flow by the resin protrusions 2 。. At this time, in order to electrically connect the wiring 3 半导体 of the semiconductor device 100 and the wiring pattern 44 (electrical connection portion 45 ), it is important that The mounting step of the semiconductor device is performed so that the adhesive 50 does not remain between the wiring 3A and the electrical connection portion 45. In other words, in the step of mounting the semiconductor device 1 on the wiring substrate 40, the adhesive 50 can be efficiently discharged between the wiring 30 and the electrical connection portion 45, and the highly reliable electronic mold can be efficiently manufactured. group. However, when the flow resistance of the adhesive 50 is high, there is a fear that the resin projections 20 are subjected to a large urging force due to the adhesive 5 虞. In particular, when the adhesive agent 5 流动 flows in the direction in which the flow is prevented from flowing, the urging force of the resin projections 2 阻挡 is greatly increased, and the possibility of deformation of the resin projections 20 is increased. When the resin protrusion 2 is deformed, there is a possibility that the adhesive 5 〇 113449.doc -13 - 1304616 remains between the wiring 30 and the wiring pattern 44 (electrical connection portion 45), which may affect the reliability of the electronic module. . However, as described above, the resin projection 2 of the semiconductor device 100 has an inclined region of 24 °, i.e., the resin projection 20 has a portion where the height is lower as it goes from the central portion thereof. Therefore, when the semiconductor device is used, the adhesive can cause the adhesive 50 (only) to flow in a direction away from the central portion of the resin projections 2''. Therefore, the resin protrusions 20 can flow the adhesive 5 〇 without hindering the flow of the adhesive 50 (the flow is not mutually inhibited). As a result, the resin protrusion 20 can efficiently and reliably discharge the adhesive 5 由 between the inclined region 24 (wiring 3) and the wiring board 4 (electrical connection portion 45). Further, since the wiring 30 is formed to pass through the inclined region 24, the wiring 30 and the electrical connecting portion 45 can be surely electrically connected. That is, the highly reliable electronic module can be efficiently manufactured by the semiconductor device 100'. Further, in the case where the inclined region 24 is formed to have a narrower width as it goes away from the central portion of the resin projection, the adhesive 5〇 can be discharged more efficiently. Therefore, a semiconductor device having better mountability can be provided. Further, as previously explained, the resin projections 20 are formed in such a manner that the height is lower as it goes from the center portion thereof. In other words, the resin projections 2 are formed in such a manner that the height is higher as it goes closer to the center portion. Therefore, in the case where the semiconductor device 1 is mounted on a flat wiring substrate, the force applied to the region where the resin projection 2 is located closer to the center portion is larger and the deformation is large. That is, the resin protrusion 2 has a shape in which the region closer to the center portion is more susceptible to damage. However, in the case where the inclined region 24 is formed so that the width of the region closer to the central portion of the resin projection 20 is wider, the damage resistance of the central portion can be improved. Therefore, an electronic module with high reliability can be provided. 113449.doc -14· 1304616 Hereinafter, a method of manufacturing the semiconductor device 100 will be described. 4 to 5(B) are diagrams for explaining a method of manufacturing the semiconductor device 100. The method of manufacturing the semiconductor device of the present embodiment may include preparing the semiconductor substrate 10. The semiconductor substrate 1 can also be in the form of a wafer as shown in FIG. The wafer-shaped semiconductor substrate 10 may also include a plurality of regions u serving as semiconductor devices. That is, the semiconductor substrate 丨〇 can also be a monolithic structure of a plurality of semiconductor wafers. However, a wafer-shaped semiconductor substrate 亦可 can also be used as the semiconductor substrate. The method of manufacturing a semiconductor device according to the present embodiment includes forming a resin bump 20 on a semiconductor substrate 1 (see Figs. 1(A) to 1(c)). The resin bump 2 is formed on the surface of the semiconductor substrate 10 where the electrode 14 is formed. The resin protrusions 20 are formed in a shape extending along the straight line 2 1 . The resin projection 2 is formed so as to have a sloped region 24 which is lower in height from the center of the resin projection 20 along the straight line 2 1 . Further, the resin projections 2 may be formed such that the width of the inclined region 24 becomes narrower as it goes away from the center of the resin projection 20. The method of forming the resin protrusions 20 is not particularly limited. For example, the resin bumps 20 may be formed by providing a resin material 22 on the semiconductor substrate 1 and hardening it. At this time, as shown in Fig. 5(A), the resin material 22 may be provided so as to extend along a straight line and become narrower as the straight line is further away from the center. That is, the resin material 22 may be provided in such a manner that the planar shape extends along the straight line and the width becomes narrower as the straight line is further away from the center. Further, the "width of the resin material 22" as used herein may mean the width of the base end portion of the resin material 22. In other words, the "width of the resin material 22" may be the width of the surface (bottom surface) of the resin material 22 facing the semiconductor substrate ίο. The resin material 22 may be provided to have a fixed thickness as shown in Fig. 5(B). In addition, FIG. 5(B) is a cross-sectional view taken along line vb_vb 113449.doc -15-1304616 of FIG. 5(A). Even in the case where the resin material 22 is set to a fixed thickness, the resin protrusions 2〇 can be formed by having the inclined regions 24 by hardening and shrinking (refer to Fig. (10). According to this method, 彳 is simple and efficient The resin protrusions 20 are produced. The step of forming the resin protrusions 2 is not limited thereto. For example, the resin protrusions 2 may be formed by a mold forming method. The method of manufacturing the semiconductor device of the present embodiment includes forming the wirings 3〇. 30 is formed in electrical connection with the electrode 14. The wiring 3 is formed on the resin protrusion 20. The wiring 3 is formed by passing over the inclined region 24. It is also possible to pass a plurality of wirings 3 on one of the resin protrusions 20. This method is carried out. The method of forming the wiring 30 is not particularly limited, and any known method can be applied. The semiconductor device 100 can also be formed by the above steps or further through the inspection step and the dicing step (refer to FIG. 1 (Α According to the figure, a semiconductor device excellent in mountability can be manufactured. Hereinafter, a modification to which an embodiment of the present invention is applied will be described with reference to the drawings. 6(A) and 6(B) are diagrams for explaining the semiconductor device of the present modification. The semiconductor device shown in Figs. 6(A) and 6(B) includes a resin bump 6〇. 60 has a shape extending along a straight line 61 as shown in Fig. 6(A). The resin protrusion 60 includes a central portion 62. The central portion 62 may also have a shape that does not change in height along a straight line. That is, the central portion 62 may also The upper end surface is flat along the straight line 61. Further, the resin protrusions 6A include inclined regions 64. The inclined regions 64 are disposed on both sides of the central portion 62. In detail, the inclined regions 64 are arranged along the straight line 6 1 ' in the central region. The two sides of the 62. The inclined region 64 is a region where the height is lower as the distance from the central portion 62 along the straight line 61 of 113449.doc -16 - 1304616. Further, the resin protrusion 60 may have a constant width along the straight line 61. The shape, that is, the tilting area 64 is a fixed width, and the central area 62 and the inclined area 64 may be the same width. However, the resin protrusions 6〇 may also be along the straight line 61 and further away from the tree. The shape with the narrower width (refer to Fig. 1(A)). Or, The moon swell 60 is a width in which the central portion 62 is fixed, and the inclined region has a narrower width (not shown) as it goes away from the center of the resin projection 6 沿着 along the straight line 61. Further, as shown in Fig. 6(A) and Fig. 6 As shown in (B), the wiring 30 is formed so as to pass through the resin projection 6. The wiring 3 can also be formed by the central portion 62. Further, the wiring 30 can be formed by the inclined portion 64. Alternatively, the resin protrusions 6A may be formed to extend in a direction intersecting the straight line 61. However, the wiring 30 may be formed only on the lift-up region 64 while avoiding the central portion 62. By means of the semiconductor device, resin may also be used. The protrusion and the wiring substrate have a discharge rate and reliably discharge the resin material. For this reason, it is possible to provide a semiconductor device which can efficiently manufacture an electronic module having high reliability. Further, the present invention is not limited to the above embodiment, and various modifications are possible. For example, the present invention includes configurations substantially the same as those described in the embodiments (e.g., configurations having the same functions, methods, and results, and configurations having the same objectives and effects). Furthermore, the invention encompasses configurations that replace non-essential portions of the construction described in the embodiments. Furthermore, the present invention encompasses a structure that can achieve the same effect as the structure described in the embodiment or achieve the same purpose. Further, the present invention encompasses a configuration in which a well-known technique is added to the configuration described in the embodiment. H3449.doc -17- 1304616 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(A) to Fig. 1(C) are diagrams for explaining a semiconductor device according to an embodiment of the present invention. 2(A) to 2(C) are diagrams for explaining a semiconductor device according to an embodiment of the present invention. Fig. 3 is a view showing an electronic module in which a semiconductor device of an embodiment of the present invention is mounted. 4 is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 5(A) and 5(B) are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 6(A) and 6(B) are diagrams for explaining a semiconductor device according to a modification of the embodiment of the present invention. [Main element symbol description] 10 Semiconductor substrate 11 Area 12 Integrated circuit 14 Electrode 16 Passivation film 20 Resin protrusion 21 Straight line 22 Resin material 24 Slanted area 30 Wiring 113449.doc -18- 1304616 40 Wiring board 42 Substrate 44 Wiring pattern 45 Electrical connection 50 Adhesive 52 Next layer 60 Resin protrusion 61 Straight line 62 Central area 64 Tilt area 100 Semiconductor Device 113449.doc

Claims (1)

1304616 十、申請專利範圍: 1· 一種半導體裝置,其包含: 半導體基板,其係具有電極; 樹脂突起,其係形成於上述半導體基板之形成有上述 電極之面上,構成沿著一直線延伸之形狀,·及 佈線,其係與上述電極電性連接而成,形成於上述樹 脂突起上; 上述知ί月曰犬起具有、沿著上述直線而愈離開i述樹脂突 起中央,高度愈低之傾斜區域; 上述佈線以通過上述傾斜區域上之方式形成。 2·如請求項1之半導體裝置,其中 上述傾斜區域以愈離開上述樹脂突起中央,寬度愈窄 之方式形成。 3 ·如請求項1之半導體裝置,其中 上述半導體基板為半導體晶片; 上述樹脂突起構成沿上述半導體基板之形成有上述電 極之面之一邊延伸之形狀。 4·如請求項1至3中任一項之半導體裝置,其中 複數條上述佈線形成在一個上述樹脂突起上。 5· 一種半導體裝置之製造方法,其包含: 準備具有電極之半導體基板之步驟; 在上述半導體基板之形成有上述電極之面上形成構成 沿一直線延伸之形狀之樹脂突起之步驟;及 將與上述電極電性連接之佈線形成於上述樹脂突起上 H3449.doc 1304616 之步驟; 將上述樹脂突起以具有沿上述直線愈離開上述樹脂突 起中央,高度愈低之傾斜區域之方式形成; 將上述佈線以通過上述傾斜區域上之方式形成。 6·如請求項5之半導體裝置之製造方法,其中 將上述樹脂突起以上述傾斜區域愈離開上述樹脂突起 中央,寬度愈窄之方式形成。 _ 7·如請求項6之半導體裝置之製造方法,其中 形成上述樹脂突起之步驟包含·· 在上述半導體基板上將樹脂材料以沿一直線延伸且 沿上述直線而愈離開中央,寬度愈窄之方式設置之步 驟;及 使述上樹脂材料硬化之步驟。 8·如請求項7之半導體裝置之製造方法,其中 將上述樹脂材料以構成一定厚度之方式設置; • 使上述樹脂材料硬化收縮,而形成上述樹脂突起。 9·如請求項5至8中任一項之半導體裝置之製造方法,其中 將複數條上述佈線形成於一個上述樹脂突起上。 113449.doc -2 -1304616 X. Patent Application Range: 1. A semiconductor device comprising: a semiconductor substrate having an electrode; and a resin protrusion formed on a surface of the semiconductor substrate on which the electrode is formed to form a shape extending along a straight line And wiring, which is electrically connected to the electrode and formed on the resin protrusion; the above-mentioned squirrel has a slope which is further away from the center of the resin protrusion along the straight line, and the inclination is lower Area; the above wiring is formed by passing over the above inclined area. 2. The semiconductor device according to claim 1, wherein the inclined region is formed to be narrower in width from a center of the resin protrusion. The semiconductor device according to claim 1, wherein the semiconductor substrate is a semiconductor wafer; and the resin protrusions have a shape extending along one side of the surface of the semiconductor substrate on which the electrode is formed. The semiconductor device according to any one of claims 1 to 3, wherein the plurality of wires are formed on one of the resin protrusions. 5. A method of manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate having an electrode; a step of forming a resin protrusion constituting a shape extending in a straight line on a surface of the semiconductor substrate on which the electrode is formed; and a step of electrically connecting the electrodes to the resin protrusions H3449.doc 1304616; forming the resin protrusions so as to have an inclined region which is lower in height from the center of the resin protrusions along the straight line; The above inclined region is formed in a manner. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the resin protrusion is formed such that the tapered region is apart from the center of the resin protrusion and the width is narrower. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the resin protrusion includes: forming a resin material on the semiconductor substrate in a manner of extending along a straight line and moving away from the center along the straight line, and the width is narrower a step of setting; and a step of hardening the resin material. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the resin material is provided to have a constant thickness; and the resin material is hardened and shrunk to form the resin protrusion. The method of manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the plurality of wires are formed on one of the resin protrusions. 113449.doc -2 -
TW095128295A 2005-08-02 2006-08-02 Semiconductor device and method of manufacturing the same TWI304616B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005223805A JP4645832B2 (en) 2005-08-02 2005-08-02 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW200721314A TW200721314A (en) 2007-06-01
TWI304616B true TWI304616B (en) 2008-12-21

Family

ID=37700266

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095128295A TWI304616B (en) 2005-08-02 2006-08-02 Semiconductor device and method of manufacturing the same

Country Status (4)

Country Link
US (1) US7728424B2 (en)
JP (1) JP4645832B2 (en)
CN (1) CN100454531C (en)
TW (1) TWI304616B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4046069B2 (en) * 2003-11-17 2008-02-13 ソニー株式会社 Solid-state imaging device and manufacturing method of solid-state imaging device
JP4273356B2 (en) 2007-02-21 2009-06-03 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP4572376B2 (en) * 2007-07-30 2010-11-04 セイコーエプソン株式会社 Semiconductor device manufacturing method and electronic device manufacturing method
JP4352279B2 (en) * 2007-08-21 2009-10-28 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP4737466B2 (en) * 2009-02-09 2011-08-03 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP5652100B2 (en) * 2010-10-05 2015-01-14 ソニー株式会社 Display panel, display device, lighting panel and lighting device, and display panel and lighting panel manufacturing method
KR101897653B1 (en) * 2017-03-06 2018-09-12 엘비세미콘 주식회사 Methods of fabricating compliant bump

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02272737A (en) 1989-04-14 1990-11-07 Citizen Watch Co Ltd Projecting electrode structure of semiconductor and formation of projecting electrode
JPH03231437A (en) * 1990-02-06 1991-10-15 Ricoh Co Ltd Forming method for protruding electrode
US5261158A (en) * 1991-01-22 1993-11-16 Hughes Aircraft Company Method of forming a resilient interconnection bridge
JP2833326B2 (en) * 1992-03-03 1998-12-09 松下電器産業株式会社 Electronic component mounted connector and method of manufacturing the same
JPH10125734A (en) * 1996-10-24 1998-05-15 Matsushita Electric Ind Co Ltd Semiconductor unit and manufacturing method thereof
US5783465A (en) * 1997-04-03 1998-07-21 Lucent Technologies Inc. Compliant bump technology
JP2001110831A (en) 1999-10-07 2001-04-20 Seiko Epson Corp External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment
JP2001127256A (en) * 1999-10-29 2001-05-11 Fuji Xerox Co Ltd Semiconductor device
DE10016132A1 (en) * 2000-03-31 2001-10-18 Infineon Technologies Ag Electronic component for electronic devices comprises electronic switch and conducting paths on surface of the component to electrically connect the switch with metal-coated protrusions made from rubber-elastic insulating material
JP3935370B2 (en) * 2002-02-19 2007-06-20 セイコーエプソン株式会社 Bumped semiconductor element manufacturing method, semiconductor device and manufacturing method thereof, circuit board, and electronic device
JP2004335660A (en) * 2003-05-06 2004-11-25 Sony Corp Semiconductor device, its manufacturing method, wiring board, and its manufacturing method
JP2005101527A (en) * 2003-08-21 2005-04-14 Seiko Epson Corp Electronic component mounting structure, electrooptic device, electronic equipment, and method of mounting electronic component
JP2005109100A (en) * 2003-09-30 2005-04-21 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
JP4218622B2 (en) * 2003-10-09 2009-02-04 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP3873986B2 (en) * 2004-04-16 2007-01-31 セイコーエプソン株式会社 Electronic component, mounting structure, electro-optical device, and electronic apparatus
JP2005340761A (en) * 2004-04-27 2005-12-08 Seiko Epson Corp Packaging method of semiconductor device, circuit board, electro-optical device, and electronic apparatus

Also Published As

Publication number Publication date
CN100454531C (en) 2009-01-21
US20070029652A1 (en) 2007-02-08
US7728424B2 (en) 2010-06-01
JP4645832B2 (en) 2011-03-09
JP2007042770A (en) 2007-02-15
CN1909221A (en) 2007-02-07
TW200721314A (en) 2007-06-01

Similar Documents

Publication Publication Date Title
TWI304616B (en) Semiconductor device and method of manufacturing the same
US20060049527A1 (en) Electronic device and method of manufacturing the same
TWI323030B (en) Semiconductor device
US7582967B2 (en) Semiconductor device, electronic module, and method of manufacturing electronic module
JP4145902B2 (en) Semiconductor device and manufacturing method thereof
JP2004327480A (en) Semiconductor device and its manufacturing process, electronic apparatus and its manufacturing process, and electronic apparatus
TW201029081A (en) Semiconductor device
KR100225398B1 (en) Bonding structure of semiconductor bump and its method
TWI236720B (en) Semiconductor device
JP4273347B2 (en) Semiconductor device
JP4888650B2 (en) Semiconductor device and method for manufacturing electronic device
JP2007019410A (en) Semiconductor device, and method of manufacturing electronic module
JP2008109024A (en) Semiconductor, electronic device, and method for manufacturing electronic device
JP2004363319A (en) Mount substrate and semiconductor device
US20040104113A1 (en) External electrode connector
JP4873144B2 (en) Electronic device manufacturing method and semiconductor device
JP2004071906A (en) Semiconductor device
JP3663036B2 (en) Semiconductor device and manufacturing method thereof
JP2008177404A (en) Semiconductor device, semiconductor module, and manufacturing method thereof
KR100755354B1 (en) Semiconductor device
JP5299626B2 (en) SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD
JP4858161B2 (en) Semiconductor device and method for manufacturing electronic device
JP2010171191A (en) Semiconductor device, and semiconductor module and manufacturing method thereof
JP2008103584A (en) Semiconductor device, electronic device, and their manufacturing methods
JP2009049188A (en) Semiconductor device, its manufacturing method and electronic device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees