KR100225398B1 - Bonding structure of semiconductor bump and its method - Google Patents
Bonding structure of semiconductor bump and its methodInfo
- Publication number
- KR100225398B1 KR100225398B1 KR1019950046106A KR19950046106A KR100225398B1 KR 100225398 B1 KR100225398 B1 KR 100225398B1 KR 1019950046106 A KR1019950046106 A KR 1019950046106A KR 19950046106 A KR19950046106 A KR 19950046106A KR 100225398 B1 KR100225398 B1 KR 100225398B1
- Authority
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- Prior art keywords
- bump
- pad
- insulating film
- semiconductor
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000002245 particle Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 14
- 239000004973 liquid crystal related substance Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 25
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000010410 layer Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 239000010409 thin film Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000010931 gold Substances 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 범프의 본딩구조 및 방법에 관한 것으로 반도체기판 위에 형성된 제1패드와, 상기 제1패드위에 형성된 범프와, 상기 범프의 측면과 상부표면의 적어도 일부분에 형성된 절연막과, 상기 범프상측 표면에 분포하는 도전입자와, 상기 도전입자를 통해 상기 범프와 전기적으로 접속되는 제2패드로 구성됨을 특징으로 하며, 파인 피치의 소자 등에 적용이 용이하고, 부수적으로 콘택저항을 낮출 수 있는 이점을 가진다.The present invention relates to a bonding structure and method of a semiconductor bump, comprising: a first pad formed on a semiconductor substrate, a bump formed on the first pad, an insulating film formed on at least a portion of a side surface and an upper surface of the bump, and a bump upper surface And a second pad electrically connected to the bump through the conductive particles, the conductive particles being distributed to the second pad, and having an advantage of being easy to be applied to a fine pitch element or the like and consequently lowering the contact resistance. .
Description
제1도는 종래의 반도체 기판 범프의 단면도.1 is a cross-sectional view of a conventional semiconductor substrate bump.
제2도는 종래의 반도체 기판 범프의 실제 본딩 상태를 예시한 단면도.2 is a cross-sectional view illustrating the actual bonding state of a conventional semiconductor substrate bump.
제3도는 본 발명의 반도체 기판 범프의 구조와 제조방법의 각 공정을 예시한 단면도.3 is a cross-sectional view illustrating each step of the structure and manufacturing method of the semiconductor substrate bump of the present invention.
제4도는 본 발명의 반도체 기판 범프의 실제 본딩 상태를 예시한 단면도.4 is a cross-sectional view illustrating the actual bonding state of the semiconductor substrate bump of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 기판 2, 12 : 패드1, 11: substrate 2, 12: pad
3, 13 : 보호막 4,14 : 확산방지층3, 13: protective film 4, 14: diffusion barrier layer
5, 15 : 범프 6, 17 : 도전성 볼5, 15 bump 6, 17 conductive ball
7, 18 : 접착물질 8, 20 : 액정기판7, 18: adhesive material 8, 20: liquid crystal substrate
9, 19 : (액정기판의)패드 16 : 절연막9, 19: pad (of liquid crystal substrate) 16: insulating film
21 : 포토레지스트 패턴21: photoresist pattern
본 발명은 반도체 범프(Bump)의 본딩 구조 및 방법에 관한 것으로, 범프를 이용한 본딩시 발생되던 전기적 단락 문제를 해결하기에 적합하도록 한 반도체 범프의 본딩 구조 및 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bonding structures and methods of semiconductor bumps, and more particularly to bonding structures and methods of semiconductor bumps that are suitable for solving the electrical short-circuit problem that occurs during bonding using bumps.
범프를 이용한 본딩방법은 주로 반도체 디바이스 패키지나, 액정표시소자(Liquid Crystal Display : LCD)의 구동 소자(IC) 실장시에 많이 쓰이는 기술로서, 본 명세서에는 주로 액정표시소자의 구동소자 실장을 예로 들어 설명하겠다.The bonding method using bumps is a technology mainly used for mounting a semiconductor device package or a driving device (IC) of a liquid crystal display (LCD). In this specification, a driving device mounting of a liquid crystal display device is mainly used. I'll explain.
액정표시소자의 구동회로는 보통 별도의 회로 소자들을 액정표시소자의 박막 트랜지스터 어레이 기판에 연결하여 사용하는데, 이러한 구동소자 실장 기술에는 구동소자를 프린트기판(PCB : Printed Circuit Board)에 실장한 후 박막 트랜지스터 어레이 기판과 프린트기판을 연결하는 방법과, 플렉시블 테이프(flexible tape)에 구동소자를 실장한 후 박막 트랜지스터 어레이 기판과 플렉시블 테이프를 연결하는 방법과, 박막 트랜지스터 기판위에 구동소자를 직접실장하는 방법(COG : Chip On Glass)등이 있다.The driving circuit of the liquid crystal display device is usually connected to the thin film transistor array substrate of the liquid crystal display device using a separate circuit element, the driving device mounting technology is a thin film after mounting the driving device on a printed circuit board (PCB) A method of connecting a transistor array substrate and a printed circuit board, a method of connecting a thin film transistor array substrate and a flexible tape after mounting a driving element on a flexible tape, and a method of directly mounting a driving element on a thin film transistor substrate ( COG: Chip On Glass).
범프를 이용한 본딩방법은 직접실장방법에서 주로 쓰이는 본딩방법으로, 범프가 형성된 소자와 외부기판의 단자를 이방성 도전 필름(Anisotropic Conductive Film : 이하 ACF라 한다.)이나 이방성 도전 접착제(Anisotropic Conductive Adhesive : 이하 ACA라 한다.)와 같은 접착물질을 이용하여 본딩하는 것이다. 이러한 ACF나 ACA는 내부에 구경이 5 내지 7㎛정도의 도전볼이 분포되어 있어서 도전성을 가지고 있다. 즉, 범프가 형성된 소자를 외부 기판에 실장할 때, 기판의 소자 실장 부위에 ACF나 ACA를 부착 내지 도포한 후, 범프가 형성된 소자를 압착시키면, ACF나 ACA에 내포된 도전볼을 통하여 소자와 기판이 서로 전기적으로 연결된다.The bonding method using bumps is a bonding method mainly used in a direct mounting method, and the terminals of bump formed elements and external substrates are referred to as anisotropic conductive film (ACF) or anisotropic conductive adhesive (hereinafter referred to as an ACF). Bonding using an adhesive material such as ACA. Such ACF and ACA have conductivity because the conductive balls having a diameter of about 5 to 7 μm are distributed therein. That is, when mounting a device with bumps on an external substrate, if ACF or ACA is attached or applied to the device mounting portion of the substrate, and then the device with bumps is pressed, the device and the conductive ball contained in the ACF or ACA are pressed. The substrates are electrically connected to each other.
그런데, 반도체 소자의 크기가 점차 소형화되어감에 따라 소자에 형성된 범프들의 간격이 점점 가까워져서, 이웃하는 두 범프가 ACF나 ACA에 내포된 도전불에 의해 서로 전기적으로 연결되어, 소자가 단락되는 문제점을 가지고 있었다.However, as the size of the semiconductor device is gradually miniaturized, the bumps formed in the device become closer to each other, so that two neighboring bumps are electrically connected to each other by a conductive light embedded in the ACF or ACA, thereby shorting the device. Had
제1도는 종래의 일반적인 범프의 구조를 나타내는 도면으로, 종래의 반도체 기판 범프는 구동소자가 형성된 기판(1)상에 형성된 패드(2)와, 패드(2)의 일부와 노출된 반도체 기판(1)위에 보호막(3)이 있다. 노출된 패드(2)와 패드위에 올라온 보호막(3)위에 확산방지층(4)이 형성되어 있으며, 확산방지층(4)의 상부에는 범프(5)가 형성되어 있는 구조를 가지고 있다.FIG. 1 is a view showing a structure of a conventional general bump. The conventional semiconductor substrate bump includes a pad 2 formed on a substrate 1 on which a driving element is formed, a portion of the pad 2 and an exposed semiconductor substrate 1. There is a protective film 3 above. The diffusion barrier layer 4 is formed on the exposed pad 2 and the protective film 3 on the pad, and the bump 5 is formed on the diffusion barrier layer 4.
제2도는 이러한 종래의 문제점을 설명하기 위해 예시한 것으로, 구동소자가 형성된 반도체 기판(1)을 박막 트랜지스터 기판(8)에 본딩할 때, 이웃하는 두 범프(5)가 접착물질(7)내의 도전볼(6)에 의하여 서로 전기적으로 연결되는 상태를 도시하고 있다.2 illustrates the conventional problem. When bonding the semiconductor substrate 1 on which the driving element is formed to the thin film transistor substrate 8, two neighboring bumps 5 are formed in the adhesive material 7. The state which is electrically connected with each other by the conductive ball 6 is shown.
이는 본딩시, 박막 트랜지스터 기판(8)에 ACF나 ACA등의 접착물질(7)을 접착 또는 도포한 후, 범프(5)가 형성된 반도체 기판(1)을 가압 가열하여 물리적으로 박막 트랜지스터 기판(8)에 본딩하는데, 이때, 범프(5)의 압력 또는 열에 의해 접착물질(7)이 범프사이 공간으로 흘러 도전볼이 밀집되기 때문이다.When bonding, the adhesive material 7 such as ACF or ACA is adhered to or applied to the thin film transistor substrate 8, and then the semiconductor substrate 1 having the bumps 5 formed thereon is pressed and heated to physically thin film transistor substrate 8. In this case, the adhesive material 7 flows into the spaces between the bumps by the pressure or heat of the bumps 5, so that the conductive balls are concentrated.
실제적으로 외부기판 단자와 전기적 접촉이 이루어지는 부위는 범프(5)의 상면인데, 그 측면까지 표면이 노출되어 있어서, 범프간 거리가 가까울 경우, 범프 사이 공간에 밀집된 접착물질에 포함된 도전볼이 이웃하는 두 범프를 서로 전기적으로 연결시켜 단락이 발생된다.In fact, the electrical contact with the external board terminal is the upper surface of the bump (5), the surface is exposed to the side, when the distance between the bumps, if the distance between the bumps, the conductive ball contained in the adhesive material dense in the space between the bumps The two bumps are electrically connected to each other to generate a short circuit.
본 발명은 이를 해결하기 위하여 안출된 것으로, 반도체기판 위에 형성된 제1패드와, 상기 제1패드 위에 형성된 범프와, 상기 범프의 측면과 상부표면의 적어도 일부분에 형성된 절연막과, 상기 범프상측 표면에 분포하는 도전입자와, 상기 도전입자를 통해 상기 범프와 전기적으로 접속되는 제2패드로 구성됨을 특징으로 하는 반도체 범프의 본딩 구조이다.The present invention has been made to solve this problem, the first pad formed on the semiconductor substrate, the bump formed on the first pad, the insulating film formed on at least a portion of the side and the upper surface of the bump, and distributed on the bump upper surface And a second pad electrically connected to the bump through the conductive particles.
또한, 본 발명은 번도체 기판 상에 범프를 형성하는 단계와, 상기 범프의 측면과 상부표면의 적어도 일부분에 절연막을 형성하는 단계와, 이방성 도전필름을 이용하여 상기 범프를 외부패드와 전기적으로 접속하는 단계를 포함하는 것을 특징으로 하는 반도체 범프의 본딩방법이다.In addition, the present invention comprises the steps of forming a bump on the conductive substrate, forming an insulating film on at least a portion of the side and the upper surface of the bump, and electrically connecting the bump to the external pad using an anisotropic conductive film Bonding method of a semiconductor bump comprising the step of.
이하, 본 발명을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
제3b도 및 3d도는 본 발명의 반도체 기판 범프의 실시예들로서, 먼저, 제3d도와 같이, 구동소자가 형성된 반도체 기판(11)상에 형성된 패드(12)와, 패드(12)의 일부와 패드(12)가 형성되지 않는 반도체 기판(11)위에 형성된 보호막(13)이 있고, 패드(12)상부의 보호막(13)과 보호막(13)으로부터 노출된 패드(12)위에 확산방지층(14)이 형성되어 있고, 확산방지층(14)의 상부에는 범프(15)가 있으며, 범프 상면의 접촉영역(A)를 제외한 범프(15) 상면의 일부, 측면, 노출된 확산방지층(14)의 측면 및 보호막(13)위에 절연막(16)이 있다. 이때, 절연막(16)이 범프(15)상면의 가장영역에는 남아 있어서, 울타리 형상을 가진다.3B and 3D illustrate embodiments of the semiconductor substrate bump of the present invention. First, as illustrated in FIG. 3D, the pad 12, a part of the pad 12, and the pad 12 are formed on the semiconductor substrate 11 on which the driving element is formed. There is a protective film 13 formed on the semiconductor substrate 11 on which the 12 is not formed, and the diffusion barrier layer 14 is disposed on the protective film 13 on the pad 12 and the pad 12 exposed from the protective film 13. The bump 15 is formed on the upper portion of the diffusion barrier layer 14, and a part, a side surface of the upper surface of the bump 15 except for the contact area A on the upper surface of the bump, and the side surface and the protective layer of the exposed diffusion barrier layer 14. On the (13) is an insulating film 16. At this time, the insulating film 16 remains in the distal region of the upper surface of the bump 15, and has a fence shape.
또한, 제3b도와 같이, 범프(15)측면 뿐아니라 상면에도 절연막(16)이 형성된 구조를 가질 수 있다.In addition, as shown in FIG. 3B, the insulating layer 16 may be formed on the upper surface of the bump 15 as well as on the upper surface thereof.
제3도는 본 발명의 반도체 범프 제조방법의 실시예로서, 먼저, 제3a도와 같이, 구동소자가 형성된 반도체 기판(11)상에 알루미늄으로 패드(12)를 형성한후, 패드(12) 및 반도체 기판(11)전면에 실리콘 산화막 또는 실리콘 질화막을 이용하여 보호막(13)을 형성하고, 사진식각하여 패드(12)를 노출시킨다. 이 때, 패드(12)의 가장자리에는 보호막(13)을 남긴다. 이어서, 노출된 패드(12) 및 보호막(13) 표면에 타이타늄(Ti), 팔라듐(Pd), 금(Au)을 차례로 적층한다. 이어서, Ti.Pd.Au 위에 패드 상부가 노출된 포토레지스트 패턴을 형성한다. 그리고, 포토레지스트 패턴을 이용하여 전기도금방법으로 금(Au)으로 범프(15)를 형성한 후, 포토레지스트 패턴을 제거한다. 이 때, 범프의 높이는 약 15㎛정도이다. 이어서, 확산방지층(14)를 사진식각하여 범프하부에만 확산방지층(14)를 남긴후, 열처리 공정을 수행한다.FIG. 3 is an embodiment of the method for manufacturing a semiconductor bump of the present invention. First, as shown in FIG. 3A, the pad 12 and the semiconductor are formed on the semiconductor substrate 11 on which the driving element is formed. The protective film 13 is formed on the entire surface of the substrate 11 using a silicon oxide film or a silicon nitride film, and the pad 12 is exposed by photolithography. At this time, the protective film 13 is left at the edge of the pad 12. Subsequently, titanium (Ti), palladium (Pd), and gold (Au) are sequentially stacked on the exposed pad 12 and the protective film 13 surface. Subsequently, a photoresist pattern on which the pad top is exposed is formed on Ti.Pd.Au. After the bumps 15 are formed of gold (Au) by the electroplating method using the photoresist pattern, the photoresist pattern is removed. At this time, the bump height is about 15 µm. Subsequently, the diffusion barrier layer 14 is photo-etched to leave the diffusion barrier layer 14 only at the bottom of the bump, and then a heat treatment process is performed.
다음으로, 제3b도와 같이, 범프(15)와 노출된 확산방지층(14) 및 보호막(13)표면에 폴리머(polymer) 또는 실리콘 질화막을 화학기상증착(CVD) 또는 물리기상증착 또는 코팅방법으로 절연막(16)을 형성한다.Next, as shown in FIG. 3B, the polymer or silicon nitride film is deposited on the surface of the bump 15 and the exposed diffusion barrier layer 14 and the protective film 13 by chemical vapor deposition (CVD) or physical vapor deposition or coating. (16) is formed.
다음으로, 제3c도와 같이, 절연막(16)위에 포토레지스트를 도포한 후, 범프(15)상면의 접촉영역(A)를 정의하는 포토레지스트 패턴(21)을 형성한다.Next, as shown in FIG. 3C, after the photoresist is applied on the insulating film 16, the photoresist pattern 21 defining the contact area A on the upper surface of the bump 15 is formed.
다음으로, 제3d도와 같이, 포토레지스트 패턴(21)을 마스크로 절연막(16)을 식각하여 범프(15) 상면의 접촉영역(A)을 노출시킨 후, 포토레지스트 패턴을 제거함으로써, 반도체 기판 범프를 제조한다.Next, as shown in FIG. 3D, the insulating layer 16 is etched using the photoresist pattern 21 as a mask to expose the contact region A on the upper surface of the bump 15, and then the photoresist pattern is removed to thereby bump the semiconductor substrate. To prepare.
또한, 제3b도의 범프(15) 상면과 측면에 절연막(16)을 형성하는 공정까지만을 진행하여 반도체 기판 범프를 제조할 수도 있다.Further, the semiconductor substrate bump may be manufactured by only proceeding to forming the insulating film 16 on the top and side surfaces of the bump 15 in FIG. 3B.
제4a도 및 4b도는 본 발명의 반도체 기판 범프를 이용하여 액정표시장치의 박막 트랜지스터 어레이 기판(20)에 구동소자가 형성된 반도체 기판(11)를 실장한 모습을 도시한 것이다.4A and 4B illustrate a state in which a semiconductor substrate 11 having a driving element is mounted on a thin film transistor array substrate 20 of a liquid crystal display using the semiconductor substrate bumps of the present invention.
제4a도는 제3d도에 도시된 반도체 기판 범프의 경우이고, 제4b도는 제3b도에 도시된 반도체 기판 범프의 경우를 각각 도시한 것이다.FIG. 4A is a case of the semiconductor substrate bump shown in FIG. 3D, and FIG. 4B is a case of the semiconductor substrate bump shown in FIG. 3B.
제4a도 및 4b도와 같이, 구동소자가 형성된 반도체 기판(11)의 범프(15)를 접착물질(18)이 도포 또는 접착된 액정기판(20)에 형성된 패드(19)에 맞추어 가압 가열하여 실장할 때, 접착물질(18)이 흘러 범프(15)사이에 도전볼(17)이 밀집되어 다수개의 도전볼(17)이 서로 접촉 연결되어 두 범프(15)의 측면을 접촉연결하더라도 범프 측면에 절연막(16)이 형성되어 있으므로 두 범프는 서로 전기적으로 절연상태를 유지할 수 있다.4A and 4B, the bump 15 of the semiconductor substrate 11 on which the driving element is formed is press-heated and mounted in accordance with the pad 19 formed on the liquid crystal substrate 20 to which the adhesive material 18 is applied or bonded. When the adhesive material 18 flows, the conductive balls 17 are concentrated between the bumps 15 so that a plurality of conductive balls 17 are in contact with each other so that the sides of the two bumps 15 are in contact with each other. Since the insulating film 16 is formed, the two bumps may be electrically insulated from each other.
제4b도의 경우, 실장시에 접착물질 내의 도전볼이 범프(15)의 상부에 형성된 절연막(16)내부로 침투되어, Au범프와 박막 트랜지스터 기판(20)상의 패드(19)를 서로 연결시킨다.In the case of FIG. 4B, conductive balls in the adhesive material penetrate into the insulating film 16 formed on the bumps 15 during mounting to connect the Au bumps and the pads 19 on the thin film transistor substrate 20 to each other.
한편, 위에서 설명한 바와 같이, 본 발명의 반도체 기판 범프는 본 명세서에서 주로 설명한 액정기판의 구동소자 실장시외에 반도체 칩 패키지에도 적용할 수 있다.On the other hand, as described above, the semiconductor substrate bump of the present invention can be applied to a semiconductor chip package in addition to the mounting of the driving element of the liquid crystal substrate mainly described herein.
따라서, 파인 피치(fine pitch)구조의 구동소자에의 적용시에도 전기적 단락등의 문제점을 해결할 수 있으며. 부수적으로 제4a도에서와 같이, 제3d도와 같은 구조를 취할 경우, 범프상면의 접촉 영역(A)을 정의하면서 상면 가장 영역에 절연막이 울타리 형상으로 남아 있어서, 본딩시 접착물질의 도전성 볼이 접착물질로 같이 흘러내리는 현상을 방지할 수 있어 많은 도전볼이 범프 상면에 남게 되므로, 콘택 저항을 낮출 수 있는 효과도 있다.Therefore, problems such as electrical short circuits can be solved even when applied to a drive element having a fine pitch structure. Incidentally, as shown in FIG. 4A, when the structure shown in FIG. 3D is taken, the insulating film remains in the shape of a fence on the uppermost area while defining the contact area A of the bump top surface, so that the conductive balls of the adhesive material adhere during bonding. It is possible to prevent the phenomenon of flowing down with the material, so that many conductive balls remain on the upper surface of the bump, thereby reducing the contact resistance.
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046106A KR100225398B1 (en) | 1995-12-01 | 1995-12-01 | Bonding structure of semiconductor bump and its method |
| US08/755,142 US6232563B1 (en) | 1995-11-25 | 1996-11-22 | Bump electrode and method for fabricating the same |
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|---|---|---|---|
| KR1019950046106A KR100225398B1 (en) | 1995-12-01 | 1995-12-01 | Bonding structure of semiconductor bump and its method |
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| KR970053159A KR970053159A (en) | 1997-07-29 |
| KR100225398B1 true KR100225398B1 (en) | 1999-10-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100367407B1 (en) * | 2000-03-31 | 2003-01-14 | 학교법인 한양학원 | low contact resistance chip bonding method |
| KR100455387B1 (en) * | 2002-05-17 | 2004-11-06 | 삼성전자주식회사 | Method for forming a bump on semiconductor chip and COG package including the bump |
| US6958539B2 (en) | 2000-08-29 | 2005-10-25 | Au Optronics Corporation | Metal bump with an insulating sidewall and method of fabricating thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429530B1 (en) * | 1998-11-02 | 2002-08-06 | International Business Machines Corporation | Miniaturized chip scale ball grid array semiconductor package |
| KR100306116B1 (en) * | 1998-12-31 | 2001-11-30 | 구자홍 | Direct attach bonding method of semiconductor bare chip |
| JP2001044358A (en) | 1999-07-28 | 2001-02-16 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| KR100367808B1 (en) * | 2000-08-18 | 2003-01-10 | 씨티에스 컴퓨터 테크놀로지 시스템 코포레이션 | Semiconductor Device and Contact-Forming Method Therefor |
| KR100559937B1 (en) * | 2003-01-08 | 2006-03-13 | 엘에스전선 주식회사 | Method of microelectrode connection and connected srtucture thereby |
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1995
- 1995-12-01 KR KR1019950046106A patent/KR100225398B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100367407B1 (en) * | 2000-03-31 | 2003-01-14 | 학교법인 한양학원 | low contact resistance chip bonding method |
| US6958539B2 (en) | 2000-08-29 | 2005-10-25 | Au Optronics Corporation | Metal bump with an insulating sidewall and method of fabricating thereof |
| US7041589B2 (en) * | 2000-08-29 | 2006-05-09 | Au Optronics Corp. | Metal bump with an insulating sidewall and method of fabricating thereof |
| KR100455387B1 (en) * | 2002-05-17 | 2004-11-06 | 삼성전자주식회사 | Method for forming a bump on semiconductor chip and COG package including the bump |
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| KR970053159A (en) | 1997-07-29 |
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