JP5608520B2 - Method for manufacturing transistor - Google Patents
Method for manufacturing transistor Download PDFInfo
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- JP5608520B2 JP5608520B2 JP2010255538A JP2010255538A JP5608520B2 JP 5608520 B2 JP5608520 B2 JP 5608520B2 JP 2010255538 A JP2010255538 A JP 2010255538A JP 2010255538 A JP2010255538 A JP 2010255538A JP 5608520 B2 JP5608520 B2 JP 5608520B2
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- 238000000034 method Methods 0.000 title claims description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 177
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 72
- 239000010936 titanium Substances 0.000 claims description 46
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 38
- 229910052719 titanium Inorganic materials 0.000 claims description 38
- 239000013078 crystal Substances 0.000 claims description 27
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 24
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 22
- 229910052733 gallium Inorganic materials 0.000 claims description 22
- 229910052738 indium Inorganic materials 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000011701 zinc Substances 0.000 claims description 18
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- 229910052725 zinc Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000012298 atmosphere Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 239000013081 microcrystal Substances 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 317
- 229910052751 metal Inorganic materials 0.000 description 94
- 239000002184 metal Substances 0.000 description 93
- 229910052760 oxygen Inorganic materials 0.000 description 45
- 239000001301 oxygen Substances 0.000 description 45
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 44
- 239000010409 thin film Substances 0.000 description 40
- 229910044991 metal oxide Inorganic materials 0.000 description 31
- 150000004706 metal oxides Chemical class 0.000 description 31
- 229910007541 Zn O Inorganic materials 0.000 description 27
- 238000004364 calculation method Methods 0.000 description 25
- 239000004408 titanium dioxide Substances 0.000 description 18
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 16
- 238000004544 sputter deposition Methods 0.000 description 15
- 125000004429 atom Chemical group 0.000 description 14
- 230000007547 defect Effects 0.000 description 14
- 239000001257 hydrogen Substances 0.000 description 14
- 229910052739 hydrogen Inorganic materials 0.000 description 14
- 239000012535 impurity Substances 0.000 description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 239000007789 gas Substances 0.000 description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 10
- 229910052750 molybdenum Inorganic materials 0.000 description 10
- 206010021143 Hypoxia Diseases 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 9
- 239000011733 molybdenum Substances 0.000 description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
- 239000011651 chromium Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- KELHQGOVULCJSG-UHFFFAOYSA-N n,n-dimethyl-1-(5-methylfuran-2-yl)ethane-1,2-diamine Chemical compound CN(C)C(CN)C1=CC=C(C)O1 KELHQGOVULCJSG-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 125000004430 oxygen atom Chemical group O* 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 5
- 229960001730 nitrous oxide Drugs 0.000 description 5
- 235000013842 nitrous oxide Nutrition 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 230000007812 deficiency Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000006356 dehydrogenation reaction Methods 0.000 description 4
- 229910001882 dioxygen Inorganic materials 0.000 description 4
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 3
- 229910019092 Mg-O Inorganic materials 0.000 description 3
- 229910019395 Mg—O Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 3
- 230000018044 dehydration Effects 0.000 description 3
- 238000006297 dehydration reaction Methods 0.000 description 3
- 238000003795 desorption Methods 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 3
- 108010083687 Ion Pumps Proteins 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000002484 cyclic voltammetry Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 238000000329 molecular dynamics simulation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000004698 pseudo-potential method Methods 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000000859 sublimation Methods 0.000 description 2
- 230000008022 sublimation Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 150000002483 hydrogen compounds Chemical class 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 150000004679 hydroxides Chemical class 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- -1 silicon (Si) Chemical compound 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Electrodes Of Semiconductors (AREA)
Description
技術分野は、酸化物半導体を用いた薄膜トランジスタに関する。 The technical field relates to a thin film transistor using an oxide semiconductor.
近年、ポリシリコンにより得られる高い移動度とアモルファスシリコンにより得られる均一な素子特性とを兼ね備えた新たな半導体材料として、酸化物半導体と呼ばれる、半導体特性を示す金属酸化物が注目されている。例えば、酸化タングステン、酸化スズ、酸化インジウム、酸化亜鉛などが、半導体特性を示す金属酸化物として挙げられる。 In recent years, metal oxides that exhibit semiconductor characteristics, called oxide semiconductors, have attracted attention as a new semiconductor material that combines high mobility obtained from polysilicon and uniform element characteristics obtained from amorphous silicon. For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like can be given as metal oxides that exhibit semiconductor characteristics.
特許文献1および2では、半導体特性を示す金属酸化物をチャネル形成領域に用いた薄膜トランジスタが提案されている。 Patent Documents 1 and 2 propose a thin film transistor in which a metal oxide exhibiting semiconductor characteristics is used for a channel formation region.
電気特性が良好な、酸化物半導体を用いた薄膜トランジスタを提供することを課題とする。 It is an object to provide a thin film transistor using an oxide semiconductor with favorable electrical characteristics.
本発明の一態様は、基板上に設けられたゲート電極と、ゲート電極上に設けられたゲート絶縁膜と、ゲート電極およびゲート絶縁膜上に設けられた酸化物半導体膜と、酸化物半導体膜上に設けられた金属酸化物膜と、金属酸化物膜上に設けられた金属膜と、を有し、酸化物半導体膜は、金属酸化物膜と接し、且つ、酸化物半導体膜の他の領域よりも金属濃度が高い領域(金属高濃度領域)を有することを特徴とする薄膜トランジスタである。 One embodiment of the present invention includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and the gate insulating film, and an oxide semiconductor film. A metal oxide film provided on the metal oxide film; the oxide semiconductor film is in contact with the metal oxide film; and the other oxide semiconductor film A thin film transistor having a region (metal high concentration region) having a metal concentration higher than that of the region.
金属高濃度領域には、酸化物半導体膜に含まれる金属が、結晶粒または微結晶として存在していてもよい。 The metal contained in the oxide semiconductor film may exist as crystal grains or microcrystals in the high metal concentration region.
本発明の一態様は、基板上に設けられたゲート電極と、ゲート電極上に設けられたゲート絶縁膜と、ゲート電極およびゲート絶縁膜上に設けられ、インジウム、ガリウム、および亜鉛を含む酸化物半導体膜と、酸化物半導体膜上に設けられた酸化チタン膜と、酸化チタン膜上に設けられたチタン膜と、を有し、酸化物半導体膜は、酸化チタン膜と接し、且つ、酸化物半導体膜の他の領域よりもインジウムの濃度が高い領域を有することを特徴とする薄膜トランジスタである。 One embodiment of the present invention includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, and an oxide containing indium, gallium, and zinc provided over the gate electrode and the gate insulating film. A semiconductor film, a titanium oxide film provided over the oxide semiconductor film, and a titanium film provided over the titanium oxide film, the oxide semiconductor film being in contact with the titanium oxide film and being an oxide The thin film transistor includes a region having a higher concentration of indium than other regions of the semiconductor film.
酸化物半導体膜の他の領域よりもインジウムの濃度が高い領域には、インジウムが結晶粒または微結晶として存在していてもよい。 Indium may exist as crystal grains or microcrystals in a region where the concentration of indium is higher than that of other regions of the oxide semiconductor film.
電気特性が良好な、酸化物半導体を用いた薄膜トランジスタを提供することができる。 A thin film transistor using an oxide semiconductor with favorable electrical characteristics can be provided.
以下、発明の実施の形態について、図面を用いて説明する。ただし、発明は以下の説明に限定されず、その発明の趣旨およびその範囲から逸脱することなく、その態様および詳細をさまざまに変更し得ることは当業者であれば容易に理解される。したがって、発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.
(実施の形態1)
図1(A)は、酸化物半導体を用いた薄膜トランジスタの断面模式図である。この薄膜トランジスタは、基板10、ゲート電極20、ゲート絶縁膜30、酸化物半導体膜40、金属酸化物膜60、金属膜70、および絶縁膜80で構成されている。
(Embodiment 1)
FIG. 1A is a schematic cross-sectional view of a thin film transistor using an oxide semiconductor. The thin film transistor includes a substrate 10, a gate electrode 20, a gate insulating film 30, an oxide semiconductor film 40, a metal oxide film 60, a metal film 70, and an insulating film 80.
図1(A)に示す薄膜トランジスタは、チャネルエッチ構造のボトムゲート型である。ただし、薄膜トランジスタの構造はこれに限定されるものでなく、任意のトップゲート型やボトムゲート型などを用いることができる。 The thin film transistor illustrated in FIG. 1A is a bottom-gate type with a channel etch structure. However, the structure of the thin film transistor is not limited to this, and an arbitrary top gate type or bottom gate type can be used.
基板10には、絶縁表面を有する基板を用いる。基板10として、ガラス基板を用いるのが適切である。後の加熱処理の温度が高い場合には、ガラス基板のなかでも、歪点が730℃以上のものを用いるとよい。また、耐熱性を考えると、酸化ホウ素(B2O3)よりも、酸化バリウム(BaO)を多く含むガラス基板が好適である。 As the substrate 10, a substrate having an insulating surface is used. It is appropriate to use a glass substrate as the substrate 10. When the temperature of the subsequent heat treatment is high, a glass substrate having a strain point of 730 ° C. or higher is preferably used. In view of heat resistance, a glass substrate containing more barium oxide (BaO) than boron oxide (B 2 O 3 ) is preferable.
ガラス基板以外にも、セラミック基板、石英ガラス基板、石英基板、サファイア基板などの絶縁体からなる基板を、基板10として用いてもよい。他にも、結晶化ガラス基板などを、基板10として用いてもよい。 In addition to the glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 10. In addition, a crystallized glass substrate or the like may be used as the substrate 10.
また、下地膜となる絶縁膜を、基板10とゲート電極20との間に設けてもよい。下地膜は、基板10からの不純物元素の拡散を防止する機能を有する。なお、下地膜となる絶縁膜は、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜、および酸化窒化シリコン膜から選ばれた、一または複数の膜により形成してもよい。 Further, an insulating film serving as a base film may be provided between the substrate 10 and the gate electrode 20. The base film has a function of preventing diffusion of impurity elements from the substrate 10. Note that the insulating film serving as a base film may be formed using one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
ゲート電極20としては、金属導電膜を用いることができる。金属導電膜の材料としては、アルミニウム(Al)、クロム(Cr)、銅(Cu)、タンタル(Ta)、チタン(Ti)、モリブデン(Mo)、およびタングステン(W)から選ばれた元素、または、これらの元素を主成分とする合金などを用いることができる。例えば、金属導電膜として、チタン膜−アルミニウム膜−チタン膜の3層構造やモリブデン膜−アルミニウム膜−モリブデン膜の3層構造などを用いることができる。なお、金属導電膜は3層構造に限られず、単層、2層構造、または4層以上の積層構造としてもよい。 As the gate electrode 20, a metal conductive film can be used. As a material of the metal conductive film, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), or An alloy containing these elements as a main component can be used. For example, a three-layer structure of titanium film-aluminum film-titanium film or a three-layer structure of molybdenum film-aluminum film-molybdenum film can be used as the metal conductive film. Note that the metal conductive film is not limited to a three-layer structure, and may have a single layer structure, a two-layer structure, or a stacked structure including four or more layers.
ゲート絶縁膜30としては、酸化シリコン膜、窒化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、酸化アルミニウム膜、窒化アルミニウム膜、酸化窒化アルミニウム膜、窒化酸化アルミニウム膜、酸化ハフニウム膜などを用いることができる。 As the gate insulating film 30, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or the like is used. Can do.
酸化物半導体膜40に用いられる酸化物半導体として、五元系金属酸化物であるIn−Sn−Ga−Zn−O系酸化物半導体や、四元系金属酸化物であるIn−Ga−Zn−O系酸化物半導体、In−Sn−Zn−O系酸化物半導体、In−Al−Zn−O系酸化物半導体、Sn−Ga−Zn−O系酸化物半導体、Al−Ga−Zn−O系酸化物半導体、Sn−Al−Zn−O系酸化物半導体や、三元系金属酸化物であるIn−Zn−O系酸化物半導体、Sn−Zn−O系酸化物半導体、Al−Zn−O系酸化物半導体、Zn−Mg−O系酸化物半導体、Sn−Mg−O系酸化物半導体、In−Mg−O系酸化物半導体、In−Ga−O系酸化物半導体や、二元系金属酸化物であるIn−O系酸化物半導体、Sn−O系酸化物半導体、Zn−O系酸化物半導体などを用いることができる。なお、本明細書においては、例えば、In−Sn−Ga−Zn−O系酸化物半導体とは、インジウム(In)、錫(Sn)、ガリウム(Ga)、亜鉛(Zn)を有する金属酸化物、という意味であり、その組成比は特に問わない。また、酸化物半導体膜40は、酸化シリコン(SiO2)を含んでいてもよい。 As an oxide semiconductor used for the oxide semiconductor film 40, an In—Sn—Ga—Zn—O-based oxide semiconductor that is a quinary metal oxide, or an In—Ga—Zn— that is a quaternary metal oxide. O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based Oxide semiconductors, Sn-Al-Zn-O-based oxide semiconductors, In-Zn-O-based oxide semiconductors that are ternary metal oxides, Sn-Zn-O-based oxide semiconductors, Al-Zn-O Oxide semiconductor, Zn—Mg—O oxide semiconductor, Sn—Mg—O oxide semiconductor, In—Mg—O oxide semiconductor, In—Ga—O oxide semiconductor, binary metal In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn- Or the like can be used system oxide semiconductor. Note that in this specification, for example, an In—Sn—Ga—Zn—O-based oxide semiconductor is a metal oxide containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The composition ratio is not particularly limited. The oxide semiconductor film 40 may include silicon oxide (SiO 2 ).
また、酸化物半導体膜40には、InMO3(ZnO)m(m>0)で表記される構造を有する酸化物半導体を用いることもできる。ここで、Mは、ガリウム(Ga)、アルミニウム(Al)、マンガン(Mn)、およびコバルト(Co)から選ばれた、一または複数の金属元素を示す。Mに該当する例として、ガリウム単体、ガリウムおよびアルミニウム、ガリウムおよびマンガン、ガリウムおよびコバルトなどが挙げられる。 For the oxide semiconductor film 40, an oxide semiconductor having a structure represented by InMO 3 (ZnO) m (m> 0) can be used. Here, M represents one or more metal elements selected from gallium (Ga), aluminum (Al), manganese (Mn), and cobalt (Co). Examples corresponding to M include gallium alone, gallium and aluminum, gallium and manganese, gallium and cobalt, and the like.
なお、InMO3(ZnO)m(m>0)で表記される構造を有する酸化物半導体のうち、Mとしてガリウム(Ga)を含む構造の酸化物半導体を、In−Ga−Zn−O系酸化物半導体とも記す。 Note that among oxide semiconductors having a structure represented by InMO 3 (ZnO) m (m> 0), an oxide semiconductor including gallium (Ga) as M is an In—Ga—Zn—O-based oxide. Also referred to as a physical semiconductor.
酸化物半導体膜40は、ドナーの原因である水素、水分、水酸基、水酸化物(水素化合物ともいう)などの不純物を意図的に排除したのち、これらの不純物の排除工程において減少してしまう酸素を供給することで、高純度化および電気的にi型(真性)化されている。これは、薄膜トランジスタの電気的特性の変動を抑制するためである。 The oxide semiconductor film 40 intentionally excludes impurities such as hydrogen, moisture, hydroxyl groups, and hydroxides (also referred to as hydrogen compounds), which are causes of donors, and then decreases oxygen in the exclusion process of these impurities. By supplying this, it is highly purified and electrically i-type (intrinsic). This is to suppress fluctuations in the electrical characteristics of the thin film transistor.
酸化物半導体膜40中の水素が少ないほど、酸化物半導体膜40はi型に近づく。したがって、酸化物半導体膜40に含まれる水素の濃度は、5×1019/cm3以下、好ましくは5×1018/cm3以下、より好ましくは5×1017/cm3以下、さらに好ましくは5×1016/cm3未満とするとよい。当該水素の濃度は、二次イオン質量分析法(SIMS;Secondary Ion Mass Spectrometry)により測定できる。 The smaller the hydrogen in the oxide semiconductor film 40 is, the closer the oxide semiconductor film 40 is to i-type. Therefore, the concentration of hydrogen contained in the oxide semiconductor film 40 is 5 × 10 19 / cm 3 or less, preferably 5 × 10 18 / cm 3 or less, more preferably 5 × 10 17 / cm 3 or less, and still more preferably It may be less than 5 × 10 16 / cm 3 . The concentration of the hydrogen can be measured by secondary ion mass spectrometry (SIMS; Secondary Ion Mass Spectrometry).
酸化物半導体膜40に含まれる水素を極力除去することで、酸化物半導体膜40中のキャリア密度は、5×1014/cm3未満、好ましくは5×1012/cm3以下、より好ましくは5×1010/cm3以下となる。酸化物半導体膜40のキャリア密度は、酸化物半導体膜40を用いたMOSキャパシタを作製し、当該MOSキャパシタのC−V測定の結果(C−V特性)を評価することで求めることができる。 By removing hydrogen contained in the oxide semiconductor film 40 as much as possible, the carrier density in the oxide semiconductor film 40 is less than 5 × 10 14 / cm 3 , preferably 5 × 10 12 / cm 3 or less, more preferably 5 × 10 10 / cm 3 or less. The carrier density of the oxide semiconductor film 40 can be obtained by fabricating a MOS capacitor using the oxide semiconductor film 40 and evaluating the CV measurement result (CV characteristics) of the MOS capacitor.
また、酸化物半導体は、ワイドギャップ半導体である。例えば、シリコンのバンドギャップは1.12eVであるのに対して、In−Ga−Zn−O系酸化物半導体のバンドギャップは3.15eVである。 The oxide semiconductor is a wide gap semiconductor. For example, the band gap of silicon is 1.12 eV, whereas the band gap of an In—Ga—Zn—O-based oxide semiconductor is 3.15 eV.
ワイドギャップ半導体である酸化物半導体は、少数キャリア密度が低く、また、少数キャリアが誘起されにくい。そのため、酸化物半導体膜40を用いた薄膜トランジスタにおいては、トンネル電流が発生しにくく、ひいては、オフ電流が流れにくいといえる。したがって、酸化物半導体膜40を用いた薄膜トランジスタのチャネル幅1μmあたりのオフ電流として、100aA/μm以下、好ましくは10aA/μm以下、より好ましくは1aA/μm以下を実現できる。 An oxide semiconductor that is a wide gap semiconductor has a low minority carrier density and is less likely to induce minority carriers. Therefore, in the thin film transistor using the oxide semiconductor film 40, it can be said that a tunnel current hardly occurs and an off current hardly flows. Therefore, an off current per channel width of 1 μm of the thin film transistor using the oxide semiconductor film 40 can be 100 aA / μm or less, preferably 10 aA / μm or less, more preferably 1 aA / μm or less.
また、酸化物半導体は、ワイドギャップ半導体であるため、酸化物半導体膜40を用いた薄膜トランジスタにおいては、衝突イオン化およびアバランシェ降伏が起きにくい。したがって、酸化物半導体膜40を用いた薄膜トランジスタは、ホットキャリア劣化への耐性があるといえる。ホットキャリア劣化は、主に、アバランシェ降伏によってキャリアが増大し、高速に加速されたキャリアがゲート絶縁膜へ注入されることにより生じるからである。 In addition, since the oxide semiconductor is a wide gap semiconductor, impact ionization and avalanche breakdown hardly occur in the thin film transistor using the oxide semiconductor film 40. Therefore, it can be said that the thin film transistor using the oxide semiconductor film 40 has resistance to hot carrier deterioration. This is because hot carrier deterioration is mainly caused by carriers increasing due to avalanche breakdown, and carriers accelerated at high speed are injected into the gate insulating film.
金属膜70は、ソース電極またはドレイン電極として用いられる。金属膜70としては、アルミニウム(Al)、クロム(Cr)、銅(Cu)、タンタル(Ta)、チタン(Ti)、モリブデン(Mo)、タングステン(W)などの金属材料、または、これらの金属材料を主成分とする合金材料を用いることができる。また、金属膜70は、アルミニウム(Al)や銅(Cu)などを用いた金属膜の一方の表面または双方の表面に、クロム(Cr)、タンタル(Ta)、チタン(Ti)、モリブデン(Mo)、タングステン(W)などを用いた高融点金属膜を積層させた構成としてもよい。なお、シリコン(Si)、チタン(Ti)、タンタル(Ta)、タングステン(W)、モリブデン(Mo)、クロム(Cr)、ネオジム(Nd)、スカンジウム(Sc)、イットリウム(Y)などの、アルミニウム膜に生ずるヒロックやウィスカーの発生を防止する元素が添加されているアルミニウムを材料として用いることで、耐熱性にすぐれた金属膜70を得ることができる。 The metal film 70 is used as a source electrode or a drain electrode. As the metal film 70, a metal material such as aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), or these metals An alloy material containing the material as a main component can be used. The metal film 70 is formed of chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo) on one surface or both surfaces of a metal film using aluminum (Al), copper (Cu), or the like. ), Refractory metal films using tungsten (W) or the like may be stacked. Aluminum such as silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), yttrium (Y), etc. By using aluminum to which an element for preventing generation of hillocks and whiskers generated in the film is used as a material, the metal film 70 having excellent heat resistance can be obtained.
金属酸化物膜60として、金属膜70に含まれる金属の酸化物を含む膜を用いることができる。例えば、金属膜70がチタンを含む膜である場合、金属酸化物膜60として酸化チタン膜などを用いることができる。 As the metal oxide film 60, a film containing a metal oxide contained in the metal film 70 can be used. For example, when the metal film 70 is a film containing titanium, a titanium oxide film or the like can be used as the metal oxide film 60.
また、酸化物半導体膜40は、金属酸化物膜60と接し、且つ、酸化物半導体膜40の他の領域よりも金属濃度が高い領域を有する。当該金属濃度が高い領域を、金属高濃度領域50とも記す。 The oxide semiconductor film 40 has a region in contact with the metal oxide film 60 and having a metal concentration higher than that of the other regions of the oxide semiconductor film 40. The region where the metal concentration is high is also referred to as a metal high concentration region 50.
図1(B)は、図1(A)における領域100を拡大した断面模式図である。 FIG. 1B is a schematic cross-sectional view in which the region 100 in FIG.
図1(B)に示すように、金属高濃度領域50には、酸化物半導体膜40に含まれる金属が、結晶粒または微結晶として存在していてもよい。 As shown in FIG. 1B, the metal contained in the oxide semiconductor film 40 may exist as crystal grains or microcrystals in the metal high concentration region 50.
図2は、図1に示す構成の薄膜トランジスタにおける、ソース電極−ドレイン電極間のエネルギーバンド図(模式図)である。この図は、ソース電極−ドレイン電極間の電位差がゼロである場合を想定している。 FIG. 2 is an energy band diagram (schematic diagram) between a source electrode and a drain electrode in the thin film transistor having the configuration shown in FIG. This figure assumes a case where the potential difference between the source electrode and the drain electrode is zero.
ここでは、金属高濃度領域50を金属として扱っている。また、不純物を極力除去し、酸素を供給することにより、酸化物半導体膜40は高純度化および電気的にi型(真性)化されている。その結果、エネルギーバンド図において、酸化物半導体膜40の膜内部でフェルミ準位(Ef)はバンドギャップの中央付近にある。 Here, the metal high concentration region 50 is treated as a metal. The oxide semiconductor film 40 is highly purified and electrically i-type (intrinsic) by removing impurities as much as possible and supplying oxygen. As a result, in the energy band diagram, the Fermi level (Ef) is in the vicinity of the center of the band gap inside the oxide semiconductor film 40.
このエネルギーバンド図より、酸化物半導体膜40において、金属高濃度領域50と他の領域との界面には障壁が存在しておらず、良好なコンタクトが得られていることがわかる。金属高濃度領域50と金属酸化物膜60との界面、および、金属酸化物膜60と金属膜70との界面においても、同様である。 From this energy band diagram, it can be seen that in the oxide semiconductor film 40, there is no barrier at the interface between the high-concentration metal region 50 and another region, and a good contact is obtained. The same applies to the interface between the metal high concentration region 50 and the metal oxide film 60 and the interface between the metal oxide film 60 and the metal film 70.
(実施の形態2)
図1に示す構成の薄膜トランジスタの作製工程について説明する。
(Embodiment 2)
A manufacturing process of the thin film transistor having the structure illustrated in FIGS.
まず、絶縁表面を有する基板10上に導電膜を形成した後、第1のフォトリソグラフィ工程によりゲート電極20を形成する。 First, after a conductive film is formed over the substrate 10 having an insulating surface, the gate electrode 20 is formed by a first photolithography process.
第1のフォトリソグラフィ工程に用いるレジストマスクは、インクジェット法で形成してもよい。レジストマスクをインクジェット法で形成すると、フォトマスクを使用しないため、製造コストを低減できる。 The resist mask used for the first photolithography process may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.
次いで、ゲート電極20上にゲート絶縁膜30を形成する。 Next, a gate insulating film 30 is formed on the gate electrode 20.
ゲート絶縁膜30は、プラズマCVD法やスパッタリング法などの方法により成膜する。ゲート絶縁膜30としては、酸化シリコン、窒化シリコン、酸化窒化シリコン、窒化酸化シリコン、酸化アルミニウム、窒化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、酸化ハフニウムなどを用いた膜が好適である。 The gate insulating film 30 is formed by a method such as a plasma CVD method or a sputtering method. As the gate insulating film 30, a film using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or the like is preferable.
酸化物半導体膜40と接するゲート絶縁膜30は、緻密で絶縁耐圧が高い膜であることが望まれる。そのため、特に、μ波(2.45GHz)を用いた高密度プラズマCVD法により成膜した、緻密で絶縁耐圧が高い膜をゲート絶縁膜30として用いることが適している。 The gate insulating film 30 in contact with the oxide semiconductor film 40 is desirably a dense film with high withstand voltage. Therefore, it is particularly suitable to use as the gate insulating film 30 a dense film having a high withstand voltage that is formed by a high-density plasma CVD method using μ waves (2.45 GHz).
このようにして得られた緻密で絶縁耐圧が高い膜であるゲート絶縁膜30と、不純物を極力除去し、酸素を供給してi型化された酸化物半導体膜40との界面特性は良好となる。 Interfacial characteristics between the gate insulating film 30 which is a dense film having a high withstand voltage obtained in this way and the oxide semiconductor film 40 which is made i-type by removing impurities as much as possible and supplying oxygen are good. Become.
仮に、酸化物半導体膜40とゲート絶縁膜30との界面特性が不良であるとすると、ゲートバイアス・熱ストレス試験(BT試験:85℃、2×106V/cm、12時間)において、不純物と酸化物半導体の主成分との結合が切断され、生成された未結合手により、しきい値電圧のシフトが誘発される結果となる。 If the interface characteristics between the oxide semiconductor film 40 and the gate insulating film 30 are poor, impurities in the gate bias / thermal stress test (BT test: 85 ° C., 2 × 10 6 V / cm, 12 hours) As a result, the bond between the main component of the oxide semiconductor and the main component of the oxide semiconductor is broken, and a shift of the threshold voltage is induced by the generated dangling bonds.
ゲート絶縁膜30は、窒化物絶縁膜と酸化物絶縁膜との積層構造としてもよい。例えば、第1のゲート絶縁膜としてスパッタリング法により膜厚50nm以上200nm以下の窒化シリコン膜(SiNy(y>0))を形成した後、第1のゲート絶縁膜上に第2のゲート絶縁膜として膜厚5nm以上300nm以下の酸化シリコン膜(SiOx(x>0))を形成することによって、積層構造を有するゲート絶縁膜30とすることができる。ゲート絶縁膜30の膜厚は、薄膜トランジスタに要求される特性によって適宜設定すればよく、350nm以上400nm程度以下としてもよい。 The gate insulating film 30 may have a stacked structure of a nitride insulating film and an oxide insulating film. For example, after a silicon nitride film (SiN y (y> 0)) having a thickness of 50 nm to 200 nm is formed as the first gate insulating film by a sputtering method, the second gate insulating film is formed on the first gate insulating film. As a gate insulating film 30 having a stacked structure can be formed by forming a silicon oxide film (SiO x (x> 0)) with a thickness of 5 nm to 300 nm. The thickness of the gate insulating film 30 may be set as appropriate depending on characteristics required for the thin film transistor, and may be about 350 nm to 400 nm.
好ましくは、ゲート絶縁膜30成膜の前処理として、スパッタリング装置の予備加熱室において、ゲート電極20が形成された基板10を予備加熱することによって、基板10に吸着した水素や水分などの不純物を、脱離および排気するとよい。これは、その後形成されるゲート絶縁膜30および酸化物半導体膜40に、水素や水分などの不純物が極力含まれないようにするためである。また、ゲート絶縁膜30を基板10上に形成した時点で基板10を予備加熱してもよい。 Preferably, as a pretreatment for forming the gate insulating film 30, impurities such as hydrogen and moisture adsorbed on the substrate 10 are preliminarily heated in the preheating chamber of the sputtering apparatus by preheating the substrate 10 on which the gate electrode 20 is formed. Desorption and evacuation are good. This is to prevent impurities such as hydrogen and moisture from being contained as much as possible in the gate insulating film 30 and the oxide semiconductor film 40 formed thereafter. Alternatively, the substrate 10 may be preheated when the gate insulating film 30 is formed on the substrate 10.
予備加熱の温度としては、100℃以上400℃以下が適切である。150℃以上300℃以下であれば、さらに好適である。また、予備加熱室における排気手段は、クライオポンプが適切である。 The preheating temperature is suitably 100 ° C. or higher and 400 ° C. or lower. If it is 150 degreeC or more and 300 degrees C or less, it is still more suitable. In addition, a cryopump is appropriate as the exhaust means in the preheating chamber.
次いで、ゲート絶縁膜30上に、酸化物半導体膜40を形成する。酸化物半導体膜40は、膜厚2nm以上200nm以下が適切である。 Next, the oxide semiconductor film 40 is formed over the gate insulating film 30. An appropriate thickness of the oxide semiconductor film 40 is 2 nm to 200 nm.
酸化物半導体膜40は、スパッタリング法により成膜する。スパッタリング法による成膜は、希ガス(代表的にはアルゴン)雰囲気下、酸素雰囲気下、または希ガスおよび酸素の混合雰囲気下において行う。 The oxide semiconductor film 40 is formed by a sputtering method. Film formation by a sputtering method is performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen.
スパッタリング法による酸化物半導体膜40の成膜に用いるターゲットとして、酸化亜鉛を主成分とする金属酸化物を用いることができる。また、組成比がそれぞれ、In2O3:Ga2O3:ZnO=1:1:1[mol%]、または、In:Ga:Zn=1:1:0.5[atom%]、In:Ga:Zn=1:1:1[atom%]、若しくは、In:Ga:Zn=1:1:2[atom%]である、インジウム(In)、ガリウム(Ga)、および亜鉛(Zn)を含む酸化物半導体成膜用ターゲットを用いることもできる。また、当該酸化物半導体成膜用ターゲットの充填率は、90%以上100%以下が適切である。95%以上99.9%以下であれば、さらに好適である。充填率の高い酸化物半導体成膜用ターゲットを用いると、より緻密な酸化物半導体膜を成膜できるためである。 As a target used for forming the oxide semiconductor film 40 by a sputtering method, a metal oxide containing zinc oxide as a main component can be used. The composition ratios of In 2 O 3 : Ga 2 O 3 : ZnO = 1: 1: 1 [mol%] or In: Ga: Zn = 1: 1: 0.5 [atom%], In : Ga: Zn = 1: 1: 1 [atom%] or In: Ga: Zn = 1: 1: 2 [atom%], indium (In), gallium (Ga), and zinc (Zn) An oxide semiconductor target for film formation containing can also be used. In addition, the filling rate of the oxide semiconductor deposition target is appropriately 90% to 100%. If it is 95% or more and 99.9% or less, it is more preferable. This is because a denser oxide semiconductor film can be formed when an oxide semiconductor deposition target with a high filling rate is used.
酸化物半導体膜40成膜前に、減圧状態の処理室内に基板10を保持し、基板10を室温以上400℃未満の温度に加熱する。その後、処理室内の残留水分を除去しつつ、水素および水分が除去されたスパッタガスを導入しながら、基板10とターゲットとの間に電圧を印加することによって、基板10上に酸化物半導体膜40を成膜する。 Before the oxide semiconductor film 40 is formed, the substrate 10 is held in a processing chamber in a reduced pressure state, and the substrate 10 is heated to a temperature of room temperature to less than 400 ° C. Thereafter, a voltage is applied between the substrate 10 and the target while removing residual moisture in the processing chamber and introducing a sputtering gas from which hydrogen and moisture have been removed, whereby the oxide semiconductor film 40 is formed on the substrate 10. Is deposited.
処理室内の残留水分を除去する排気手段として、吸着型の真空ポンプを用いることが適切である。例として、クライオポンプ、イオンポンプ、チタンサブリメーションポンプなどが挙げられる。また、排気手段として、ターボポンプにコールドトラップを加えたものを用いることもできる。処理室内より、水素原子、水素分子、水(H2O)などの水素原子を含む化合物、などを(より好ましくは、炭素原子を含む化合物とともに)排気することにより、当該処理室において成膜した酸化物半導体膜40に含まれる不純物の濃度を低減できる。また、クライオポンプにより処理室内の残留水分を除去しつつスパッタリング法により成膜を行うことにより、酸化物半導体膜40を成膜する際の基板10の温度を、室温以上400℃未満とすることができる。 It is appropriate to use an adsorption-type vacuum pump as an exhausting means for removing residual moisture in the processing chamber. Examples include a cryopump, an ion pump, and a titanium sublimation pump. Moreover, what added the cold trap to the turbo pump can also be used as an exhaust means. A film containing a hydrogen atom, a hydrogen molecule, a compound containing a hydrogen atom such as water (H 2 O), or the like (preferably together with a compound containing a carbon atom) is exhausted from the treatment chamber to form a film in the treatment chamber. The concentration of impurities contained in the oxide semiconductor film 40 can be reduced. In addition, the temperature of the substrate 10 when the oxide semiconductor film 40 is formed is set to be room temperature or higher and lower than 400 ° C. by performing film formation by a sputtering method while removing residual moisture in the treatment chamber with a cryopump. it can.
なお、酸化物半導体膜40をスパッタリング法により成膜する前に、逆スパッタによって、ゲート絶縁膜30の表面に付着しているゴミを除去するとよい。逆スパッタとは、ターゲット側に電圧を印加せずに、基板側にRF電源を用いて電圧を印加することにより生じる反応性プラズマによって、基板表面を洗浄する方法である。なお、逆スパッタは、アルゴン雰囲気中で行う。また、アルゴンにかえて、窒素、ヘリウム、酸素などを用いてもよい。 Note that dust attached to the surface of the gate insulating film 30 is preferably removed by reverse sputtering before the oxide semiconductor film 40 is formed by a sputtering method. Reverse sputtering is a method of cleaning the substrate surface with reactive plasma generated by applying a voltage to the substrate side using an RF power source without applying a voltage to the target side. Note that reverse sputtering is performed in an argon atmosphere. Further, nitrogen, helium, oxygen, or the like may be used instead of argon.
酸化物半導体膜40成膜後、酸化物半導体膜40の脱水化または脱水素化を行う。脱水化または脱水素化のための加熱処理の温度は、400℃以上750℃以下が適切であり、特に425℃以上であることが好適である。なお、加熱処理時間は、当該加熱処理の温度が425℃以上であれば1時間以下でよいが、425℃未満であれば1時間よりも長くすることが好ましい。本明細書では、この加熱処理によって水素分子(H2)を脱離させることのみを脱水素化と呼んでいるわけではなく、水素原子(H)や水酸基(OH)などを脱離することを含めて脱水化または脱水素化と便宜上呼ぶこととする。 After the oxide semiconductor film 40 is formed, the oxide semiconductor film 40 is dehydrated or dehydrogenated. The temperature of the heat treatment for dehydration or dehydrogenation is suitably 400 ° C. or higher and 750 ° C. or lower, and particularly preferably 425 ° C. or higher. Note that the heat treatment time may be 1 hour or less if the temperature of the heat treatment is 425 ° C. or higher, but is preferably longer than 1 hour if the temperature is less than 425 ° C. In this specification, the desorption of hydrogen molecules (H 2 ) by this heat treatment is not only called dehydrogenation, but desorption of hydrogen atoms (H), hydroxyl groups (OH), and the like. Including the dehydration or dehydrogenation for convenience.
例えば、加熱処理装置の一つである電気炉に、酸化物半導体膜40が形成された基板10を導入し、窒素雰囲気下において加熱処理を行う。その後、同じ炉に高純度の酸素ガス、高純度の一酸化二窒素(N2O)ガス、または超乾燥エアー(露点が−40℃以下、好ましくは−60℃以下で、窒素と酸素が4対1の割合で混合された気体)を導入して冷却を行う。酸素ガスまたは一酸化二窒素(N2O)ガスには、水や水素などが含まれないことが好ましい。また、酸素ガスまたは一酸化二窒素(N2O)ガスの純度を、6N(99.9999%)以上、好ましくは7N(99.99999%)以上(すなわち酸素ガスまたは一酸化二窒素(N2O)ガス中の不純物濃度を1ppm以下、好ましくは0.1ppm以下)とすることが適切である。 For example, the substrate 10 over which the oxide semiconductor film 40 is formed is introduced into an electric furnace which is one of heat treatment apparatuses, and heat treatment is performed in a nitrogen atmosphere. Thereafter, high purity oxygen gas, high purity dinitrogen monoxide (N 2 O) gas, or ultra-dry air (with a dew point of −40 ° C. or lower, preferably −60 ° C. or lower, nitrogen and oxygen of 4 in the same furnace) Cooling is performed by introducing a gas mixed at a ratio of 1: 2. The oxygen gas or dinitrogen monoxide (N 2 O) gas preferably does not contain water or hydrogen. The purity of oxygen gas or dinitrogen monoxide (N 2 O) gas is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, oxygen gas or dinitrogen monoxide (N 2 )). O) It is appropriate that the impurity concentration in the gas is 1 ppm or less, preferably 0.1 ppm or less.
なお、加熱処理装置は電気炉に限られず、例えば、GRTA(Gas Rapid Thermal Anneal)装置やLRTA(Lamp Rapid Thermal Anneal)装置などのRTA(Rapid Thermal Anneal)装置を用いることができる。 Note that the heat treatment apparatus is not limited to an electric furnace, and for example, an RTA (Rapid Thermal Annial) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used.
また、酸化物半導体膜40の脱水化または脱水素化のための加熱処理は、第2のフォトリソグラフィ工程により酸化物半導体膜40を島状に加工する前後を問わず、酸化物半導体膜40に対して行うことができる。 Further, the heat treatment for dehydration or dehydrogenation of the oxide semiconductor film 40 is performed on the oxide semiconductor film 40 before or after the oxide semiconductor film 40 is processed into an island shape by the second photolithography process. Can be done against.
以上の工程を経て、酸化物半導体膜40全体を酸素過剰な状態とすることによって、酸化物半導体膜40全体を高抵抗化、すなわちi型化させる。 Through the above steps, the entire oxide semiconductor film 40 is brought into an oxygen-excess state, whereby the entire oxide semiconductor film 40 is increased in resistance, that is, i-type.
次いで、ゲート絶縁膜30および酸化物半導体膜40上に、金属膜70を形成する。金属膜70は、スパッタリング法や真空蒸着法などで成膜すればよい。また、金属膜70は、単層構造であってもよいし、2層以上の積層構造であってもよい。 Next, a metal film 70 is formed over the gate insulating film 30 and the oxide semiconductor film 40. The metal film 70 may be formed by a sputtering method, a vacuum evaporation method, or the like. Further, the metal film 70 may have a single layer structure or a laminated structure of two or more layers.
その後、第3のフォトリソグラフィ工程により、金属膜70上にレジストマスクを形成し、選択的にエッチングを行ってソース電極およびドレイン電極を形成した後、レジストマスクを除去する。 Thereafter, a resist mask is formed over the metal film 70 by a third photolithography process, and selective etching is performed to form a source electrode and a drain electrode, and then the resist mask is removed.
薄膜トランジスタのチャネル長は、酸化物半導体膜40上で隣り合うソース電極の下端部とドレイン電極の下端部との間隔によって決定される。すなわち、第3のフォトリソグラフィ工程におけるレジストマスク形成時の露光の条件によって、薄膜トランジスタのチャネル長が決定されるといえる。第3のフォトリソグラフィ工程におけるレジストマスク形成時の露光には、紫外線、KrFレーザ光、またはArFレーザ光を用いることができる。また、チャネル長を25nm未満とする場合には、数nm以上数10nm以下の極めて波長が短い超紫外線(Extreme Ultraviolet)を用いて露光すればよい。超紫外線による露光は、解像度が高く焦点深度も大きいためである。したがって、薄膜トランジスタのチャネル長は、露光に用いる光の種類によって、10nm以上1000nm以下とすることが可能である。 The channel length of the thin film transistor is determined by the distance between the lower end of the source electrode adjacent to the lower end of the drain electrode on the oxide semiconductor film 40. That is, it can be said that the channel length of the thin film transistor is determined by the exposure condition when forming the resist mask in the third photolithography process. Ultraviolet, KrF laser light, or ArF laser light can be used for light exposure for forming the resist mask in the third photolithography process. In addition, when the channel length is less than 25 nm, exposure may be performed using extreme ultraviolet (Extreme Ultraviolet) with a very short wavelength of several nm to several tens of nm. This is because the exposure with extreme ultraviolet rays has a high resolution and a large depth of focus. Therefore, the channel length of the thin film transistor can be 10 nm to 1000 nm depending on the type of light used for exposure.
なお、金属膜70をエッチングする際に、酸化物半導体膜40を除去しないようにするため、金属膜70の材料および酸化物半導体膜40の材料、ならびに、エッチング条件を適宜調節する必要がある。 Note that the material of the metal film 70, the material of the oxide semiconductor film 40, and the etching conditions need to be adjusted as appropriate so that the oxide semiconductor film 40 is not removed when the metal film 70 is etched.
一例として、金属膜70としてチタン膜を用い、かつ、酸化物半導体膜40としてIn−Ga−Zn−O系酸化物半導体膜を用いた場合には、エッチング溶液としてアンモニア過水(アンモニア、水、および過酸化水素水の混合液)を用いるとよい。 As an example, in the case where a titanium film is used as the metal film 70 and an In—Ga—Zn—O-based oxide semiconductor film is used as the oxide semiconductor film 40, ammonia overwater (ammonia, water, And a mixed solution of hydrogen peroxide water).
なお、第3のフォトリソグラフィ工程において、酸化物半導体膜40の一部のみがエッチングされることによって、溝部(凹部)を有する酸化物半導体膜40としてもよい。また、ソース電極およびドレイン電極を形成するためのレジストマスクは、インクジェット法で形成してもよい。レジストマスクをインクジェット法で形成すると、フォトマスクを使用しないため、製造コストを低減できる。 Note that in the third photolithography process, only part of the oxide semiconductor film 40 may be etched, whereby the oxide semiconductor film 40 having a groove (a depressed portion) may be formed. Further, the resist mask for forming the source electrode and the drain electrode may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.
ソース電極およびドレイン電極を形成後、一酸化二窒素(N2O)、窒素(N2)、またはアルゴン(Ar)などのガスを用いたプラズマ処理によって、露出している酸化物半導体膜40の表面に付着した水(吸着水)などを除去してもよい。当該プラズマ処理には、酸素およびアルゴンの混合ガスを用いることもできる。 After forming the source electrode and the drain electrode, the exposed oxide semiconductor film 40 is exposed by plasma treatment using a gas such as dinitrogen monoxide (N 2 O), nitrogen (N 2 ), or argon (Ar). You may remove the water (adsorbed water) etc. which adhered to the surface. In the plasma treatment, a mixed gas of oxygen and argon can be used.
プラズマ処理を行った場合は、そのまま大気に触れることなく、酸化物半導体膜40の一部と接する、絶縁膜80を形成する。図1に示す薄膜トランジスタでは、酸化物半導体膜40と、金属膜70とが重ならない領域において、酸化物半導体膜40と絶縁膜80とが接する。 In the case where plasma treatment is performed, the insulating film 80 that is in contact with part of the oxide semiconductor film 40 is formed without being exposed to the air as it is. In the thin film transistor illustrated in FIG. 1, the oxide semiconductor film 40 and the insulating film 80 are in contact with each other in a region where the oxide semiconductor film 40 and the metal film 70 do not overlap.
絶縁膜80の一例として、酸化物半導体膜40および金属膜70が形成された基板10を、室温以上100℃未満の温度で加熱した後、水素および水分が除去された高純度酸素を含むスパッタガスを導入しシリコンターゲットを用いて成膜した、欠陥を含む酸化シリコン膜が挙げられる。 As an example of the insulating film 80, the substrate 10 on which the oxide semiconductor film 40 and the metal film 70 are formed is heated at a temperature of room temperature to less than 100 ° C., and then a sputtering gas containing high-purity oxygen from which hydrogen and moisture are removed. And a silicon oxide film containing defects formed using a silicon target.
絶縁膜80は、処理室内の残留水分を除去しつつ成膜することが好ましい。酸化物半導体膜40および絶縁膜80に水素、水酸基、および水分が含まれないようにするためである。 The insulating film 80 is preferably formed while removing residual moisture in the processing chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film 40 and the insulating film 80.
処理室内の残留水分を除去する排気手段として、吸着型の真空ポンプを用いることが適切である。例として、クライオポンプ、イオンポンプ、チタンサブリメーションポンプなどが挙げられる。また、排気手段として、ターボポンプにコールドトラップを加えたものを用いることもできる。処理室内より、水素原子、水素分子、水(H2O)などの水素原子を含む化合物、などを排気することにより、当該処理室において成膜した絶縁膜80に含まれる不純物の濃度を低減できる。 It is appropriate to use an adsorption-type vacuum pump as an exhausting means for removing residual moisture in the processing chamber. Examples include a cryopump, an ion pump, and a titanium sublimation pump. Moreover, what added the cold trap to the turbo pump can also be used as an exhaust means. By exhausting hydrogen atoms, hydrogen molecules, compounds containing hydrogen atoms such as water (H 2 O), and the like from the treatment chamber, the concentration of impurities contained in the insulating film 80 formed in the treatment chamber can be reduced. .
なお、絶縁膜80としては、酸化シリコン膜の他に、酸化窒化シリコン膜、酸化アルミニウム膜、酸化窒化アルミニウム膜などを用いることもできる。 Note that as the insulating film 80, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used in addition to the silicon oxide film.
絶縁膜80の成膜後に、不活性ガス雰囲気下または窒素ガス雰囲気下において、100℃以上400℃以下、好ましくは150℃以上350℃未満の加熱処理を行う。加熱処理を行うと、酸化物半導体膜40中に含まれる水素、水分、水酸基、水素化物などの不純物が、欠陥を含む絶縁膜80中に拡散する。その結果、酸化物半導体膜40中に含まれる不純物を、より低減させることができる。 After the insulating film 80 is formed, heat treatment is performed at 100 ° C. to 400 ° C., preferably 150 ° C. to less than 350 ° C. in an inert gas atmosphere or a nitrogen gas atmosphere. When heat treatment is performed, impurities such as hydrogen, moisture, a hydroxyl group, and hydride contained in the oxide semiconductor film 40 diffuse into the insulating film 80 including defects. As a result, impurities contained in the oxide semiconductor film 40 can be further reduced.
また、当該加熱処理によって、酸化物半導体膜40と金属膜70との界面に金属酸化物膜60が形成され、酸化物半導体膜40内の金属酸化物膜60と接する領域に金属高濃度領域50が形成される。 Further, by the heat treatment, a metal oxide film 60 is formed at the interface between the oxide semiconductor film 40 and the metal film 70, and the metal high-concentration region 50 is formed in a region in contact with the metal oxide film 60 in the oxide semiconductor film 40. Is formed.
なお、金属酸化物膜60は、金属膜70の形成前に、スパッタリング法などを用いて酸化物半導体膜40上に形成してもよい。この場合、酸化物半導体膜40と、金属膜70とが重ならない領域に設けられた金属酸化物膜60を除去することで、図1の薄膜トランジスタが得られる。 Note that the metal oxide film 60 may be formed over the oxide semiconductor film 40 by a sputtering method or the like before the metal film 70 is formed. In this case, the thin film transistor of FIG. 1 can be obtained by removing the metal oxide film 60 provided in a region where the oxide semiconductor film 40 and the metal film 70 do not overlap.
また、上記加熱処理は、絶縁膜80の成膜前に行ってもよい。 The heat treatment may be performed before the insulating film 80 is formed.
以上の工程により、図1に示す構成の薄膜トランジスタを形成することができる。 Through the above steps, the thin film transistor having the structure illustrated in FIG. 1 can be formed.
(実施の形態3)
図1に示す構成の薄膜トランジスタの、酸化物半導体膜40と金属膜70との界面に金属酸化物膜60が形成され、酸化物半導体膜40内の金属酸化物膜60と接する領域に金属高濃度領域50が形成される現象について、計算科学により検証した結果を示す。
(Embodiment 3)
In the thin film transistor having the structure shown in FIG. 1, a metal oxide film 60 is formed at the interface between the oxide semiconductor film 40 and the metal film 70, and a high metal concentration is present in a region in contact with the metal oxide film 60 in the oxide semiconductor film 40. The result of having verified by the computational science about the phenomenon in which the area | region 50 is formed is shown.
以下の計算において、酸化物半導体膜40が、In−Ga−Zn−O系酸化物半導体膜である場合を考えた。また、金属膜70は、タングステン(W)膜、モリブデン(Mo)膜、またはチタン(Ti)膜である場合を考えた。 In the following calculation, the case where the oxide semiconductor film 40 is an In—Ga—Zn—O-based oxide semiconductor film was considered. The metal film 70 is considered to be a tungsten (W) film, a molybdenum (Mo) film, or a titanium (Ti) film.
[金属高濃度領域50が形成される現象について]
In−Ga−Zn−O系酸化物半導体を構成しているインジウム、ガリウム、亜鉛それぞれの酸化物が、酸素欠損状態を形成するために必要なエネルギー(欠損形成エネルギーEdef)を計算した。
[Phenomenon in which metal high concentration region 50 is formed]
The energy (defect formation energy E def ) required for each of the oxides of indium, gallium, and zinc constituting the In—Ga—Zn—O-based oxide semiconductor to form an oxygen-deficient state was calculated.
欠損形成エネルギーEdefは、次の数式(1)で定義される。 The defect formation energy E def is defined by the following formula (1).
なお、E(AmOn−1)は酸素欠損のある酸化物AmOn−1のエネルギー、E(O)は酸素原子のエネルギー、E(AmOn)は酸素欠損のない酸化物AmOnのエネルギーを表す。また、Aは、インジウム単独、ガリウム単独、亜鉛単独、またはインジウムとガリウムと亜鉛を示す。 Note that E (A m O n-1 ) is the energy of the oxide A m O n-1 having oxygen vacancies, E (O) is the energy of oxygen atoms, and E (A m O n ) is the oxidation without oxygen vacancies. It represents the energy of the object a m O n. A represents indium alone, gallium alone, zinc alone, or indium, gallium and zinc.
また、酸素の欠損濃度nと、欠損形成エネルギーEdefとの関係は、近似的に次の数式(2)で表される。 Further, the relationship between the oxygen deficiency concentration n and the deficiency formation energy E def is approximately expressed by the following equation (2).
なお、Nは欠損が形成されていない状態における酸素の数、kBはボルツマン定数、Tは絶対温度を表す。 N represents the number of oxygen in a state where no defect is formed, k B represents a Boltzmann constant, and T represents an absolute temperature.
数式(2)より、欠損形成エネルギーEdefが大きくなると、酸素の欠損濃度n、すなわち酸素の欠損量は小さくなることが分かった。 From the mathematical formula (2), it is found that as the deficiency formation energy E def increases, the oxygen deficiency concentration n, that is, the amount of oxygen deficiency decreases.
欠損形成エネルギーEdefの計算には、密度汎関数法のプログラムであるCASTEPを用いた。密度汎関数法として平面波基底擬ポテンシャル法を用い、汎関数はGGA−PBEを用いた。カットオフエネルギーは、500eVとした。k点のグリッド数は、インジウムとガリウムと亜鉛を含む酸化物(以下、「IGZO」とも記す。)については3×3×1、インジウムの酸化物(以下、「In2O3」とも記す。)については2×2×2、ガリウムの酸化物(以下、「Ga2O3」とも記す。)については2×3×2、亜鉛の酸化物(以下、「ZnO」とも記す。)については4×4×1とした。 CASTEP, which is a program of the density functional method, was used for the calculation of the defect formation energy E def . A plane wave basis pseudopotential method was used as the density functional method, and GGA-PBE was used as the functional. The cut-off energy was 500 eV. The number of grids at point k is 3 × 3 × 1 for an oxide containing indium, gallium, and zinc (hereinafter also referred to as “IGZO”), and is also referred to as an oxide of indium (hereinafter referred to as “In 2 O 3 ”). ) Is 2 × 2 × 2, gallium oxide (hereinafter also referred to as “Ga 2 O 3 ”) is 2 × 3 × 2, and zinc oxide (hereinafter also referred to as “ZnO”). 4 × 4 × 1.
結晶構造は、IGZOについては対称性R−3(国際番号:148)の構造をa軸、b軸にそれぞれ2倍することによって得られた84原子の構造に対して、Ga、Znをエネルギーが最小になるように配置した構造を用いた。In2O3については80原子のbixbyite構造を、Ga2O3については80原子のβ−Gallia構造を、ZnOについては80原子のウルツ構造を用いた。 The crystal structure of Ga and Zn is higher than that of 84 atoms obtained by doubling the structure of symmetry R-3 (international number: 148) for the IGZO to the a-axis and b-axis, respectively. A structure arranged so as to be minimized was used. For In 2 O 3 , an 80 atom bixbyte structure was used, for Ga 2 O 3 , an 80 atom β-Gallia structure, and for ZnO, an 80 atom Wurtz structure was used.
表1に、数式(1)において、Aがそれぞれ、インジウム単独、ガリウム単独、亜鉛単独、インジウムとガリウムと亜鉛の場合の、欠損形成エネルギーEdefを示す。また、図3に、In−Ga−Zn―O系酸化物半導体中における、金属と酸素の結晶構造を示す。 Table 1 shows the defect formation energy E def when A is indium alone, gallium alone, zinc alone, indium, gallium, and zinc in Formula (1), respectively. FIG. 3 shows a crystal structure of metal and oxygen in the In—Ga—Zn—O-based oxide semiconductor.
IGZO(Model1)の欠損形成エネルギーEdefは、Aがインジウムとガリウムと亜鉛の場合に、IGZO結晶中において、3つのインジウム原子と1つの亜鉛原子に隣接する酸素(図3(A)参照)の欠損形成エネルギーに相当する。 The deficiency formation energy E def of IGZO (Model 1) is obtained when oxygen is adjacent to three indium atoms and one zinc atom in the IGZO crystal when A is indium, gallium, and zinc (see FIG. 3A). It corresponds to the defect formation energy.
IGZO(Model2)の欠損形成エネルギーEdefは、Aがインジウムとガリウムと亜鉛の場合に、IGZO結晶中において、3つのインジウム原子と1つのガリウム原子に隣接する酸素(図3(B)参照)の欠損形成エネルギーに相当する。 The defect formation energy E def of IGZO (Model 2) is the amount of oxygen adjacent to three indium atoms and one gallium atom in the IGZO crystal when A is indium, gallium, and zinc (see FIG. 3B). It corresponds to the defect formation energy.
IGZO(Model3)の欠損形成エネルギーEdefは、Aがインジウムとガリウムと亜鉛の場合に、IGZO結晶中において、2つの亜鉛原子と2つのガリウム原子に隣接する酸素(図3(C)参照)の欠損形成エネルギーに相当する。 The deficiency formation energy E def of IGZO (Model 3) is obtained when oxygen is adjacent to two zinc atoms and two gallium atoms in the IGZO crystal when A is indium, gallium, and zinc (see FIG. 3C). It corresponds to the defect formation energy.
欠損形成エネルギーEdefが大きいほど、酸素欠損状態を形成するために高いエネルギーが必要である。つまり、欠損形成エネルギーEdefが大きいほど、酸素と金属との結合が強い傾向にあることを意味する。換言すれば、表1より、欠損形成エネルギーEdefが最も小さいインジウムが、最も酸素との結合が弱いといえた。 The higher the defect formation energy E def , the higher the energy required to form the oxygen deficiency state. That is, the larger the defect formation energy E def, the stronger the bond between oxygen and metal. In other words, from Table 1, it can be said that indium having the smallest defect formation energy E def has the weakest bond with oxygen.
In−Ga−Zn−O系酸化物半導体における酸素欠損状態は、ソース電極またはドレイン電極として用いられた金属膜70が、酸化物半導体膜40から酸素を引き抜くために起こった。こうして酸素欠損状態となった酸化物半導体膜40の一部が、金属高濃度領域50となった。この金属高濃度領域50の有無により、酸化物半導体膜40のキャリア密度は少なくとも2桁異なる。酸化物半導体膜40から酸素が引き抜かれることによって、酸化物半導体膜40がn型化したためである。なお、n型化とは、多数キャリアである電子が増加することを意味する。 The oxygen deficiency state in the In—Ga—Zn—O-based oxide semiconductor occurred because the metal film 70 used as the source electrode or the drain electrode extracted oxygen from the oxide semiconductor film 40. A part of the oxide semiconductor film 40 in the oxygen deficient state thus becomes the metal high concentration region 50. Depending on the presence or absence of the metal high concentration region 50, the carrier density of the oxide semiconductor film 40 differs by at least two orders of magnitude. This is because oxygen is extracted from the oxide semiconductor film 40 so that the oxide semiconductor film 40 is n-type. The n-type means that the number of electrons that are majority carriers increases.
[金属酸化物膜60が形成される現象について]
In−Ga−Zn−O系酸化物半導体を用いた酸化物半導体膜40と金属膜70との積層構造に対して、量子分子動力学(QMD)計算を行った。金属による酸化物半導体からの酸素の引き抜きについて確認するためである。
[Phenomenon in which metal oxide film 60 is formed]
Quantum molecular dynamics (QMD) calculation was performed on the stacked structure of the oxide semiconductor film 40 using the In—Ga—Zn—O-based oxide semiconductor and the metal film 70. This is for confirming extraction of oxygen from the oxide semiconductor by a metal.
計算する構造は以下のように作製した。まず、古典分子動力学(CMD)法により作製したアモルファス構造のIn−Ga−Zn−O系酸化物半導体(以下、「a−IGZO」とも記す。)に対してQMD法により構造最適化を行った。さらに、構造最適化した単位格子を切断することで得られたa−IGZO膜上に、金属原子(W、Mo、Ti)の結晶を有する金属膜を積層した。そして、作製した構造に対して、構造最適化を行った。この構造を出発点として、623.0Kで、QMD法を用いて計算を行った。なお、界面の相互作用だけを見積もるために、a−IGZO膜の下端と金属膜の上端は固定した。 The structure to be calculated was prepared as follows. First, structural optimization is performed on an amorphous In—Ga—Zn—O-based oxide semiconductor (hereinafter also referred to as “a-IGZO”) manufactured by a classical molecular dynamics (CMD) method by a QMD method. It was. Furthermore, a metal film having a crystal of metal atoms (W, Mo, Ti) was stacked on the a-IGZO film obtained by cutting the unit cell whose structure was optimized. And the structure optimization was performed with respect to the produced structure. Using this structure as a starting point, calculations were performed at 623.0 K using the QMD method. In order to estimate only the interface interaction, the lower end of the a-IGZO film and the upper end of the metal film were fixed.
CMD計算の計算条件を以下に示す。計算プログラムには、Materials Explorerを用いた。a−IGZOは、次の条件で作製した。一辺1nmの計算セルに、In:Ga:Zn:O=1:1:1:4の比率で全84原子をランダムに配置し、密度を5.9g/cm3に設定した。CMD計算は、NVTアンサンブルで行い、温度を5500Kから1Kに徐々に下げた後、1Kで10nsの構造緩和を行った。時間刻み幅は0.1fsで、総計算時間は10nsとした。ポテンシャルは、金属−酸素間および酸素−酸素間にはBorn−Mayer−Huggins型を適用し、金属−金属間にはLennard−Jones型を適用した。電荷は、In:+3、Ga:+3、Zn:+2、O:−2とした。 The calculation conditions for CMD calculation are shown below. For the calculation program, Materials Explorer was used. a-IGZO was produced under the following conditions. In a calculation cell having a side of 1 nm, all 84 atoms were randomly arranged at a ratio of In: Ga: Zn: O = 1: 1: 1: 4, and the density was set to 5.9 g / cm 3 . The CMD calculation was performed with an NVT ensemble. After the temperature was gradually lowered from 5500K to 1K, the structure was relaxed for 10 ns at 1K. The time increment was 0.1 fs and the total calculation time was 10 ns. For the potential, the Born-Mayer-Huggins type was applied between the metal and oxygen and between the oxygen and oxygen, and the Lennard-Jones type was applied between the metal and metal. The charges were In: +3, Ga: +3, Zn: +2, and O: -2.
QMD計算の計算条件を以下に示す。計算プログラムには、第一原理計算ソフトCASTEPを用いた。汎関数はGGA−PBEを用いた。擬ポテンシャルはUltrasoftを用いた。カットオフエネルギーは260eV、k点の数は1×1×1とした。QMD計算は、NVTアンサンブルで行い、温度は623Kとした。時間刻み幅は1.0fsで、総計算時間は2.0psとした。 The calculation conditions for QMD calculation are shown below. First-principles calculation software CASTEP was used as the calculation program. The functional was GGA-PBE. For the pseudopotential, Ultrasoft was used. The cut-off energy was 260 eV, and the number of k points was 1 × 1 × 1. QMD calculation was performed with an NVT ensemble, and the temperature was 623K. The time increment was 1.0 fs and the total calculation time was 2.0 ps.
図4〜図6の構造モデルを用いて、上記計算の結果を説明する。図4〜図6において、白丸はa−IGZO膜上に積層した金属膜に含まれる結晶金属原子を表し、黒丸は酸素原子を表している。 The results of the above calculation will be described using the structural models shown in FIGS. 4 to 6, white circles represent crystal metal atoms contained in the metal film stacked on the a-IGZO film, and black circles represent oxygen atoms.
図4は、a−IGZO膜上にタングステン(W)の結晶を有する金属膜を積層した場合の構造モデルを示している。図4(A)はQMD計算を行う前の構造、図4(B)はQMD計算を行った後の構造に相当する。 FIG. 4 shows a structural model in the case where a metal film having a tungsten (W) crystal is stacked on the a-IGZO film. 4A corresponds to the structure before the QMD calculation, and FIG. 4B corresponds to the structure after the QMD calculation.
図5は、a−IGZO膜上にモリブデン(Mo)の結晶を有する金属膜を積層した場合の構造モデルを示している。図5(A)はQMD計算を行う前の構造、図5(B)はQMD計算を行った後の構造に相当する。 FIG. 5 shows a structural model in the case where a metal film having a molybdenum (Mo) crystal is stacked over an a-IGZO film. 5A corresponds to the structure before the QMD calculation, and FIG. 5B corresponds to the structure after the QMD calculation.
図6は、a−IGZO膜上にチタン(Ti)の結晶を有する金属膜を積層した場合の構造モデルを示している。図6(A)はQMD計算を行う前の構造、図6(B)はQMD計算を行った後の構造に相当する。 FIG. 6 shows a structural model when a metal film having a titanium (Ti) crystal is stacked on an a-IGZO film. 6A corresponds to the structure before the QMD calculation, and FIG. 6B corresponds to the structure after the QMD calculation.
図5(A)および図6(A)より、a−IGZO膜上にモリブデンまたはチタンの結晶を有する金属膜を積層した場合には、構造最適化前にすでに金属膜に酸素原子が移動していることがわかった。また、図4(B)、図5(B)、および図6(B)を比較すると、a−IGZO膜上にチタンの結晶を有する金属膜を積層した場合に、酸素原子が金属膜に最も多く移動していることがわかった。よって、金属としてチタンを用いた場合に、金属による酸化物半導体からの酸素の引き抜きが最も起こりやすかった。これより、a−IGZO膜に酸素欠損をもたらす電極として最適なものは、チタンの結晶を有する金属膜であった。 5A and 6A, when a metal film having molybdenum or titanium crystals is stacked on the a-IGZO film, oxygen atoms have already moved to the metal film before the structure optimization. I found out. 4B, FIG. 5B, and FIG. 6B, when a metal film having a titanium crystal is stacked on the a-IGZO film, oxygen atoms are the most in the metal film. I found that it was moving a lot. Therefore, when titanium is used as a metal, oxygen is most likely to be extracted from the oxide semiconductor by the metal. Thus, the most suitable electrode for causing oxygen deficiency in the a-IGZO film was a metal film having titanium crystals.
[酸化物半導体膜40中のキャリア密度について]
金属膜70中に含まれる金属による酸化物半導体膜40からの酸素の引き抜きについて、実際に素子を作製し、評価した。具体的には、酸素を引き抜く効果を有する金属膜を酸化物半導体膜に積層した場合と、酸素を引き抜く効果を有しない金属膜を酸化物半導体膜に積層した場合の、酸化物半導体膜40中のキャリア密度を計算し、結果を比較した。
[Carrier density in oxide semiconductor film 40]
Regarding the extraction of oxygen from the oxide semiconductor film 40 by the metal contained in the metal film 70, an element was actually fabricated and evaluated. Specifically, in the oxide semiconductor film 40 when a metal film having an effect of extracting oxygen is stacked on the oxide semiconductor film, and when a metal film having no effect of extracting oxygen is stacked on the oxide semiconductor film. The carrier density was calculated and the results were compared.
酸化物半導体膜中のキャリア密度は、酸化物半導体膜を用いたMOSキャパシタを作製し、当該MOSキャパシタのC−V測定の結果(C−V特性)を評価することで求めることが可能である。 The carrier density in the oxide semiconductor film can be obtained by fabricating a MOS capacitor using the oxide semiconductor film and evaluating the CV measurement result (CV characteristics) of the MOS capacitor. .
キャリア密度の測定は、次の(1)〜(3)の手順で行った。(1)MOSキャパシタのゲート電圧(Vg)と容量(C)との関係をプロットしたC−V特性を取得する。(2)当該C−V特性から、ゲート電圧(Vg)と(1/C)2との関係を表すグラフを取得し、当該グラフにおいて弱反転領域での(1/C)2の微分値を求める。(3)得られた微分値を、キャリア密度(Nd)を表す以下の数式(3)に代入する。 The carrier density was measured by the following procedures (1) to (3). (1) A CV characteristic in which the relationship between the gate voltage (Vg) and the capacitance (C) of the MOS capacitor is plotted is acquired. (2) A graph representing the relationship between the gate voltage (Vg) and (1 / C) 2 is acquired from the CV characteristics, and the differential value of (1 / C) 2 in the weak inversion region in the graph is obtained. Ask. (3) The obtained differential value is substituted into the following formula (3) representing the carrier density (Nd).
なお、eは電気素量、ε0は真空の誘電率、εは酸化物半導体の比誘電率を表す。 Note that e represents the amount of electricity, ε 0 represents the dielectric constant of vacuum, and ε represents the relative dielectric constant of the oxide semiconductor.
測定に係る試料として、酸素を引き抜く効果を有する金属膜を用いたMOSキャパシタ(以下、「試料1」とも記す。)と、酸素を引き抜く効果を有しない金属膜を用いたMOSキャパシタ(以下、「試料2」とも記す。)とを用意した。なお、酸素を引き抜く効果を有する金属膜として、チタン膜を適用した。また、酸素を引き抜く効果を有しない金属膜として、チタン膜とその表面(酸化物半導体膜側)に窒化チタン膜を有する膜を適用した。 As a sample for measurement, a MOS capacitor using a metal film having an effect of extracting oxygen (hereinafter also referred to as “sample 1”) and a MOS capacitor using a metal film having no effect of extracting oxygen (hereinafter referred to as “sample”). Also referred to as “Sample 2”). Note that a titanium film was applied as a metal film having an effect of extracting oxygen. In addition, as a metal film having no effect of extracting oxygen, a titanium film and a film having a titanium nitride film on the surface (oxide semiconductor film side) were applied.
試料の詳細は、次の通りである。
試料1:
ガラス基板上に400nmの厚さのチタン膜を有し、チタン膜上にアモルファス構造のIn−Ga−Zn−O系酸化物半導体(a−IGZO)を用いた2μmの厚さの酸化物半導体膜を有し、酸化物半導体膜上に300nmの厚さの酸化窒化シリコン膜を有し、酸化窒化シリコン膜上に300nmの銀膜を有する。
試料2:
ガラス基板上に300nmの厚さのチタン膜を有し、チタン膜上に100nmの厚さの窒化チタン膜を有し、窒化チタン膜上にアモルファス構造のIn−Ga−Zn−O系酸化物半導体(a−IGZO)を用いた2μmの厚さの酸化物半導体膜を有し、酸化物半導体膜上に300nmの厚さの酸化窒化シリコン膜を有し、酸化窒化シリコン膜上に300nmの銀膜を有する。
The details of the sample are as follows.
Sample 1:
An oxide semiconductor film having a thickness of 2 μm using a titanium film having a thickness of 400 nm on a glass substrate and using an In—Ga—Zn—O-based oxide semiconductor (a-IGZO) having an amorphous structure on the titanium film. A silicon oxynitride film with a thickness of 300 nm is formed over the oxide semiconductor film, and a silver film with a thickness of 300 nm is formed over the silicon oxynitride film.
Sample 2:
An In—Ga—Zn—O-based oxide semiconductor having a 300 nm thick titanium film over a glass substrate, a 100 nm thick titanium nitride film over the titanium film, and an amorphous structure over the titanium nitride film A 2 μm-thick oxide semiconductor film using (a-IGZO), a 300 nm-thick silicon oxynitride film on the oxide semiconductor film, and a 300-nm silver film on the silicon oxynitride film Have
なお、試料1および試料2において、酸化物半導体膜は、インジウム(In)、ガリウム(Ga)、および亜鉛(Zn)を含む酸化物半導体成膜用ターゲット(In:Ga:Zn=1:1:0.5[atom%])を用いたスパッタリング法により形成した。また、酸化物半導体膜の形成雰囲気は、アルゴン(Ar)と酸素(O2)との混合雰囲気(Ar:O2=30(sccm):15(sccm))とした。 Note that in Samples 1 and 2, the oxide semiconductor film is a target for forming an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) (In: Ga: Zn = 1: 1: 0.5 [atom%]). The atmosphere for forming the oxide semiconductor film was a mixed atmosphere of argon (Ar) and oxygen (O 2 ) (Ar: O 2 = 30 (sccm): 15 (sccm)).
図7(A)は、試料1のC−V特性を示している。また、図7(B)は、試料1のゲート電圧(Vg)と(1/C)2との関係を示している。図7(B)の弱反転領域における(1/C)2の微分値を、数式(3)に代入すると、酸化物半導体膜中のキャリア密度1.8×1012/cm3が得られた。 FIG. 7A shows the CV characteristics of Sample 1. FIG. FIG. 7B shows the relationship between the gate voltage (Vg) of sample 1 and (1 / C) 2 . When the differential value of (1 / C) 2 in the weak inversion region in FIG. 7B is substituted into Equation (3), a carrier density of 1.8 × 10 12 / cm 3 in the oxide semiconductor film is obtained. .
図8(A)は、試料2のC−V特性を示している。また、図8(B)は、試料2のゲート電圧(Vg)と(1/C)2との関係を示している。図8(B)の弱反転領域における(1/C)2の微分値を、数式(3)に代入すると、酸化物半導体膜中のキャリア密度6.0×1010/cm3が得られた。 FIG. 8A shows the CV characteristics of Sample 2. FIG. 8B shows the relationship between the gate voltage (Vg) of sample 2 and (1 / C) 2 . When the differential value of (1 / C) 2 in the weak inversion region in FIG. 8B is substituted into Equation (3), a carrier density of 6.0 × 10 10 / cm 3 in the oxide semiconductor film was obtained. .
以上の結果より、酸素を引き抜く効果を有する金属膜を用いたMOSキャパシタ(試料1)と、酸素を引き抜く効果を有しない金属膜を用いたMOSキャパシタ(試料2)では、酸化物半導体膜中のキャリア密度が少なくとも2桁異なることがわかった。これより、金属膜によって酸化物半導体膜から酸素が引き抜かれ、酸化物半導体膜における酸素欠損が増加した結果、金属膜に接する酸化物半導体膜がn型化したことが示唆された。なお、n型化とは、多数キャリアである電子が増加することを意味する。 From the above results, in the MOS capacitor (sample 1) using a metal film having an effect of extracting oxygen and the MOS capacitor (sample 2) using a metal film having no effect of extracting oxygen, It was found that the carrier density was at least two orders of magnitude different. This suggested that oxygen was extracted from the oxide semiconductor film by the metal film and oxygen vacancies in the oxide semiconductor film increased, and as a result, the oxide semiconductor film in contact with the metal film became n-type. The n-type means that the number of electrons that are majority carriers increases.
[酸化チタン膜の導電性について]
上記の計算結果を参酌し、図1に示す構成の薄膜トランジスタにおいて、金属膜70がチタンの結晶を有する金属膜である場合を考えた。
[Conductivity of titanium oxide film]
In consideration of the above calculation results, the case where the metal film 70 is a metal film having a titanium crystal in the thin film transistor having the configuration shown in FIG. 1 was considered.
In−Ga−Zn−O系酸化物半導体膜(図1の「酸化物半導体膜40」に対応。)とチタン膜(図1の「金属膜70」に対応。)との界面には、チタンに引き抜かれた酸素がチタンと反応することにより、酸化チタン膜(図1の「金属酸化物膜60」に対応。)が形成された。次に、この酸化チタン膜の導電性について、計算科学により検証した結果を示す。 At the interface between the In—Ga—Zn—O-based oxide semiconductor film (corresponding to the “oxide semiconductor film 40” in FIG. 1) and the titanium film (corresponding to the “metal film 70” in FIG. 1), titanium is present. The oxygen extracted by the reaction with titanium formed a titanium oxide film (corresponding to “metal oxide film 60” in FIG. 1). Next, the result verified by computational science about the conductivity of this titanium oxide film is shown.
二酸化チタンは、ルチル構造(高温型の正方晶)、アナターゼ構造(低温型の正方晶)、ブルッカイト構造(斜方晶)など、いくつかの結晶構造をとった。アナターゼ型およびブルッカイト型は、加熱すると最も安定な構造のルチル型に不可逆的に変化することから、上記二酸化チタンはルチル構造をとるものと仮定した。 Titanium dioxide has several crystal structures such as a rutile structure (high-temperature tetragonal crystal), anatase structure (low-temperature tetragonal crystal), and brookite structure (orthorhombic crystal). The anatase type and brookite type were irreversibly changed to the most stable rutile type when heated, and therefore it was assumed that the titanium dioxide had a rutile structure.
図9は、ルチル構造を有する二酸化チタンの結晶構造を示す図である。ルチル構造は正方晶であり、結晶の対称性を示す空間群はP42/mnmに属する。なお、アナターゼ構造の二酸化チタンも、ルチル構造の二酸化チタンと同様に、結晶の対称性を示す空間群はP42/mnmに属する。 FIG. 9 is a diagram showing a crystal structure of titanium dioxide having a rutile structure. The rutile structure is tetragonal, and the space group showing the symmetry of the crystal belongs to P42 / mnm. In addition, the space group which shows the symmetry of a crystal also belongs to P42 / mnm similarly to the titanium dioxide of an anatase structure similarly to the titanium dioxide of a rutile structure.
上記二酸化チタンの結晶構造に対して、GGA−PBE汎関数を用いた密度汎関数法により、状態密度を求める計算を行った。対称性は維持したまま、セル構造も含めた構造最適化を行い、状態密度を求めた。密度汎関数法を用いた計算には、CASTEPコードに導入された平面波擬ポテンシャル法を用いた。カットオフエネルギーは380eVとした。 For the crystal structure of titanium dioxide, calculation for obtaining the state density was performed by a density functional method using a GGA-PBE functional. While maintaining symmetry, structural optimization including the cell structure was performed to obtain the density of states. The plane wave pseudopotential method introduced in the CASTEP code was used for the calculation using the density functional method. The cut-off energy was 380 eV.
図10は、ルチル構造を有する二酸化チタンの状態密度図である。図10に示すように、ルチル構造を有する二酸化チタンはバンドギャップを有しており、半導体的な状態密度を有することがわかった。なお、密度汎関数法ではバンドギャップが小さく見積もられる傾向にあり、実際の二酸化チタンのバンドギャップは3.0eV程度と、図10の状態密度図に示すバンドギャップよりも大きい。なお、密度汎関数法を用いた電子状態計算は絶対零度において行われるので、エネルギーの原点がフェルミ準位である。 FIG. 10 is a state density diagram of titanium dioxide having a rutile structure. As shown in FIG. 10, it was found that titanium dioxide having a rutile structure has a band gap and has a semiconductor state density. In the density functional method, the band gap tends to be estimated to be small, and the actual band gap of titanium dioxide is about 3.0 eV, which is larger than the band gap shown in the state density diagram of FIG. Since the electronic state calculation using the density functional method is performed at absolute zero, the origin of energy is the Fermi level.
図11は、酸素欠損状態の、ルチル構造を有する二酸化チタンの状態密度図である。計算には、Ti24原子およびO48原子を有する酸化チタンからO原子を一つ抜いた、Ti24原子およびO47原子を有する酸化チタンを、モデルとして用いた。図11に示すように、酸素欠損がある場合のフェルミ準位が伝導帯に存在し、フェルミ準位で状態密度が0ではなかった。これより、酸素欠損を有する二酸化チタンがn型の導電性を示すことがわかった。 FIG. 11 is a state density diagram of titanium dioxide having a rutile structure in an oxygen deficient state. For the calculation, a titanium oxide having 24 Ti atoms and O47 atoms obtained by extracting one O atom from a titanium oxide having 24 Ti atoms and 48 O atoms was used as a model. As shown in FIG. 11, the Fermi level in the presence of oxygen vacancies exists in the conduction band, and the density of states is not zero at the Fermi level. From this, it was found that titanium dioxide having oxygen deficiency shows n-type conductivity.
図12は、一酸化チタン(TiO)の状態密度図である。図12に示すように、一酸化チタンは金属的な状態密度を有することがわかった。 FIG. 12 is a state density diagram of titanium monoxide (TiO). As shown in FIG. 12, it was found that titanium monoxide has a metallic density of states.
図10に示す二酸化チタンの状態密度図、図11に示す酸素欠損を有する二酸化チタンの状態密度図、および図12に示す一酸化チタンの状態密度図より、酸素欠損を有する二酸化チタン(TiO2−δ)が、0<δ<1の範囲にわたってn型の導電性を示すものと予測された。したがって、酸化チタン膜(金属酸化物膜60)の組成が、一酸化チタンまたは酸素欠損を有する二酸化チタンを含んだものであっても、In−Ga−Zn−O系酸化物半導体膜(酸化物半導体膜40)とチタン膜(金属膜70)との間の電流の流れは、阻害されにくい。 State density map of the titanium dioxide as shown in FIG. 10, the state density diagram of titanium dioxide having an oxygen deficiency shown in FIG. 11, and from the state density map of titanium monoxide shown in FIG. 12, titanium dioxide having an oxygen deficiency (TiO 2- δ ) was predicted to exhibit n-type conductivity over the range 0 <δ <1. Therefore, even if the composition of the titanium oxide film (metal oxide film 60) includes titanium monoxide or titanium dioxide having oxygen vacancies, the In—Ga—Zn—O-based oxide semiconductor film (oxide) The current flow between the semiconductor film 40) and the titanium film (metal film 70) is not easily inhibited.
(実施の形態4)
上記実施の形態で説明した薄膜トランジスタは、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビまたはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラやデジタルビデオカメラなどのカメラ、デジタルフォトフレーム、携帯電話機(携帯電話または携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機、太陽電池などが挙げられる。以下に、上記実施の形態で説明した薄膜トランジスタを適用した電子機器の一例について、図13を参照して説明する。
(Embodiment 4)
The thin film transistor described in the above embodiment can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (a mobile phone or a mobile phone device). Also, portable game machines, portable information terminals, sound reproducing devices, large game machines such as pachinko machines, solar cells, and the like. An example of an electronic device to which the thin film transistor described in the above embodiment is applied is described below with reference to FIGS.
図13(A)は、上記実施の形態で説明した薄膜トランジスタを適用した携帯電話機の一例を示している。この携帯電話機は、筐体120に組み込まれた表示部121を備えている。 FIG. 13A illustrates an example of a mobile phone to which the thin film transistor described in the above embodiment is applied. This mobile phone includes a display unit 121 incorporated in a housing 120.
この携帯電話機は、表示部121を指などで触れることで、情報の入力ができる。また、電話を掛ける、メールを打つなどの操作も、表示部121を指などで触れることにより行うことができる。 This mobile phone can input information by touching the display unit 121 with a finger or the like. In addition, operations such as making a call and typing a mail can be performed by touching the display unit 121 with a finger or the like.
例えば、表示部121における画素のスイッチング素子として、上記実施の形態で説明した薄膜トランジスタを複数配置することで、この携帯電話機の性能を高めることができる。 For example, by arranging a plurality of thin film transistors described in the above embodiment as switching elements of pixels in the display portion 121, the performance of this mobile phone can be improved.
図13(B)は、上記実施の形態で説明した薄膜トランジスタを適用したテレビジョン装置の一例を示している。このテレビジョン装置は、筐体130に表示部131が組み込まれている。 FIG. 13B illustrates an example of a television device to which the thin film transistor described in the above embodiment is applied. In this television apparatus, a display portion 131 is incorporated in a housing 130.
例えば、表示部131における画素のスイッチング素子として、上記実施の形態で説明した薄膜トランジスタを複数配置することで、このテレビジョン装置の性能を高めることができる。 For example, by arranging a plurality of thin film transistors described in the above embodiment as switching elements of pixels in the display portion 131, the performance of the television device can be improved.
以上のように、上記実施の形態で説明した薄膜トランジスタは、さまざまな電子機器の表示部に配置することで、その電子機器の性能を高めることができる。 As described above, the thin film transistor described in the above embodiment can be improved in performance of the electronic device by being provided in a display portion of various electronic devices.
図14は、In−Ga−Zn−O系酸化物半導体を用いた薄膜トランジスタの断面を、透過型電子顕微鏡(TEM:Transmission Electron Microscope、日立製作所「H−9000NAR」)で加速電圧を300kVとして観察した写真である。 FIG. 14 shows a cross section of a thin film transistor using an In—Ga—Zn—O-based oxide semiconductor observed with a transmission electron microscope (TEM: Transmission Electron Microscope, Hitachi “H-9000NAR”) at an acceleration voltage of 300 kV. It is a photograph.
図14に示す薄膜トランジスタは、酸化物半導体膜40としてIn−Ga−Zn−O系酸化物半導体膜を50nm成膜後、窒素雰囲気下において第1の加熱処理(650℃、1時間)を行い、その後金属膜70としてチタン膜を150nm成膜し、さらに窒素雰囲気下において第2の加熱処理(250℃、1時間)を行ったものである。 In the thin film transistor illustrated in FIG. 14, an In—Ga—Zn—O-based oxide semiconductor film having a thickness of 50 nm is formed as the oxide semiconductor film 40, and then first heat treatment (650 ° C., 1 hour) is performed in a nitrogen atmosphere. Thereafter, a titanium film having a thickness of 150 nm is formed as the metal film 70, and second heat treatment (250 ° C., 1 hour) is performed in a nitrogen atmosphere.
図14において、酸化物半導体膜40と金属膜70との界面に金属酸化物膜60が形成されることが確認された。また酸化物半導体膜40内の金属酸化物膜60と接する領域に、金属高濃度領域50が形成されることが確認された。なお、FFTM(Fast Fourier Transform Mapping)法を用いた解析の結果、この薄膜トランジスタの金属高濃度領域50には、インジウム(In)の組成に近い結晶が析出していることが確認された。同様に、金属酸化物膜60として、酸化チタン膜が形成されていることが確認された。 In FIG. 14, it was confirmed that the metal oxide film 60 was formed at the interface between the oxide semiconductor film 40 and the metal film 70. In addition, it was confirmed that the metal high concentration region 50 was formed in a region in the oxide semiconductor film 40 in contact with the metal oxide film 60. As a result of the analysis using the Fast Fourier Transform Mapping (FFTM) method, it was confirmed that crystals close to the composition of indium (In) were deposited in the metal high concentration region 50 of the thin film transistor. Similarly, it was confirmed that a titanium oxide film was formed as the metal oxide film 60.
10 基板
20 ゲート電極
30 ゲート絶縁膜
40 酸化物半導体膜
50 金属高濃度領域
60 金属酸化物膜
70 金属膜
80 絶縁膜
100 領域
120 筐体
121 表示部
130 筐体
131 表示部
DESCRIPTION OF SYMBOLS 10 Substrate 20 Gate electrode 30 Gate insulating film 40 Oxide semiconductor film 50 High metal concentration region 60 Metal oxide film 70 Metal film 80 Insulating film 100 region 120 Case 121 Display unit 130 Case 131 Display unit
Claims (5)
前記酸化物半導体膜は、第1の領域と、第2の領域と、第3の領域とを有し、
前記第3の領域は、前記第1の領域と前記第2の領域とに挟まれ、且つチャネル形成領域としての機能を有し、
前記第1の領域の上面と接する第1の酸化チタン膜と、
前記第2の領域の上面と接する第2の酸化チタン膜と、
前記第1の酸化チタン膜を挟んで前記第1の領域上と重なる部分を有し、ソース電極として機能する第1のチタン膜と、
前記第2の酸化チタン膜を挟んで前記第2の領域上と重なる部分を有し、ドレイン電極として機能する第2のチタン膜と、
前記第1のチタン膜上、前記第2のチタン膜上、及び前記第3の領域上に接する絶縁膜と、を有し、
前記第1の領域と前記第1の酸化チタン膜との界面及び前記第2の領域と前記第2の酸化チタン膜との界面において、インジウムの結晶粒または微結晶が存在するトランジスタの作製方法であって、
前記酸化物半導体膜を形成後、前記第1の領域上面、前記第2の領域上面、及び前記第3の領域上面に接して、チタン膜を形成し、
前記チタン膜をエッチングして、前記第1のチタン膜及び前記第2のチタン膜を形成し、
前記第1のチタン膜上、前記第2のチタン膜上、及び前記第3の領域上に接して、前記絶縁膜を形成し、
前記絶縁膜を形成後に加熱処理を行うことにより、前記第1の酸化チタン膜、前記第2の酸化チタン膜、及び前記インジウムの結晶粒または微結晶を形成することを特徴とするトランジスタの作製方法。 Lee indium has an oxide semiconductor film including gallium, and zinc,
The oxide semiconductor film has a first region, a second region, and a third region,
The third region is sandwiched between the first region and the second region, and has a function as a channel formation region,
A first titanium oxide film in contact with an upper surface of the first region ;
A second titanium oxide film in contact with the upper surface of the second region ;
A first titanium film having a portion overlapping with the first region across the first titanium oxide film and functioning as a source electrode;
A second titanium film that has a portion overlapping the second region across the second titanium oxide film and functions as a drain electrode;
A first titanium film, the second titanium film, and an insulating film in contact with the third region,
At the interface between the interface and the said second region second titanium oxide layer between the before and Symbol first region the first titanium oxide layer, a method for manufacturing a transistor exists grains or microcrystals of indium Because
After forming the oxide semiconductor film, a titanium film is formed in contact with the upper surface of the first region, the upper surface of the second region, and the upper surface of the third region,
Etching the titanium film to form the first titanium film and the second titanium film,
Forming the insulating film on and in contact with the first titanium film, the second titanium film, and the third region;
A method for manufacturing a transistor is characterized in that the first titanium oxide film, the second titanium oxide film, and the indium crystal grains or microcrystals are formed by performing heat treatment after the insulating film is formed. .
基板上のゲート電極と、
前記ゲート電極上のゲート絶縁膜と、
前記ゲート絶縁膜上の前記酸化物半導体膜を有することを特徴とするトランジスタの作製方法。 In claim 1,
A gate electrode on the substrate;
A gate insulating film on the gate electrode;
The method for manufacturing a transistor which comprises said oxide semiconductor film on the gate insulating film.
前記加熱処理は、不活性ガス雰囲気下または窒素ガス雰囲気下で行われることを特徴とするトランジスタの作製方法。The method for manufacturing a transistor is characterized in that the heat treatment is performed in an inert gas atmosphere or a nitrogen gas atmosphere.
前記加熱処理は、100℃以上400℃以下で行われることを特徴とするトランジスタの作製方法。The method for manufacturing a transistor is characterized in that the heat treatment is performed at 100 ° C to 400 ° C.
前記絶縁膜は、酸化シリコン、酸化窒化シリコン、酸化アルミニウム、または酸化窒化アルミニウムであることを特徴とするトランジスタの作製方法。The method for manufacturing a transistor is characterized in that the insulating film is silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride.
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Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102503687B1 (en) * | 2009-07-03 | 2023-02-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for manufacturing semiconductor device |
WO2011046015A1 (en) | 2009-10-16 | 2011-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Logic circuit and semiconductor device |
KR20120107107A (en) * | 2009-12-04 | 2012-09-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
US8779478B2 (en) * | 2010-06-01 | 2014-07-15 | Sharp Kabushiki Kaisha | Thin film transistor |
CN103038866A (en) * | 2010-07-02 | 2013-04-10 | 合同会社先端配线材料研究所 | Semiconductor device |
WO2012056933A1 (en) * | 2010-10-25 | 2012-05-03 | 株式会社日立製作所 | Oxide semiconductor device and method for manufacturing same |
JP2012169344A (en) * | 2011-02-10 | 2012-09-06 | Sony Corp | Thin film transistor, display device and electronic equipment |
US8659015B2 (en) * | 2011-03-04 | 2014-02-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP5429718B2 (en) | 2011-03-08 | 2014-02-26 | 合同会社先端配線材料研究所 | Oxide semiconductor electrode and method for forming the same |
US9496138B2 (en) * | 2011-07-08 | 2016-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing oxide semiconductor film, method for manufacturing semiconductor device, and semiconductor device |
JP5917385B2 (en) * | 2011-12-27 | 2016-05-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
TWI604609B (en) * | 2012-02-02 | 2017-11-01 | 半導體能源研究所股份有限公司 | Semiconductor device |
JP6059566B2 (en) * | 2012-04-13 | 2017-01-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
US9018624B2 (en) | 2012-09-13 | 2015-04-28 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic appliance |
JP6021586B2 (en) | 2012-10-17 | 2016-11-09 | 株式会社半導体エネルギー研究所 | Semiconductor device |
TWI527230B (en) | 2012-10-19 | 2016-03-21 | 元太科技工業股份有限公司 | Thin film transistor structure and method for manufacturing the same |
US9246011B2 (en) * | 2012-11-30 | 2016-01-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
DE112013006219T5 (en) | 2012-12-25 | 2015-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and its manufacturing method |
JP2015018939A (en) * | 2013-07-11 | 2015-01-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP6180908B2 (en) * | 2013-12-06 | 2017-08-16 | 富士フイルム株式会社 | Metal oxide semiconductor film, thin film transistor, display device, image sensor and X-ray sensor |
KR102260886B1 (en) * | 2014-12-10 | 2021-06-07 | 삼성디스플레이 주식회사 | Thin film transistor |
KR102283812B1 (en) | 2015-02-04 | 2021-08-02 | 삼성디스플레이 주식회사 | Semiconductor element and organic light emitting display device having a semiconductor element |
US9761732B2 (en) | 2015-02-25 | 2017-09-12 | Snaptrack Inc. | Tunnel thin film transistor with hetero-junction structure |
CN106887436B (en) * | 2015-12-16 | 2019-10-25 | 鸿富锦精密工业(深圳)有限公司 | Thin-film transistor array base-plate and preparation method thereof |
US10388738B2 (en) * | 2016-04-01 | 2019-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Composite oxide semiconductor and method for manufacturing the same |
CN107689391B (en) * | 2016-08-04 | 2020-09-08 | 鸿富锦精密工业(深圳)有限公司 | Thin film transistor substrate and preparation method thereof |
JP6268248B2 (en) * | 2016-09-22 | 2018-01-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing transistor |
TW202129966A (en) * | 2016-10-21 | 2021-08-01 | 日商半導體能源研究所股份有限公司 | Composite oxide semiconductor and transistor |
CN110383436A (en) | 2017-03-13 | 2019-10-25 | 株式会社半导体能源研究所 | Composite oxides and transistor |
KR102263435B1 (en) | 2017-09-13 | 2021-06-11 | 주식회사 엘지에너지솔루션 | Cylindrical Battery Cell Having no Beading Part |
JP7398860B2 (en) * | 2018-08-08 | 2023-12-15 | 株式会社ジャパンディスプレイ | Manufacturing method of thin film transistor |
US11430846B2 (en) * | 2019-03-19 | 2022-08-30 | Innolux Corporation | Display module with transistor |
TWI690060B (en) | 2019-04-25 | 2020-04-01 | 元太科技工業股份有限公司 | Memory structure and manufacturing method thereof |
US20210376156A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Company Limited | Raised source/drain oxide semiconducting thin film transistor and methods of making the same |
Family Cites Families (117)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60198861A (en) | 1984-03-23 | 1985-10-08 | Fujitsu Ltd | Thin film transistor |
JPH0244256B2 (en) | 1987-01-28 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN2O5DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
JPH0244258B2 (en) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN3O6DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
JPS63210023A (en) | 1987-02-24 | 1988-08-31 | Natl Inst For Res In Inorg Mater | Compound having laminar structure of hexagonal crystal system expressed by ingazn4o7 and its production |
JPH0244260B2 (en) | 1987-02-24 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN5O8DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
JPH0244262B2 (en) | 1987-02-27 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN6O9DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
JPH0244263B2 (en) | 1987-04-22 | 1990-10-03 | Kagaku Gijutsucho Mukizaishitsu Kenkyushocho | INGAZN7O10DESHIMESARERUROTSUHOSHOKEINOSOJOKOZOOJUSURUKAGOBUTSUOYOBISONOSEIZOHO |
JPH05251705A (en) | 1992-03-04 | 1993-09-28 | Fuji Xerox Co Ltd | Thin-film transistor |
JP3479375B2 (en) | 1995-03-27 | 2003-12-15 | 科学技術振興事業団 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
KR100394896B1 (en) * | 1995-08-03 | 2003-11-28 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | A semiconductor device including a transparent switching element |
JP3625598B2 (en) * | 1995-12-30 | 2005-03-02 | 三星電子株式会社 | Manufacturing method of liquid crystal display device |
JP4170454B2 (en) | 1998-07-24 | 2008-10-22 | Hoya株式会社 | Article having transparent conductive oxide thin film and method for producing the same |
JP2000150861A (en) * | 1998-11-16 | 2000-05-30 | Tdk Corp | Oxide thin film |
JP3276930B2 (en) * | 1998-11-17 | 2002-04-22 | 科学技術振興事業団 | Transistor and semiconductor device |
TW460731B (en) * | 1999-09-03 | 2001-10-21 | Ind Tech Res Inst | Electrode structure and production method of wide viewing angle LCD |
JP4089858B2 (en) | 2000-09-01 | 2008-05-28 | 国立大学法人東北大学 | Semiconductor device |
KR20020038482A (en) * | 2000-11-15 | 2002-05-23 | 모리시타 요이찌 | Thin film transistor array, method for producing the same, and display panel using the same |
JP3997731B2 (en) * | 2001-03-19 | 2007-10-24 | 富士ゼロックス株式会社 | Method for forming a crystalline semiconductor thin film on a substrate |
JP2002289859A (en) | 2001-03-23 | 2002-10-04 | Minolta Co Ltd | Thin-film transistor |
JP3925839B2 (en) | 2001-09-10 | 2007-06-06 | シャープ株式会社 | Semiconductor memory device and test method thereof |
JP4090716B2 (en) | 2001-09-10 | 2008-05-28 | 雅司 川崎 | Thin film transistor and matrix display device |
JP4164562B2 (en) | 2002-09-11 | 2008-10-15 | 独立行政法人科学技術振興機構 | Transparent thin film field effect transistor using homologous thin film as active layer |
WO2003040441A1 (en) * | 2001-11-05 | 2003-05-15 | Japan Science And Technology Agency | Natural superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film |
JP4083486B2 (en) * | 2002-02-21 | 2008-04-30 | 独立行政法人科学技術振興機構 | Method for producing LnCuO (S, Se, Te) single crystal thin film |
CN1445821A (en) * | 2002-03-15 | 2003-10-01 | 三洋电机株式会社 | Forming method of ZnO film and ZnO semiconductor layer, semiconductor element and manufacturing method thereof |
JP3933591B2 (en) * | 2002-03-26 | 2007-06-20 | 淳二 城戸 | Organic electroluminescent device |
US7339187B2 (en) * | 2002-05-21 | 2008-03-04 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures |
JP2004022625A (en) * | 2002-06-13 | 2004-01-22 | Murata Mfg Co Ltd | Manufacturing method of semiconductor device and its manufacturing method |
US7105868B2 (en) * | 2002-06-24 | 2006-09-12 | Cermet, Inc. | High-electron mobility transistor with zinc oxide |
US7067843B2 (en) * | 2002-10-11 | 2006-06-27 | E. I. Du Pont De Nemours And Company | Transparent oxide semiconductor thin film transistors |
JP4166105B2 (en) | 2003-03-06 | 2008-10-15 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
JP2004273732A (en) | 2003-03-07 | 2004-09-30 | Sharp Corp | Active matrix substrate and its producing process |
JP4108633B2 (en) * | 2003-06-20 | 2008-06-25 | シャープ株式会社 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
US7262463B2 (en) * | 2003-07-25 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | Transistor including a deposited channel region having a doped portion |
US7145174B2 (en) * | 2004-03-12 | 2006-12-05 | Hewlett-Packard Development Company, Lp. | Semiconductor device |
JP4620046B2 (en) | 2004-03-12 | 2011-01-26 | 独立行政法人科学技術振興機構 | Thin film transistor and manufacturing method thereof |
US7282782B2 (en) * | 2004-03-12 | 2007-10-16 | Hewlett-Packard Development Company, L.P. | Combined binary oxide semiconductor device |
US7297977B2 (en) * | 2004-03-12 | 2007-11-20 | Hewlett-Packard Development Company, L.P. | Semiconductor device |
US7211825B2 (en) * | 2004-06-14 | 2007-05-01 | Yi-Chi Shih | Indium oxide-based thin film transistors and circuits |
JP2006100760A (en) * | 2004-09-02 | 2006-04-13 | Casio Comput Co Ltd | Thin-film transistor and its manufacturing method |
US7285501B2 (en) * | 2004-09-17 | 2007-10-23 | Hewlett-Packard Development Company, L.P. | Method of forming a solution processed device |
US7298084B2 (en) * | 2004-11-02 | 2007-11-20 | 3M Innovative Properties Company | Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes |
KR100911698B1 (en) * | 2004-11-10 | 2009-08-10 | 캐논 가부시끼가이샤 | Field effect transistor employing an amorphous oxide |
KR100953596B1 (en) * | 2004-11-10 | 2010-04-21 | 캐논 가부시끼가이샤 | Light-emitting device |
US7863611B2 (en) * | 2004-11-10 | 2011-01-04 | Canon Kabushiki Kaisha | Integrated circuits utilizing amorphous oxides |
US7829444B2 (en) * | 2004-11-10 | 2010-11-09 | Canon Kabushiki Kaisha | Field effect transistor manufacturing method |
US7791072B2 (en) * | 2004-11-10 | 2010-09-07 | Canon Kabushiki Kaisha | Display |
US7601984B2 (en) * | 2004-11-10 | 2009-10-13 | Canon Kabushiki Kaisha | Field effect transistor with amorphous oxide active layer containing microcrystals and gate electrode opposed to active layer through gate insulator |
US7453065B2 (en) * | 2004-11-10 | 2008-11-18 | Canon Kabushiki Kaisha | Sensor and image pickup device |
US7579224B2 (en) * | 2005-01-21 | 2009-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film semiconductor device |
US7608531B2 (en) * | 2005-01-28 | 2009-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
TWI472037B (en) * | 2005-01-28 | 2015-02-01 | Semiconductor Energy Lab | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
US7858451B2 (en) * | 2005-02-03 | 2010-12-28 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device, semiconductor device and manufacturing method thereof |
US7948171B2 (en) * | 2005-02-18 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device |
US20060197092A1 (en) * | 2005-03-03 | 2006-09-07 | Randy Hoffman | System and method for forming conductive material on a substrate |
US8681077B2 (en) * | 2005-03-18 | 2014-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and display device, driving method and electronic apparatus thereof |
WO2006105077A2 (en) * | 2005-03-28 | 2006-10-05 | Massachusetts Institute Of Technology | Low voltage thin film transistor with high-k dielectric material |
US7645478B2 (en) * | 2005-03-31 | 2010-01-12 | 3M Innovative Properties Company | Methods of making displays |
US8300031B2 (en) * | 2005-04-20 | 2012-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising transistor having gate and drain connected through a current-voltage conversion element |
JP2006344849A (en) * | 2005-06-10 | 2006-12-21 | Casio Comput Co Ltd | Thin film transistor |
US7402506B2 (en) * | 2005-06-16 | 2008-07-22 | Eastman Kodak Company | Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby |
US7691666B2 (en) * | 2005-06-16 | 2010-04-06 | Eastman Kodak Company | Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby |
US7507618B2 (en) * | 2005-06-27 | 2009-03-24 | 3M Innovative Properties Company | Method for making electronic devices using metal oxide nanoparticles |
KR100711890B1 (en) * | 2005-07-28 | 2007-04-25 | 삼성에스디아이 주식회사 | Organic Light Emitting Display and Fabrication Method for the same |
JP2007059128A (en) * | 2005-08-23 | 2007-03-08 | Canon Inc | Organic electroluminescent display device and manufacturing method thereof |
JP2007073705A (en) * | 2005-09-06 | 2007-03-22 | Canon Inc | Oxide-semiconductor channel film transistor and its method of manufacturing same |
JP4850457B2 (en) * | 2005-09-06 | 2012-01-11 | キヤノン株式会社 | Thin film transistor and thin film diode |
JP5116225B2 (en) * | 2005-09-06 | 2013-01-09 | キヤノン株式会社 | Manufacturing method of oxide semiconductor device |
JP4280736B2 (en) * | 2005-09-06 | 2009-06-17 | キヤノン株式会社 | Semiconductor element |
JP4560502B2 (en) * | 2005-09-06 | 2010-10-13 | キヤノン株式会社 | Field effect transistor |
JP5064747B2 (en) | 2005-09-29 | 2012-10-31 | 株式会社半導体エネルギー研究所 | Semiconductor device, electrophoretic display device, display module, electronic device, and method for manufacturing semiconductor device |
JP5078246B2 (en) | 2005-09-29 | 2012-11-21 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
EP1998374A3 (en) | 2005-09-29 | 2012-01-18 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device having oxide semiconductor layer and manufacturing method thereof |
JP5037808B2 (en) * | 2005-10-20 | 2012-10-03 | キヤノン株式会社 | Field effect transistor using amorphous oxide, and display device using the transistor |
KR101112655B1 (en) * | 2005-11-15 | 2012-02-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Active Matrix Display Device and a Television Receiver Including the Same |
TWI292281B (en) * | 2005-12-29 | 2008-01-01 | Ind Tech Res Inst | Pixel structure of active organic light emitting diode and method of fabricating the same |
US7867636B2 (en) * | 2006-01-11 | 2011-01-11 | Murata Manufacturing Co., Ltd. | Transparent conductive film and method for manufacturing the same |
JP4977478B2 (en) * | 2006-01-21 | 2012-07-18 | 三星電子株式会社 | ZnO film and method of manufacturing TFT using the same |
US7576394B2 (en) * | 2006-02-02 | 2009-08-18 | Kochi Industrial Promotion Center | Thin film transistor including low resistance conductive thin films and manufacturing method thereof |
US7977169B2 (en) * | 2006-02-15 | 2011-07-12 | Kochi Industrial Promotion Center | Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof |
KR20070101595A (en) * | 2006-04-11 | 2007-10-17 | 삼성전자주식회사 | Zno thin film transistor |
US20070252928A1 (en) * | 2006-04-28 | 2007-11-01 | Toppan Printing Co., Ltd. | Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof |
JP5028033B2 (en) * | 2006-06-13 | 2012-09-19 | キヤノン株式会社 | Oxide semiconductor film dry etching method |
JP4999400B2 (en) * | 2006-08-09 | 2012-08-15 | キヤノン株式会社 | Oxide semiconductor film dry etching method |
JP4609797B2 (en) * | 2006-08-09 | 2011-01-12 | Nec液晶テクノロジー株式会社 | Thin film device and manufacturing method thereof |
JP4332545B2 (en) * | 2006-09-15 | 2009-09-16 | キヤノン株式会社 | Field effect transistor and manufacturing method thereof |
JP5164357B2 (en) * | 2006-09-27 | 2013-03-21 | キヤノン株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP4274219B2 (en) * | 2006-09-27 | 2009-06-03 | セイコーエプソン株式会社 | Electronic devices, organic electroluminescence devices, organic thin film semiconductor devices |
US7622371B2 (en) * | 2006-10-10 | 2009-11-24 | Hewlett-Packard Development Company, L.P. | Fused nanocrystal thin film semiconductor and method |
US7772021B2 (en) * | 2006-11-29 | 2010-08-10 | Samsung Electronics Co., Ltd. | Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays |
JP2008140684A (en) * | 2006-12-04 | 2008-06-19 | Toppan Printing Co Ltd | Color el display, and its manufacturing method |
KR101303578B1 (en) * | 2007-01-05 | 2013-09-09 | 삼성전자주식회사 | Etching method of thin film |
US8207063B2 (en) * | 2007-01-26 | 2012-06-26 | Eastman Kodak Company | Process for atomic layer deposition |
KR101410926B1 (en) * | 2007-02-16 | 2014-06-24 | 삼성전자주식회사 | Thin film transistor and method for forming the same |
WO2008099863A1 (en) * | 2007-02-16 | 2008-08-21 | Idemitsu Kosan Co., Ltd. | Semiconductor, semiconductor device, and complementary transistor circuit device |
US8129714B2 (en) * | 2007-02-16 | 2012-03-06 | Idemitsu Kosan Co., Ltd. | Semiconductor, semiconductor device, complementary transistor circuit device |
KR100858088B1 (en) * | 2007-02-28 | 2008-09-10 | 삼성전자주식회사 | Thin Film Transistor and method of manufacturing the same |
KR100851215B1 (en) * | 2007-03-14 | 2008-08-07 | 삼성에스디아이 주식회사 | Thin film transistor and organic light-emitting dislplay device having the thin film transistor |
JP5197058B2 (en) * | 2007-04-09 | 2013-05-15 | キヤノン株式会社 | Light emitting device and manufacturing method thereof |
US7795613B2 (en) * | 2007-04-17 | 2010-09-14 | Toppan Printing Co., Ltd. | Structure with transistor |
JP2008270313A (en) * | 2007-04-17 | 2008-11-06 | Matsushita Electric Ind Co Ltd | Semiconductor memory element |
KR101325053B1 (en) * | 2007-04-18 | 2013-11-05 | 삼성디스플레이 주식회사 | Thin film transistor substrate and manufacturing method thereof |
KR20080094300A (en) * | 2007-04-19 | 2008-10-23 | 삼성전자주식회사 | Thin film transistor and method of manufacturing the same and flat panel display comprising the same |
KR101334181B1 (en) * | 2007-04-20 | 2013-11-28 | 삼성전자주식회사 | Thin Film Transistor having selectively crystallized channel layer and method of manufacturing the same |
US8274078B2 (en) | 2007-04-25 | 2012-09-25 | Canon Kabushiki Kaisha | Metal oxynitride semiconductor containing zinc |
KR101345376B1 (en) * | 2007-05-29 | 2013-12-24 | 삼성전자주식회사 | Fabrication method of ZnO family Thin film transistor |
JP5213421B2 (en) | 2007-12-04 | 2013-06-19 | キヤノン株式会社 | Oxide semiconductor thin film transistor |
US8202365B2 (en) * | 2007-12-17 | 2012-06-19 | Fujifilm Corporation | Process for producing oriented inorganic crystalline film, and semiconductor device using the oriented inorganic crystalline film |
JP4623179B2 (en) | 2008-09-18 | 2011-02-02 | ソニー株式会社 | Thin film transistor and manufacturing method thereof |
JP5451280B2 (en) | 2008-10-09 | 2014-03-26 | キヤノン株式会社 | Wurtzite crystal growth substrate, manufacturing method thereof, and semiconductor device |
KR101671210B1 (en) * | 2009-03-06 | 2016-11-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
WO2011043218A1 (en) | 2009-10-09 | 2011-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
WO2011043164A1 (en) | 2009-10-09 | 2011-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
CN102598279B (en) | 2009-11-06 | 2015-10-07 | 株式会社半导体能源研究所 | Semiconductor device |
CN102598284B (en) | 2009-11-06 | 2015-04-15 | 株式会社半导体能源研究所 | Semiconductor device |
CN102668097B (en) * | 2009-11-13 | 2015-08-12 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
JP5612299B2 (en) * | 2009-11-20 | 2014-10-22 | 株式会社半導体エネルギー研究所 | Method for manufacturing transistor |
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WO2011062048A1 (en) | 2011-05-26 |
US20110121289A1 (en) | 2011-05-26 |
KR20200124769A (en) | 2020-11-03 |
US20140284601A1 (en) | 2014-09-25 |
KR101945660B1 (en) | 2019-02-07 |
KR20170117208A (en) | 2017-10-20 |
KR20220041239A (en) | 2022-03-31 |
KR20190109597A (en) | 2019-09-25 |
US9306075B2 (en) | 2016-04-05 |
TWI491046B (en) | 2015-07-01 |
US8766250B2 (en) | 2014-07-01 |
TW201530781A (en) | 2015-08-01 |
US8963149B2 (en) | 2015-02-24 |
KR20160031047A (en) | 2016-03-21 |
TW201130139A (en) | 2011-09-01 |
TWI529950B (en) | 2016-04-11 |
JP2011129897A (en) | 2011-06-30 |
US20150162450A1 (en) | 2015-06-11 |
TW201631762A (en) | 2016-09-01 |
KR20140074404A (en) | 2014-06-17 |
TWI580039B (en) | 2017-04-21 |
KR102026212B1 (en) | 2019-09-27 |
KR20120107079A (en) | 2012-09-28 |
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