WO2012056933A1

WO2012056933A1 - Oxide semiconductor device and method for manufacturing same

Info

Publication number: WO2012056933A1
Application number: PCT/JP2011/073879
Authority: WO
Inventors: 裕紀若菜; 哲史河村; 内山　博幸; 藤井　邦治
Original assignee: 株式会社日立製作所
Priority date: 2010-10-25
Filing date: 2011-10-18
Publication date: 2012-05-03
Also published as: JP5666616B2; JPWO2012056933A1

Abstract

To reduce the contact resistance between an oxide semiconductor layer and a source/drain electrode in a thin film transistor that uses an oxide semiconductor material for a channel layer. A thin film transistor, wherein a gate electrode (11), a gate insulating film (12), an amorphous oxide semiconductor layer (13) that constitutes a channel layer, a source electrode (14s) and a drain electrode (14d) are sequentially laminated in this order, is formed on the upper surface of a substrate (10). Crystal grains (13cg), which contain a constituent element of the amorphous oxide semiconductor layer (13), are formed within the amorphous oxide semiconductor layer (13) in the vicinity of the interfaces with the source electrode (14s) and the drain electrode (14d). The crystal grains (13cg) are formed by utilizing the energy of accelerated particles that are incident on the amorphous oxide semiconductor layer (13) when a conductive film that constitutes the source electrode (14s) and the drain electrode (14d) is deposited.

Description

Oxide semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device having a thin film transistor (TFT: Thin Film Transistor) using an oxide semiconductor material for a channel layer, and a technology effective when applied to the manufacture thereof.

Thin film transistors (TFTs) are used as display device driving transistors in various portable electronic devices such as mobile phones, notebook personal computers, and PDAs because they have a small element area and save space.

Conventionally, most of thin film transistors have been made of silicon-based semiconductor materials typified by amorphous silicon and polycrystalline silicon. This is because there is a merit that a thin film transistor can be manufactured using a manufacturing process and manufacturing technology of a conventional semiconductor device.

However, when a thin film transistor is manufactured using a conventional manufacturing process of a semiconductor device, a processing temperature is 350 ° C. or higher, and thus a usable substrate material is limited. In particular, glass substrates and flexible resin substrates often have a heat-resistant temperature of 350 ° C. or lower, and it is difficult to form thin film transistors on these substrates using a conventional semiconductor device manufacturing process.

Therefore, recently, research and development of a thin film transistor using an oxide semiconductor material that can be formed at a low temperature as a channel layer is underway. In the case where this oxide semiconductor film is used for a channel layer, a thin film transistor can be formed over a glass substrate or a flexible resin substrate, so that a novel device that is not conventionally used can be manufactured at low cost. In addition, a device can be formed using the transparency of the oxide semiconductor material, and the thin film transistor can be applied to an RFID (Radio Frequency Identification) tag or the like.

In order to improve the reliability and device performance of a thin film transistor using the above-described oxide semiconductor material for a channel layer, it is a problem to reduce contact resistance between the oxide semiconductor layer and the source and drain electrodes.

Conventionally, as a method for reducing contact resistance between an oxide semiconductor layer and a source / drain electrode, a low resistance such as a dissimilar metal material layer or an oxygen-deficient oxide semiconductor layer is provided between the oxide semiconductor layer and the source / drain electrode. A method of sandwiching layers (Patent Document 1) and a method of forming low-resistance crystal grains having a composition different from that of the oxide semiconductor layer in the oxide semiconductor layer below the source and drain electrodes are proposed (Patent Document 2). Has been.

JP 2010-080952 A JP 2009-14001 A

In Patent Document 1 in which a low-resistance layer is sandwiched between an oxide semiconductor layer and source and drain electrodes, the low-resistance layer has a lower oxygen concentration in the film than the oxide semiconductor layer and includes crystal fine particles. It has been reported that a good contact can be formed by using a semiconductor layer. However, since it is difficult to form the oxide semiconductor layer and the low resistance layer at the same time in this method, an increase in manufacturing cost accompanying an increase in the number of manufacturing steps is a problem.

Further, in the method of Patent Document 2 in which low-resistance crystal grains are formed in an oxide semiconductor layer, for example, in an oxide semiconductor layer made of In (indium) -Zn (zinc) -Ga (gallium) -O (oxygen). It has been reported that contact resistance is reduced by forming metal crystal grains having a diameter of about 20 nm. However, in the case of this method, a threshold voltage shift or an on-current (Ion) due to a larger number of crystal grains in the oxide semiconductor layer being formed in the vicinity of the gate insulating film than in the vicinity of the source and drain electrodes. / Reduction of off-current (Ioff) ratio is a problem.

Note that in the method of Patent Document 2, the mechanism by which low-resistance crystal grains are formed in the oxide semiconductor layer is unknown, but the metal material constituting the source and drain electrodes diffuses into the oxide semiconductor layer. Are considered to be related.

An object of the present invention is to reduce a contact resistance between an oxide semiconductor layer and a source / drain electrode without causing a problem as in the prior art in a thin film transistor using an oxide semiconductor material for a channel layer. It is to provide a technology that can be used.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

An oxide semiconductor device which is a preferable embodiment of the present invention includes a thin film transistor in which a gate electrode, a gate insulating film, an amorphous oxide semiconductor layer constituting a channel layer, a source, and a drain electrode are stacked in this order on an upper surface of a substrate. And the amorphous oxide semiconductor layer in the vicinity of the interface with the source and drain electrodes has crystal grains containing the constituent elements of the amorphous oxide semiconductor layer.

The crystal grains are formed by using energy of accelerated particles incident on the amorphous oxide semiconductor layer when depositing conductive films for source and drain electrodes on the amorphous oxide semiconductor layer.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

A thin film transistor with low contact resistance between the oxide semiconductor layer and the source and drain electrodes can be realized.

Further, the contact resistance between the oxide semiconductor layer and the source and drain electrodes can be reduced without increasing the number of manufacturing steps of the thin film transistor.

It is sectional drawing which shows the manufacturing method of the thin-film transistor which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the thin-film transistor following FIG. FIG. 3 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 2. FIG. 4 is a cross-sectional view showing a method for manufacturing the thin film transistor following FIG. 3. FIG. 5 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 5. FIG. 7 is an enlarged view of FIG. 6. FIG. 7 is a cross-sectional view showing a method for manufacturing the thin film transistor following FIG. 6. It is a graph which shows the relationship between the gate voltage (Vg) and drain current (Id) of the thin-film transistor of Embodiment 1 and a comparative example. 4 is a cross-sectional TEM photograph of the vicinity of an interface between a drain electrode and an oxide semiconductor layer in the thin film transistor of Embodiment 1. It is the photograph of the crystal structure of the crystal grain 13cg investigated by FFT diffraction from the TEM image of FIG. It is sectional drawing which shows the manufacturing method of the thin-film transistor which is Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the thin-film transistor following FIG. FIG. 14 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 13. It is sectional drawing which shows another example of the thin-film transistor of this invention. It is sectional drawing of the thin-film transistor which is Embodiment 3 of this invention. 10 is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) of the thin film transistor of the third embodiment. It is a figure which shows schematic structure of the RFID tag using the thin-film transistor of this invention. It is a circuit block diagram which shows an example of the array structure of the semiconductor device using the thin-film transistor of this invention. FIG. 20 is a schematic diagram of an active matrix liquid crystal display device to which the array shown in FIG. 19 is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. Further, in the drawings describing the embodiments, hatching may be given even in plan views in order to make the configuration easy to understand.

(Embodiment 1)
This embodiment is applied to a bottom gate / top contact thin film transistor. Here, the bottom gate means a structure in which the gate electrode is arranged below the channel layer (oxide semiconductor layer), and the top contact means that the source electrode and the drain electrode are arranged above the channel layer. Means the structure.

The bottom gate / top contact type thin film transistor of this embodiment is manufactured by the following method.

First, as shown in FIG. 1, an insulating substrate 10 is prepared. Examples of the material of the substrate 10 include Si (silicon), sapphire, quartz, glass, and a flexible plastic film. Examples of the plastic film material include polyethylene terephthalate, polyethylene naphthalate, polyetherimide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. Moreover, what provided the insulating coating layer on the surface of the above-mentioned material as needed can also be used.

Next, as shown in FIG. 2, a gate electrode 11 is formed by depositing a conductive film on the upper surface of the substrate 10 and then patterning the conductive film. As the conductive film constituting the gate electrode 11, Mo (molybdenum), Cr (chromium), W (tungsten), Al (aluminum), Cu (copper), Ti (titanium), Ni (nickel), Ta (tantalum) A single layer film of metal such as Ag (silver), Co (cobalt), Zn, Au (gold), and Pt (platinum), an alloy film containing two or more of these metals, and a laminated film of these metals can do. In addition, conductive metal oxide films such as ZnO (zinc oxide) to which ITO (In—Sn—O: indium tin oxide), Al, Ga, In, or B (boron) is added, and their conductivity A laminated film of a metal oxide and the metal can also be used. Furthermore, a single layer film of conductive metal nitride such as TiN (titanium nitride), a laminated film of the conductive metal nitride and the metal, or the like can also be used.

The above-described various conductive films are deposited by CVD, sputtering, vapor deposition or the like, and patterning is performed by dry etching or wet etching using a photoresist film as a mask.

Next, as shown in FIG. 3, a gate insulating film 12 is formed on the upper surface of the substrate 10 on which the gate electrode 11 is formed.

The insulating film constituting the gate insulating film 12 includes a silicon oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, a Y ₂ O ₃ (yttrium oxide) film, an HfO ₂ (hafnium oxide) film, and a YSZ (yttria stable). Zirconia) film, organic polymer insulating film, and the like. Materials for organic polymer insulating films include polyimide derivatives, benzocyclobutene derivatives, photoacryl derivatives, polystyrene derivatives, polyvinyl phenol derivatives, polyester derivatives, polycarbonate derivatives, polyester derivatives, polyvinyl acetate derivatives, polyurethane derivatives, polysulfone derivatives. Acrylate resin, acrylic resin, epoxy resin, parylene and the like. These insulating films are deposited by a CVD method, a sputtering method, a vapor deposition method, a coating method, or the like.

Next, as shown in FIG. 4, an amorphous oxide semiconductor layer 13 is formed on the gate insulating film 12. The amorphous oxide semiconductor layer 13 is a semiconductor layer that constitutes a channel layer of the thin film transistor, and includes In, Zn, Cd (cadmium), Al, Ga, Si, Sn, Ce (cerium), Ge (germanium), and Hf. An oxide in which one or more elements are combined with oxygen can be exemplified. The oxide film constituting the amorphous oxide semiconductor layer 13 is deposited by sputtering, CVD, pulsed laser deposition (PLD), coating, printing, co-evaporation, or the like. The thickness is about 25 nm to 100 nm. Further, after the amorphous oxide semiconductor layer 13 is formed, impurities may be doped as necessary, or the substrate 10 may be annealed. Further, the patterning of the oxide film is performed by dry etching or wet etching using a photoresist film as a mask.

In this embodiment, first, a multi-source sputtering apparatus capable of simultaneously depositing Zn, Sn, and O is used, the gas pressure is set to 0.5 Pa (Ar (argon) + 10% O ₂ ), the RC power is set to 50 W, and the room temperature is set. Below, an amorphous Zn—Sn—O (zinc tin oxide) film having a thickness of 50 nm was deposited on the gate insulating film 12. Next, the Zn—Sn—O film is patterned by wet etching using a photoresist film as a mask, and the Zn—Sn—O film is left in the region above the gate electrode 11 and the region in the vicinity thereof. An oxide semiconductor layer 13 was formed.

Next, as shown in FIG. 5, an insulating film is deposited on the amorphous oxide semiconductor layer 13, and then the insulating film is patterned to thereby form a channel layer region (region above the gate electrode 11). A barrier layer 15 is formed on the top.

Examples of the insulating film constituting the barrier layer 15 include inorganic insulating films such as a silicon oxide film, a silicon nitride film, and an alumina film, and organic insulating films such as a parylene film. These insulating films are deposited by a CVD method, a sputtering method, a coating method, or the like. The insulating film is patterned by dry etching or wet etching using a photoresist film as a mask.

Next, as shown in FIG. 6, a conductive film 14 is deposited on the amorphous oxide semiconductor layer 13 and the barrier layer 15. Examples of the conductive film 14 include various conductive films that constitute the gate electrode 11 described above. The conductive film 14 is deposited by electron beam evaporation, sputtering, or the like. In the present embodiment, the conductive film 14 made of Al is deposited by using an electron beam evaporation apparatus and setting the acceleration voltage of the electron beam to a value higher than usual (for example, 10 kV).

When the conductive film 14 is deposited on the amorphous oxide semiconductor layer 13 with the acceleration voltage of the electron beam set to a higher value than usual, crystal grains are formed in the vicinity of the surface of the amorphous oxide semiconductor layer 13 as shown in FIG. 13cg is generated. This is because when the conductive film material installed in the electron beam evaporation apparatus is irradiated with an electron beam accelerated at a high voltage, the evaporated conductive film material collides with the surface of the amorphous oxide semiconductor layer 13 at a high speed, and amorphous oxide This is because part of the oxide (Zn—Sn—O in this embodiment) included in the physical semiconductor layer 13 is crystallized by its energy. At this time, since the channel layer region (region above the gate electrode 11) of the amorphous oxide semiconductor layer 13 is covered with the barrier layer 15, the crystal grain 13cg is not formed in this region.

Next, as shown in FIG. 8, a source electrode 14s and a drain electrode 14d are formed by removing the conductive film 14 above the gate electrode 11 by dry etching using a photoresist film as a mask. Through the steps so far, the bottom-gate / top-contact thin film transistor of this embodiment is completed.

A solid line A in FIG. 9 is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) of the thin film transistor manufactured by the above-described method. A broken line B in the figure shows the relationship between the threshold gate voltage (Vg) and the drain current (Id) of the thin film transistor (comparative example) in which the conductive film 14 is deposited with the electron beam acceleration voltage set to 5 kV. It is a graph. The channel length of the two types of thin film transistors was 0.1 mm, and the channel width was 2 mm.

As shown in FIG. 9, the thin film transistor of this embodiment in which the conductive film 14 is deposited with the acceleration voltage of the electron beam set to 10 kV is 2 in comparison with the thin film transistor of the comparative example in which the acceleration voltage of the electron beam is set to 5 kV. The on-current (Ion) was doubled or more.

This is because in the thin film transistor of this embodiment, since the vicinity of the surface of the amorphous oxide semiconductor layer 13 is crystallized, the arrangement of the constituent elements (Zn—Sn—O) of the amorphous oxide semiconductor layer 13 is dense in this region. As a result, the electron which is a carrier easily flows. As a result, the contact resistance between the amorphous oxide semiconductor layer 13 and the source electrode 14s and the drain electrode 14d is reduced, whereas in the thin film transistor of the comparative example, the amorphous oxide semiconductor layer This is because crystal grains 13 cg were not generated in 13.

FIG. 10 is a cross-sectional TEM photograph of the vicinity of the interface between the drain electrode 14d and the amorphous oxide semiconductor layer 13 in the thin film transistor of the present embodiment. As shown in FIG. 10, it was confirmed that the crystal grains 13cg were present in almost one row in the crystal grain existence region (Tcg) within a depth of 10 nm from the interface with the drain electrode 14d. On the other hand, the presence of the crystal grains 13cg could not be confirmed from the cross-sectional TEM photograph of the thin film transistor of the comparative example.

When the crystal structure was examined by FFT diffraction from the TEM image of the crystal grain 13cg, the presence of ZnSnO ₃ as shown in FIG. 11 was confirmed. It was also confirmed at the same time that the region other than the region where the crystal grains 13cg were formed was in an amorphous state.

Next, in order to investigate the relationship between the grain size of the crystal grain 13cg and the crystal grain existence region (Tcg), the deposition conditions of the conductive film (Al film) 14 constituting the source electrode 14s and the drain electrode 14d and the annealing conditions after the deposition Was changed to change the grain size of the crystal grains 13cg and the crystal grain existence region (Tcg). As a result, it was confirmed that the on-current (Ion) was improved when the grain size of the crystal grain 13cg was about 15 nm and the crystal grain existence region (Tcg) was within 20 nm from the surface of the amorphous oxide semiconductor layer 13. In contrast, it was confirmed that when the grain size of the crystal grain 13cg exceeds 20 nm, the crystal grain 13cg starts to grow in a columnar shape, the surface roughness of the amorphous oxide semiconductor layer 13 occurs, and the contact resistance increases.

From the above results, the grain size of the crystal grains 13cg is preferably 15 nm or less. Further, the crystal grain existence region (Tcg) is preferably within 20 nm from the surface of the amorphous oxide semiconductor layer 13, more preferably within 10 nm.

Thus, according to the thin film transistor of this embodiment, the contact resistance between the amorphous oxide semiconductor layer 13, the source electrode 14s, and the drain electrode 14d can be reduced. Accordingly, an on-current (Ion) is improved and field effect mobility is improved, so that a high-performance thin film transistor can be provided. Thereby, for example, an RFID tag that operates in a 13.56 MHz band can be realized.

In this embodiment, when the conductive film 14 is deposited by the electron beam evaporation method, the crystal grains 13cg are formed in the amorphous oxide semiconductor layer 13 only by setting the acceleration voltage of the electron beam to a value higher than usual. Since it forms, the special process and apparatus for forming the crystal grain 13cg are unnecessary.

(Embodiment 2)
The thin film transistor can also be manufactured by the following method. First, as shown in FIG. 12, the gate electrode 11, the gate insulating film 12, and the amorphous oxide semiconductor layer 13 are formed in this order on the upper surface of the insulating substrate 10. The steps so far are the same as the steps shown in FIGS. 1 to 4 of the first embodiment.

Next, as shown in FIG. 13, a conductive film 14 is deposited on the amorphous oxide semiconductor layer 13. Examples of the conductive film 14 include various conductive films that constitute the gate electrode 11 described above. In the present embodiment, the conductive film (Al film) 14 is deposited using a sputtering apparatus with the voltage applied between the substrate 10 and the conductive film material (target) set to a value higher than usual.

In this way, accelerated ions and electrons collide with the target at a higher speed than usual, and the target particles collide with the surface of the amorphous oxide semiconductor layer 13 with high energy, thereby forming the amorphous oxide semiconductor layer 13. A part of the oxide is crystallized by the energy to generate crystal grains 13cg. In this embodiment, since the channel layer region (region above the gate electrode 11) of the amorphous oxide semiconductor layer 13 is not covered with the barrier layer 15 (see FIG. 5), the crystal is also formed near the surface of the channel layer region. Grains 13cg are formed.

When depositing the conductive film 14 using the sputtering method, assist ions (for example, Ar ⁺ ) are added into the chamber of the sputtering apparatus, and the assist ions collide with the surface of the amorphous oxide semiconductor layer 13 at a high speed. The crystal grains 13cg can also be formed. Prior to the step of depositing the conductive film 14 by the electron beam evaporation method (Embodiment 1) or the sputtering method (Embodiment 2), the surface of the amorphous oxide semiconductor layer 13 is irradiated with a high-energy laser beam. Thus, the crystal grains 13cg can be formed.

As in the first embodiment, the crystal grain 13cg preferably has a particle size of 15 nm or less. Further, the crystal grain existence region (Tcg) is preferably within 20 nm from the surface of the oxide semiconductor layer 13, and more preferably within 10 nm.

Next, as shown in FIG. 14, the source electrode 14s and the drain electrode 14d are formed by removing the conductive film 14 above the gate electrode 11 by dry etching using the photoresist film 16 as a mask. At this time, in this embodiment, following removal of the conductive film 14, the amorphous oxide semiconductor layer 13 therebelow is over-etched to remove the crystal grains 13cg formed near the surface of the channel layer region.

The bottom gate / top contact type thin film transistor of this embodiment is completed through the steps so far. The thin film transistor has a channel length of 0.1 mm and a channel width of 2 mm.

Next, when a voltage applied between the substrate 10 and the conductive film material (target) was set as usual, a thin film transistor in which the conductive film (Al film) 14 was deposited was produced, and the on-current (Ion) was compared. The thin film transistor of this embodiment exhibited an on-current (Ion) that is twice or more that of the thin film transistor of the comparative example.

Further, when a cross-sectional TEM photograph in the vicinity of the interface between the drain electrode 14d and the amorphous oxide semiconductor layer 13 in the thin film transistor of this embodiment was observed, a crystal grain existence region (Tcg) within a depth of 10 nm from the interface with the drain electrode 14d was observed. It was confirmed that the crystal grains 13cg were present in a line. It was also confirmed at the same time that the region other than the region where the crystal grains 13cg were formed was in an amorphous state. On the other hand, the presence of the crystal grains 13cg could not be confirmed from the cross-sectional TEM photograph of the thin film transistor of the comparative example.

When the crystal structure was examined by FFT diffraction from the TEM image of the crystal grain 13cg, it was different depending on the constituent elements of the selected amorphous oxide semiconductor layer 13, but some constituent elements were mainly composed of ZnSnO ₃ and In ₂ O _3. Was confirmed to have a crystal structure substituted with other constituent elements. Thus, the constituent element of the crystal grain 13cg is not only the same as the constituent element of the amorphous oxide semiconductor layer 13, but may be at least a part of the constituent element of the amorphous oxide semiconductor layer 13.

According to the present embodiment, it is possible to provide a high-performance thin film transistor, as in the first embodiment. Further, in this embodiment, the step of forming the barrier layer 15 on the channel layer region of the amorphous oxide semiconductor layer 13 is not necessary, so that a high-performance thin film transistor can be manufactured with fewer steps.

In the manufacturing method of the present embodiment, when the conductive film 14 for the source and drain electrodes is patterned by dry etching, the amorphous oxide semiconductor layer 13 below the conductive film 14 is over-etched so that the surface of the channel layer region is near the surface. Crystal grains 13cg were removed. However, at this time, if the amount of overetching of the amorphous oxide semiconductor layer 13 varies, the film thickness of the channel layer varies, and the characteristics of the thin film transistor may vary.

As a measure for preventing the above problem, as shown in FIG. 15, the amorphous oxide semiconductor layer 13 has a stacked structure of a first oxide semiconductor layer 13 </ b> A and a second oxide semiconductor layer 13 </ b> B. The layer 13A is made of an oxide of an element that can use s-orbital electrons as carriers, such as In or Sn. Further, it is considered that the upper second oxide semiconductor layer 13B to be over-etched is made of a high resistance oxide having an oxygen concentration higher than that of the oxide constituting the lower first oxide semiconductor layer 13A. . As a specific example, the lower first oxide semiconductor layer 13A is made of SnOx, and the upper second oxide semiconductor layer 13B is made of ZnSnOx.

In this way, the lower first oxide semiconductor layer 13A having a lower electrical resistance than the upper second oxide semiconductor layer 13B substantially functions as a channel layer, so that the upper second oxide semiconductor layer 13B Even if the amount of overetching varies, variation in characteristics of the thin film transistor can be suppressed.

(Embodiment 3)
FIG. 16 is a cross-sectional view illustrating the thin film transistor of this embodiment. The thin film transistor of this embodiment is characterized in that crystal grains 13cg are formed not only in the vicinity of the interface between the source electrode 14s and the drain electrode 14d but also in the channel layer of the amorphous oxide semiconductor layer 13.

The manufacturing method of the thin film transistor of this embodiment is almost the same as the manufacturing method of Embodiment 2 described above. When the conductive film 14 for the source and drain electrodes is patterned by dry etching, the amorphous structure under the conductive film 14 is formed. The only difference is that the oxide semiconductor layer 13 is not over-etched.

When a cross-sectional TEM photograph in the vicinity of the interface between the drain electrode 14d and the amorphous oxide semiconductor layer 13 in the thin film transistor of this embodiment is observed, a crystal grain existing region (Tcg) within a depth of 10 nm from the interface with the drain electrode 14d is observed. It was confirmed that the crystal grains 13cg existed in a line.

FIG. 17 is a graph showing the relationship between the threshold gate voltage (Vg) and the drain current (Id) of the thin film transistor of this embodiment. Here, the solid line C is obtained when the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less (here, 6 nm), and the broken line D is the film thickness (tch) of the amorphous oxide semiconductor layer 13. ) Is thicker than 10 nm.

When the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less, a good on-current (Ion) value is shown, and compared with a conventional thin film transistor that does not form crystal grains 13 cg in the amorphous oxide semiconductor layer 13. The on-current (Ion) more than twice. Further, when a cross-sectional TEM photograph in the vicinity of the channel layer of this thin film transistor was observed, crystal grains 13cg having a grain size of 5 nm or less were confirmed. On the other hand, when the film thickness (tch) of the amorphous oxide semiconductor layer 13 is greater than 10 nm, the amorphous oxide semiconductor layer 13 cannot be turned off even when the gate voltage is −50 V, and behaves like a conductive film.

From the above, in the thin film transistor in which the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less, even when the crystal grain 13cg is formed in the channel layer, the on-current (Ion) is improved, and the field effect It can be seen that the mobility is improved.

(Embodiment 4)
FIG. 18 shows a schematic configuration of an RFID tag 20 in which an antenna resonance circuit 21, a rectifier 22, a modulator 23, a digital circuit 24, and the like are configured using the thin film transistor of the present invention.

The RFID tag 20 can communicate with an external reader / writer 25 wirelessly using a high frequency of 13.56 MHz, for example. Further, since the oxide semiconductor layer constituting the channel layer of the thin film transistor is a transparent material, an almost transparent circuit can be formed in the IC chip.

For example, a transparent wireless IC tag that transmits and receives at a high frequency (RF) of 13.56 MHz, for example, by configuring electrodes and wiring of an IC chip with a transparent conductive film such as ITO and circuit elements with the thin film transistor of the present invention. Can be produced. Such a wireless IC tag is different from a conventional RFID tag in that an IC chip and an antenna are almost transparent. Therefore, when the wireless IC tag is attached to a film or a card, the design printed on the film or the card is not damaged. .

(Embodiment 5)
FIG. 19 is a circuit block diagram showing an example of an array configuration of a semiconductor device using the thin film transistor of the present invention. The semiconductor device of this embodiment has a configuration in which elements including the thin film transistor of the present invention are arranged on a substrate 30 in an array. Of course, the thin film transistor is used as a switching transistor or a driving transistor for each element in the array, as well as a gate line driving circuit 32 for sending a signal to the gate wiring 31 connected to the gate electrode (11) of the thin film transistor, You may use for the transistor which comprises the data line drive circuit 34 which sends a signal to the data wiring 33 connected with a source electrode and a drain electrode. In this case, the thin film transistor of each element and the thin film transistor in the gate line driving circuit 32 or the data line driving circuit 34 can be formed in parallel.

When the above-described array is applied to an active matrix liquid crystal display device, each element has a configuration as shown in FIG. 20, for example. When a scanning signal is supplied to the gate wiring 31 extending in the x direction in the figure, the thin film transistor 35 is turned on, and the image from the data wiring 33 extending in the y direction in the figure through the turned on thin film transistor 35. A signal is supplied to the pixel electrode 36.

The gate lines 31 are arranged in parallel in the y direction in the figure, and the data lines 33 are arranged in parallel in the x direction in the figure and are surrounded by a pair of adjacent gate lines 31 and a pair of adjacent data lines 33. A pixel electrode 36 is arranged in the area (pixel area). In this case, for example, the data line 33 is electrically connected to the source electrode, and the pixel electrode 36 is electrically connected to the drain electrode. Alternatively, the data wiring 33 may also serve as the source electrode. Further, the above-described array may be applied not only to the liquid crystal display device but also to an organic EL display device or the like. In this case, a thin film transistor is applied to a transistor included in the pixel circuit. Furthermore, the above-described array may be applied to the memory element, and a thin film transistor may be applied to the selection transistor.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The present invention can be applied to a semiconductor device having a thin film transistor using an oxide semiconductor material for a channel layer.

10 substrate 11 gate electrode 12 gate insulating film 13 amorphous oxide semiconductor layer 13A first oxide semiconductor layer 13B second oxide semiconductor layer 13cg crystal grain 14 conductive film 14d drain electrode 14s source electrode 15 barrier layer 16 photoresist film 20 RFID Tag 21 Antenna resonance circuit 22 Rectifier 23 Modulator 24 Digital circuit 25 Reader / writer 30 Substrate 31 Gate wiring 32 Gate line driving circuit 33 Data wiring 34 Data line driving circuit 35 Thin film transistor 36 Pixel electrode

Claims

Provided with a thin film transistor in which a gate electrode, a gate insulating film, an amorphous oxide semiconductor layer constituting a channel layer, a source and a drain electrode are laminated in this order on the upper surface of the substrate,
An oxide semiconductor device comprising crystal grains containing constituent elements of the amorphous oxide semiconductor layer in the amorphous oxide semiconductor layer in the vicinity of the interface with the source and drain electrodes.
The amorphous oxide semiconductor layer is made of an oxide in which any one or more elements of In, Zn, Cd, Al, Ga, Si, Sn, Ce, Ge, and Hf are combined with oxygen. The oxide semiconductor device according to claim 1.
The film thickness of the amorphous oxide semiconductor layer is 25 nm or more, and the crystal grains exist in a region from the surface of the amorphous oxide semiconductor layer to a depth of 20 nm. Oxide semiconductor device.
4. The oxide semiconductor device according to claim 3, wherein a grain size of the crystal grains is 15 nm or less.
2. The oxide semiconductor device according to claim 1, wherein a film thickness of the amorphous oxide semiconductor layer is 10 nm or less, and the crystal grains are also present in a channel layer of the amorphous oxide semiconductor layer.
The amorphous oxide semiconductor layer includes a first amorphous oxide semiconductor layer made of a first oxide, and a second oxygen concentration lower than that of the first oxide, formed on the first amorphous oxide semiconductor layer. The oxide semiconductor device according to claim 1, wherein the oxide semiconductor device has a stacked structure with a second amorphous oxide semiconductor layer made of an oxide.
A method for manufacturing an oxide semiconductor device having a thin film transistor using an oxide semiconductor material for a channel layer,
(A) forming a gate electrode on the upper surface of the substrate;
(B) forming a gate insulating film on the gate electrode;
(C) forming an amorphous oxide semiconductor layer on the gate insulating film;
(D) forming a barrier layer on the channel layer region of the amorphous oxide semiconductor layer;
(E) forming a conductive film on the amorphous oxide semiconductor layer and the barrier layer;
(F) forming the source and drain electrodes made of the conductive film on the amorphous oxide semiconductor layer on both sides of the channel layer region by removing the conductive film above the channel layer region;
Have
When depositing the conductive film in the step (e), using the energy of accelerated particles incident on the amorphous oxide semiconductor layer, in the amorphous oxide semiconductor layer in the vicinity of the interface with the source and drain electrodes, A method for manufacturing an oxide semiconductor device, comprising forming a crystal grain containing a constituent element of the amorphous oxide semiconductor layer.
A method for manufacturing an oxide semiconductor device having a thin film transistor using an oxide semiconductor material for a channel layer,
(A) forming a gate electrode on the upper surface of the substrate;
(B) forming a gate insulating film on the gate electrode;
(C) forming an amorphous oxide semiconductor layer on the gate insulating film;
(D) forming a conductive film on the amorphous oxide semiconductor layer;
(E) forming the source and drain electrodes made of the conductive film on the amorphous oxide semiconductor layer on both sides of the channel layer region by removing the conductive film above the gate electrode by etching;
Have
When depositing the conductive film in the step (d), using the energy of accelerated particles incident on the amorphous oxide semiconductor layer, the amorphous oxide semiconductor layer in the vicinity of the interface with the source and drain electrodes, Forming crystal grains containing the constituent elements of the amorphous oxide semiconductor layer;
When etching the conductive film in the step (e), the crystal grains formed in the channel layer region are removed by over-etching the vicinity of the surface of the amorphous oxide semiconductor layer. For manufacturing a semiconductor device.
The amorphous oxide semiconductor layer is made of an oxide in which any one or more elements of In, Zn, Cd, Al, Ga, Si, Sn, Ce, Ge, and Hf are combined with oxygen. A method for manufacturing an oxide semiconductor device according to claim 7.
8. The method of manufacturing an oxide semiconductor device according to claim 7, wherein the conductive film is deposited by an electron beam evaporation method or a sputtering method.
The film thickness of the amorphous oxide semiconductor layer is 25 nm or more, and the crystal grains exist in a region from the surface of the amorphous oxide semiconductor layer to a depth of 20 nm. Manufacturing method of oxide semiconductor device.
The method for manufacturing an oxide semiconductor device according to claim 7, wherein the crystal grains have a particle size of 15 nm or less.